14f04d8f0SCatalin Marinas /* 24f04d8f0SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 34f04d8f0SCatalin Marinas * 44f04d8f0SCatalin Marinas * This program is free software; you can redistribute it and/or modify 54f04d8f0SCatalin Marinas * it under the terms of the GNU General Public License version 2 as 64f04d8f0SCatalin Marinas * published by the Free Software Foundation. 74f04d8f0SCatalin Marinas * 84f04d8f0SCatalin Marinas * This program is distributed in the hope that it will be useful, 94f04d8f0SCatalin Marinas * but WITHOUT ANY WARRANTY; without even the implied warranty of 104f04d8f0SCatalin Marinas * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 114f04d8f0SCatalin Marinas * GNU General Public License for more details. 124f04d8f0SCatalin Marinas * 134f04d8f0SCatalin Marinas * You should have received a copy of the GNU General Public License 144f04d8f0SCatalin Marinas * along with this program. If not, see <http://www.gnu.org/licenses/>. 154f04d8f0SCatalin Marinas */ 164f04d8f0SCatalin Marinas #ifndef __ASM_PGTABLE_HWDEF_H 174f04d8f0SCatalin Marinas #define __ASM_PGTABLE_HWDEF_H 184f04d8f0SCatalin Marinas 19686e7838SSuzuki K. Poulose /* 20686e7838SSuzuki K. Poulose * Number of page-table levels required to address 'va_bits' wide 21686e7838SSuzuki K. Poulose * address, without section mapping. We resolve the top (va_bits - PAGE_SHIFT) 22686e7838SSuzuki K. Poulose * bits with (PAGE_SHIFT - 3) bits at each page table level. Hence: 23686e7838SSuzuki K. Poulose * 24686e7838SSuzuki K. Poulose * levels = DIV_ROUND_UP((va_bits - PAGE_SHIFT), (PAGE_SHIFT - 3)) 25686e7838SSuzuki K. Poulose * 26686e7838SSuzuki K. Poulose * where DIV_ROUND_UP(n, d) => (((n) + (d) - 1) / (d)) 27686e7838SSuzuki K. Poulose * 28686e7838SSuzuki K. Poulose * We cannot include linux/kernel.h which defines DIV_ROUND_UP here 29686e7838SSuzuki K. Poulose * due to build issues. So we open code DIV_ROUND_UP here: 30686e7838SSuzuki K. Poulose * 31686e7838SSuzuki K. Poulose * ((((va_bits) - PAGE_SHIFT) + (PAGE_SHIFT - 3) - 1) / (PAGE_SHIFT - 3)) 32686e7838SSuzuki K. Poulose * 33686e7838SSuzuki K. Poulose * which gets simplified as : 34686e7838SSuzuki K. Poulose */ 35686e7838SSuzuki K. Poulose #define ARM64_HW_PGTABLE_LEVELS(va_bits) (((va_bits) - 4) / (PAGE_SHIFT - 3)) 36686e7838SSuzuki K. Poulose 37686e7838SSuzuki K. Poulose /* 38686e7838SSuzuki K. Poulose * Size mapped by an entry at level n ( 0 <= n <= 3) 39686e7838SSuzuki K. Poulose * We map (PAGE_SHIFT - 3) at all translation levels and PAGE_SHIFT bits 40686e7838SSuzuki K. Poulose * in the final page. The maximum number of translation levels supported by 41686e7838SSuzuki K. Poulose * the architecture is 4. Hence, starting at at level n, we have further 42686e7838SSuzuki K. Poulose * ((4 - n) - 1) levels of translation excluding the offset within the page. 43686e7838SSuzuki K. Poulose * So, the total number of bits mapped by an entry at level n is : 44686e7838SSuzuki K. Poulose * 45686e7838SSuzuki K. Poulose * ((4 - n) - 1) * (PAGE_SHIFT - 3) + PAGE_SHIFT 46686e7838SSuzuki K. Poulose * 47686e7838SSuzuki K. Poulose * Rearranging it a bit we get : 48686e7838SSuzuki K. Poulose * (4 - n) * (PAGE_SHIFT - 3) + 3 49686e7838SSuzuki K. Poulose */ 50686e7838SSuzuki K. Poulose #define ARM64_HW_PGTABLE_LEVEL_SHIFT(n) ((PAGE_SHIFT - 3) * (4 - (n)) + 3) 51686e7838SSuzuki K. Poulose 526b4fee24SCatalin Marinas #define PTRS_PER_PTE (1 << (PAGE_SHIFT - 3)) 536b4fee24SCatalin Marinas 546b4fee24SCatalin Marinas /* 556b4fee24SCatalin Marinas * PMD_SHIFT determines the size a level 2 page table entry can map. 566b4fee24SCatalin Marinas */ 579f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 2 58686e7838SSuzuki K. Poulose #define PMD_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(2) 596b4fee24SCatalin Marinas #define PMD_SIZE (_AC(1, UL) << PMD_SHIFT) 606b4fee24SCatalin Marinas #define PMD_MASK (~(PMD_SIZE-1)) 616b4fee24SCatalin Marinas #define PTRS_PER_PMD PTRS_PER_PTE 624f04d8f0SCatalin Marinas #endif 634f04d8f0SCatalin Marinas 644f04d8f0SCatalin Marinas /* 656b4fee24SCatalin Marinas * PUD_SHIFT determines the size a level 1 page table entry can map. 666b4fee24SCatalin Marinas */ 679f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 3 68686e7838SSuzuki K. Poulose #define PUD_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(1) 696b4fee24SCatalin Marinas #define PUD_SIZE (_AC(1, UL) << PUD_SHIFT) 706b4fee24SCatalin Marinas #define PUD_MASK (~(PUD_SIZE-1)) 716b4fee24SCatalin Marinas #define PTRS_PER_PUD PTRS_PER_PTE 726b4fee24SCatalin Marinas #endif 736b4fee24SCatalin Marinas 746b4fee24SCatalin Marinas /* 756b4fee24SCatalin Marinas * PGDIR_SHIFT determines the size a top-level page table entry can map 766b4fee24SCatalin Marinas * (depending on the configuration, this level can be 0, 1 or 2). 776b4fee24SCatalin Marinas */ 78686e7838SSuzuki K. Poulose #define PGDIR_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - CONFIG_PGTABLE_LEVELS) 796b4fee24SCatalin Marinas #define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT) 806b4fee24SCatalin Marinas #define PGDIR_MASK (~(PGDIR_SIZE-1)) 816b4fee24SCatalin Marinas #define PTRS_PER_PGD (1 << (VA_BITS - PGDIR_SHIFT)) 826b4fee24SCatalin Marinas 836b4fee24SCatalin Marinas /* 846b4fee24SCatalin Marinas * Section address mask and size definitions. 856b4fee24SCatalin Marinas */ 866b4fee24SCatalin Marinas #define SECTION_SHIFT PMD_SHIFT 876b4fee24SCatalin Marinas #define SECTION_SIZE (_AC(1, UL) << SECTION_SHIFT) 886b4fee24SCatalin Marinas #define SECTION_MASK (~(SECTION_SIZE-1)) 896b4fee24SCatalin Marinas 906b4fee24SCatalin Marinas /* 91ecf35a23SJeremy Linton * Contiguous page definitions. 92ecf35a23SJeremy Linton */ 9366b3923aSDavid Woods #ifdef CONFIG_ARM64_64K_PAGES 9466b3923aSDavid Woods #define CONT_PTE_SHIFT 5 9566b3923aSDavid Woods #define CONT_PMD_SHIFT 5 9666b3923aSDavid Woods #elif defined(CONFIG_ARM64_16K_PAGES) 9766b3923aSDavid Woods #define CONT_PTE_SHIFT 7 9866b3923aSDavid Woods #define CONT_PMD_SHIFT 5 9966b3923aSDavid Woods #else 10066b3923aSDavid Woods #define CONT_PTE_SHIFT 4 10166b3923aSDavid Woods #define CONT_PMD_SHIFT 4 10266b3923aSDavid Woods #endif 10366b3923aSDavid Woods 10466b3923aSDavid Woods #define CONT_PTES (1 << CONT_PTE_SHIFT) 10566b3923aSDavid Woods #define CONT_PTE_SIZE (CONT_PTES * PAGE_SIZE) 10666b3923aSDavid Woods #define CONT_PTE_MASK (~(CONT_PTE_SIZE - 1)) 10766b3923aSDavid Woods #define CONT_PMDS (1 << CONT_PMD_SHIFT) 10866b3923aSDavid Woods #define CONT_PMD_SIZE (CONT_PMDS * PMD_SIZE) 10966b3923aSDavid Woods #define CONT_PMD_MASK (~(CONT_PMD_SIZE - 1)) 110ecf35a23SJeremy Linton /* the the numerical offset of the PTE within a range of CONT_PTES */ 111ecf35a23SJeremy Linton #define CONT_RANGE_OFFSET(addr) (((addr)>>PAGE_SHIFT)&(CONT_PTES-1)) 112ecf35a23SJeremy Linton 113ecf35a23SJeremy Linton /* 1144f04d8f0SCatalin Marinas * Hardware page table definitions. 1154f04d8f0SCatalin Marinas * 116084bd298SSteve Capper * Level 1 descriptor (PUD). 117084bd298SSteve Capper */ 118c79b954bSJungseok Lee #define PUD_TYPE_TABLE (_AT(pudval_t, 3) << 0) 119084bd298SSteve Capper #define PUD_TABLE_BIT (_AT(pgdval_t, 1) << 1) 120206a2a73SSteve Capper #define PUD_TYPE_MASK (_AT(pgdval_t, 3) << 0) 121206a2a73SSteve Capper #define PUD_TYPE_SECT (_AT(pgdval_t, 1) << 0) 122084bd298SSteve Capper 123084bd298SSteve Capper /* 1244f04d8f0SCatalin Marinas * Level 2 descriptor (PMD). 1254f04d8f0SCatalin Marinas */ 1264f04d8f0SCatalin Marinas #define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0) 1274f04d8f0SCatalin Marinas #define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0) 1284f04d8f0SCatalin Marinas #define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0) 1294f04d8f0SCatalin Marinas #define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0) 130084bd298SSteve Capper #define PMD_TABLE_BIT (_AT(pmdval_t, 1) << 1) 1314f04d8f0SCatalin Marinas 1324f04d8f0SCatalin Marinas /* 1334f04d8f0SCatalin Marinas * Section 1344f04d8f0SCatalin Marinas */ 135af074848SSteve Capper #define PMD_SECT_VALID (_AT(pmdval_t, 1) << 0) 136af074848SSteve Capper #define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */ 137af074848SSteve Capper #define PMD_SECT_RDONLY (_AT(pmdval_t, 1) << 7) /* AP[2] */ 1384f04d8f0SCatalin Marinas #define PMD_SECT_S (_AT(pmdval_t, 3) << 8) 1394f04d8f0SCatalin Marinas #define PMD_SECT_AF (_AT(pmdval_t, 1) << 10) 1404f04d8f0SCatalin Marinas #define PMD_SECT_NG (_AT(pmdval_t, 1) << 11) 141ecf35a23SJeremy Linton #define PMD_SECT_CONT (_AT(pmdval_t, 1) << 52) 1428e620b04SCatalin Marinas #define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53) 1438e620b04SCatalin Marinas #define PMD_SECT_UXN (_AT(pmdval_t, 1) << 54) 1444f04d8f0SCatalin Marinas 1454f04d8f0SCatalin Marinas /* 1464f04d8f0SCatalin Marinas * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 1474f04d8f0SCatalin Marinas */ 1484f04d8f0SCatalin Marinas #define PMD_ATTRINDX(t) (_AT(pmdval_t, (t)) << 2) 1494f04d8f0SCatalin Marinas #define PMD_ATTRINDX_MASK (_AT(pmdval_t, 7) << 2) 1504f04d8f0SCatalin Marinas 1514f04d8f0SCatalin Marinas /* 1524f04d8f0SCatalin Marinas * Level 3 descriptor (PTE). 1534f04d8f0SCatalin Marinas */ 1544f04d8f0SCatalin Marinas #define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0) 1554f04d8f0SCatalin Marinas #define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0) 1564f04d8f0SCatalin Marinas #define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0) 157084bd298SSteve Capper #define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1) 1584f04d8f0SCatalin Marinas #define PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ 1594f04d8f0SCatalin Marinas #define PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */ 1604f04d8f0SCatalin Marinas #define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ 1614f04d8f0SCatalin Marinas #define PTE_AF (_AT(pteval_t, 1) << 10) /* Access Flag */ 1624f04d8f0SCatalin Marinas #define PTE_NG (_AT(pteval_t, 1) << 11) /* nG */ 1632f4b829cSCatalin Marinas #define PTE_DBM (_AT(pteval_t, 1) << 51) /* Dirty Bit Management */ 164ecf35a23SJeremy Linton #define PTE_CONT (_AT(pteval_t, 1) << 52) /* Contiguous range */ 1658e620b04SCatalin Marinas #define PTE_PXN (_AT(pteval_t, 1) << 53) /* Privileged XN */ 1668e620b04SCatalin Marinas #define PTE_UXN (_AT(pteval_t, 1) << 54) /* User XN */ 1671166f3feSMarc Zyngier #define PTE_HYP_XN (_AT(pteval_t, 1) << 54) /* HYP XN */ 1684f04d8f0SCatalin Marinas 1694f04d8f0SCatalin Marinas /* 1704f04d8f0SCatalin Marinas * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 1714f04d8f0SCatalin Marinas */ 1724f04d8f0SCatalin Marinas #define PTE_ATTRINDX(t) (_AT(pteval_t, (t)) << 2) 1734f04d8f0SCatalin Marinas #define PTE_ATTRINDX_MASK (_AT(pteval_t, 7) << 2) 1744f04d8f0SCatalin Marinas 1754f04d8f0SCatalin Marinas /* 17636311607SMarc Zyngier * 2nd stage PTE definitions 17736311607SMarc Zyngier */ 17836311607SMarc Zyngier #define PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[2:1] */ 17936311607SMarc Zyngier #define PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */ 18036311607SMarc Zyngier 1818199ed0eSMario Smarduch #define PMD_S2_RDONLY (_AT(pmdval_t, 1) << 6) /* HAP[2:1] */ 182ad361f09SChristoffer Dall #define PMD_S2_RDWR (_AT(pmdval_t, 3) << 6) /* HAP[2:1] */ 183ad361f09SChristoffer Dall 18436311607SMarc Zyngier /* 18536311607SMarc Zyngier * Memory Attribute override for Stage-2 (MemAttr[3:0]) 18636311607SMarc Zyngier */ 18736311607SMarc Zyngier #define PTE_S2_MEMATTR(t) (_AT(pteval_t, (t)) << 2) 18836311607SMarc Zyngier #define PTE_S2_MEMATTR_MASK (_AT(pteval_t, 0xf) << 2) 18936311607SMarc Zyngier 19036311607SMarc Zyngier /* 19136311607SMarc Zyngier * EL2/HYP PTE/PMD definitions 19236311607SMarc Zyngier */ 19336311607SMarc Zyngier #define PMD_HYP PMD_SECT_USER 19436311607SMarc Zyngier #define PTE_HYP PTE_USER 19536311607SMarc Zyngier 19636311607SMarc Zyngier /* 19787366d8cSRadha Mohan Chintakuntla * Highest possible physical address supported. 1984f04d8f0SCatalin Marinas */ 199*982aa7c5SKristina Martsenko #define PHYS_MASK_SHIFT (CONFIG_ARM64_PA_BITS) 2004f04d8f0SCatalin Marinas #define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1) 2014f04d8f0SCatalin Marinas 2024f04d8f0SCatalin Marinas /* 2034f04d8f0SCatalin Marinas * TCR flags. 2044f04d8f0SCatalin Marinas */ 205dd006da2SArd Biesheuvel #define TCR_T0SZ_OFFSET 0 206dd006da2SArd Biesheuvel #define TCR_T1SZ_OFFSET 16 207dd006da2SArd Biesheuvel #define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_T0SZ_OFFSET) 208dd006da2SArd Biesheuvel #define TCR_T1SZ(x) ((UL(64) - (x)) << TCR_T1SZ_OFFSET) 209dd006da2SArd Biesheuvel #define TCR_TxSZ(x) (TCR_T0SZ(x) | TCR_T1SZ(x)) 210dd006da2SArd Biesheuvel #define TCR_TxSZ_WIDTH 6 211adf75899SMark Rutland #define TCR_T0SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET) 212a563f759SSuzuki K Poulose 213a563f759SSuzuki K Poulose #define TCR_IRGN0_SHIFT 8 214a563f759SSuzuki K Poulose #define TCR_IRGN0_MASK (UL(3) << TCR_IRGN0_SHIFT) 215a563f759SSuzuki K Poulose #define TCR_IRGN0_NC (UL(0) << TCR_IRGN0_SHIFT) 216a563f759SSuzuki K Poulose #define TCR_IRGN0_WBWA (UL(1) << TCR_IRGN0_SHIFT) 217a563f759SSuzuki K Poulose #define TCR_IRGN0_WT (UL(2) << TCR_IRGN0_SHIFT) 218a563f759SSuzuki K Poulose #define TCR_IRGN0_WBnWA (UL(3) << TCR_IRGN0_SHIFT) 219a563f759SSuzuki K Poulose 220a563f759SSuzuki K Poulose #define TCR_IRGN1_SHIFT 24 221a563f759SSuzuki K Poulose #define TCR_IRGN1_MASK (UL(3) << TCR_IRGN1_SHIFT) 222a563f759SSuzuki K Poulose #define TCR_IRGN1_NC (UL(0) << TCR_IRGN1_SHIFT) 223a563f759SSuzuki K Poulose #define TCR_IRGN1_WBWA (UL(1) << TCR_IRGN1_SHIFT) 224a563f759SSuzuki K Poulose #define TCR_IRGN1_WT (UL(2) << TCR_IRGN1_SHIFT) 225a563f759SSuzuki K Poulose #define TCR_IRGN1_WBnWA (UL(3) << TCR_IRGN1_SHIFT) 226a563f759SSuzuki K Poulose 227a563f759SSuzuki K Poulose #define TCR_IRGN_NC (TCR_IRGN0_NC | TCR_IRGN1_NC) 228a563f759SSuzuki K Poulose #define TCR_IRGN_WBWA (TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) 229a563f759SSuzuki K Poulose #define TCR_IRGN_WT (TCR_IRGN0_WT | TCR_IRGN1_WT) 230a563f759SSuzuki K Poulose #define TCR_IRGN_WBnWA (TCR_IRGN0_WBnWA | TCR_IRGN1_WBnWA) 231a563f759SSuzuki K Poulose #define TCR_IRGN_MASK (TCR_IRGN0_MASK | TCR_IRGN1_MASK) 232a563f759SSuzuki K Poulose 233a563f759SSuzuki K Poulose 234a563f759SSuzuki K Poulose #define TCR_ORGN0_SHIFT 10 235a563f759SSuzuki K Poulose #define TCR_ORGN0_MASK (UL(3) << TCR_ORGN0_SHIFT) 236a563f759SSuzuki K Poulose #define TCR_ORGN0_NC (UL(0) << TCR_ORGN0_SHIFT) 237a563f759SSuzuki K Poulose #define TCR_ORGN0_WBWA (UL(1) << TCR_ORGN0_SHIFT) 238a563f759SSuzuki K Poulose #define TCR_ORGN0_WT (UL(2) << TCR_ORGN0_SHIFT) 239a563f759SSuzuki K Poulose #define TCR_ORGN0_WBnWA (UL(3) << TCR_ORGN0_SHIFT) 240a563f759SSuzuki K Poulose 241a563f759SSuzuki K Poulose #define TCR_ORGN1_SHIFT 26 242a563f759SSuzuki K Poulose #define TCR_ORGN1_MASK (UL(3) << TCR_ORGN1_SHIFT) 243a563f759SSuzuki K Poulose #define TCR_ORGN1_NC (UL(0) << TCR_ORGN1_SHIFT) 244a563f759SSuzuki K Poulose #define TCR_ORGN1_WBWA (UL(1) << TCR_ORGN1_SHIFT) 245a563f759SSuzuki K Poulose #define TCR_ORGN1_WT (UL(2) << TCR_ORGN1_SHIFT) 246a563f759SSuzuki K Poulose #define TCR_ORGN1_WBnWA (UL(3) << TCR_ORGN1_SHIFT) 247a563f759SSuzuki K Poulose 248a563f759SSuzuki K Poulose #define TCR_ORGN_NC (TCR_ORGN0_NC | TCR_ORGN1_NC) 249a563f759SSuzuki K Poulose #define TCR_ORGN_WBWA (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA) 250a563f759SSuzuki K Poulose #define TCR_ORGN_WT (TCR_ORGN0_WT | TCR_ORGN1_WT) 251a563f759SSuzuki K Poulose #define TCR_ORGN_WBnWA (TCR_ORGN0_WBnWA | TCR_ORGN1_WBnWA) 252a563f759SSuzuki K Poulose #define TCR_ORGN_MASK (TCR_ORGN0_MASK | TCR_ORGN1_MASK) 253a563f759SSuzuki K Poulose 254a563f759SSuzuki K Poulose #define TCR_SH0_SHIFT 12 255a563f759SSuzuki K Poulose #define TCR_SH0_MASK (UL(3) << TCR_SH0_SHIFT) 256a563f759SSuzuki K Poulose #define TCR_SH0_INNER (UL(3) << TCR_SH0_SHIFT) 257a563f759SSuzuki K Poulose 258a563f759SSuzuki K Poulose #define TCR_SH1_SHIFT 28 259a563f759SSuzuki K Poulose #define TCR_SH1_MASK (UL(3) << TCR_SH1_SHIFT) 260a563f759SSuzuki K Poulose #define TCR_SH1_INNER (UL(3) << TCR_SH1_SHIFT) 261a563f759SSuzuki K Poulose #define TCR_SHARED (TCR_SH0_INNER | TCR_SH1_INNER) 262a563f759SSuzuki K Poulose 263a563f759SSuzuki K Poulose #define TCR_TG0_SHIFT 14 264a563f759SSuzuki K Poulose #define TCR_TG0_MASK (UL(3) << TCR_TG0_SHIFT) 265a563f759SSuzuki K Poulose #define TCR_TG0_4K (UL(0) << TCR_TG0_SHIFT) 266a563f759SSuzuki K Poulose #define TCR_TG0_64K (UL(1) << TCR_TG0_SHIFT) 267a563f759SSuzuki K Poulose #define TCR_TG0_16K (UL(2) << TCR_TG0_SHIFT) 268a563f759SSuzuki K Poulose 269a563f759SSuzuki K Poulose #define TCR_TG1_SHIFT 30 270a563f759SSuzuki K Poulose #define TCR_TG1_MASK (UL(3) << TCR_TG1_SHIFT) 271a563f759SSuzuki K Poulose #define TCR_TG1_16K (UL(1) << TCR_TG1_SHIFT) 272a563f759SSuzuki K Poulose #define TCR_TG1_4K (UL(2) << TCR_TG1_SHIFT) 273a563f759SSuzuki K Poulose #define TCR_TG1_64K (UL(3) << TCR_TG1_SHIFT) 274a563f759SSuzuki K Poulose 2754f04d8f0SCatalin Marinas #define TCR_ASID16 (UL(1) << 36) 276d50240a5SWill Deacon #define TCR_TBI0 (UL(1) << 37) 2772f4b829cSCatalin Marinas #define TCR_HA (UL(1) << 39) 2782f4b829cSCatalin Marinas #define TCR_HD (UL(1) << 40) 2794f04d8f0SCatalin Marinas 2804f04d8f0SCatalin Marinas #endif 281