14f04d8f0SCatalin Marinas /* 24f04d8f0SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 34f04d8f0SCatalin Marinas * 44f04d8f0SCatalin Marinas * This program is free software; you can redistribute it and/or modify 54f04d8f0SCatalin Marinas * it under the terms of the GNU General Public License version 2 as 64f04d8f0SCatalin Marinas * published by the Free Software Foundation. 74f04d8f0SCatalin Marinas * 84f04d8f0SCatalin Marinas * This program is distributed in the hope that it will be useful, 94f04d8f0SCatalin Marinas * but WITHOUT ANY WARRANTY; without even the implied warranty of 104f04d8f0SCatalin Marinas * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 114f04d8f0SCatalin Marinas * GNU General Public License for more details. 124f04d8f0SCatalin Marinas * 134f04d8f0SCatalin Marinas * You should have received a copy of the GNU General Public License 144f04d8f0SCatalin Marinas * along with this program. If not, see <http://www.gnu.org/licenses/>. 154f04d8f0SCatalin Marinas */ 164f04d8f0SCatalin Marinas #ifndef __ASM_PGTABLE_HWDEF_H 174f04d8f0SCatalin Marinas #define __ASM_PGTABLE_HWDEF_H 184f04d8f0SCatalin Marinas 194f04d8f0SCatalin Marinas #ifdef CONFIG_ARM64_64K_PAGES 204f04d8f0SCatalin Marinas #include <asm/pgtable-2level-hwdef.h> 214f04d8f0SCatalin Marinas #else 224f04d8f0SCatalin Marinas #include <asm/pgtable-3level-hwdef.h> 234f04d8f0SCatalin Marinas #endif 244f04d8f0SCatalin Marinas 254f04d8f0SCatalin Marinas /* 264f04d8f0SCatalin Marinas * Hardware page table definitions. 274f04d8f0SCatalin Marinas * 284f04d8f0SCatalin Marinas * Level 2 descriptor (PMD). 294f04d8f0SCatalin Marinas */ 304f04d8f0SCatalin Marinas #define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0) 314f04d8f0SCatalin Marinas #define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0) 324f04d8f0SCatalin Marinas #define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0) 334f04d8f0SCatalin Marinas #define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0) 344f04d8f0SCatalin Marinas 354f04d8f0SCatalin Marinas /* 364f04d8f0SCatalin Marinas * Section 374f04d8f0SCatalin Marinas */ 384f04d8f0SCatalin Marinas #define PMD_SECT_S (_AT(pmdval_t, 3) << 8) 394f04d8f0SCatalin Marinas #define PMD_SECT_AF (_AT(pmdval_t, 1) << 10) 404f04d8f0SCatalin Marinas #define PMD_SECT_NG (_AT(pmdval_t, 1) << 11) 41*8e620b04SCatalin Marinas #define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53) 42*8e620b04SCatalin Marinas #define PMD_SECT_UXN (_AT(pmdval_t, 1) << 54) 434f04d8f0SCatalin Marinas 444f04d8f0SCatalin Marinas /* 454f04d8f0SCatalin Marinas * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 464f04d8f0SCatalin Marinas */ 474f04d8f0SCatalin Marinas #define PMD_ATTRINDX(t) (_AT(pmdval_t, (t)) << 2) 484f04d8f0SCatalin Marinas #define PMD_ATTRINDX_MASK (_AT(pmdval_t, 7) << 2) 494f04d8f0SCatalin Marinas 504f04d8f0SCatalin Marinas /* 514f04d8f0SCatalin Marinas * Level 3 descriptor (PTE). 524f04d8f0SCatalin Marinas */ 534f04d8f0SCatalin Marinas #define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0) 544f04d8f0SCatalin Marinas #define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0) 554f04d8f0SCatalin Marinas #define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0) 564f04d8f0SCatalin Marinas #define PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ 574f04d8f0SCatalin Marinas #define PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */ 584f04d8f0SCatalin Marinas #define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ 594f04d8f0SCatalin Marinas #define PTE_AF (_AT(pteval_t, 1) << 10) /* Access Flag */ 604f04d8f0SCatalin Marinas #define PTE_NG (_AT(pteval_t, 1) << 11) /* nG */ 61*8e620b04SCatalin Marinas #define PTE_PXN (_AT(pteval_t, 1) << 53) /* Privileged XN */ 62*8e620b04SCatalin Marinas #define PTE_UXN (_AT(pteval_t, 1) << 54) /* User XN */ 634f04d8f0SCatalin Marinas 644f04d8f0SCatalin Marinas /* 654f04d8f0SCatalin Marinas * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 664f04d8f0SCatalin Marinas */ 674f04d8f0SCatalin Marinas #define PTE_ATTRINDX(t) (_AT(pteval_t, (t)) << 2) 684f04d8f0SCatalin Marinas #define PTE_ATTRINDX_MASK (_AT(pteval_t, 7) << 2) 694f04d8f0SCatalin Marinas 704f04d8f0SCatalin Marinas /* 714f04d8f0SCatalin Marinas * 40-bit physical address supported. 724f04d8f0SCatalin Marinas */ 734f04d8f0SCatalin Marinas #define PHYS_MASK_SHIFT (40) 744f04d8f0SCatalin Marinas #define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1) 754f04d8f0SCatalin Marinas 764f04d8f0SCatalin Marinas /* 774f04d8f0SCatalin Marinas * TCR flags. 784f04d8f0SCatalin Marinas */ 794f04d8f0SCatalin Marinas #define TCR_TxSZ(x) (((UL(64) - (x)) << 16) | ((UL(64) - (x)) << 0)) 804f04d8f0SCatalin Marinas #define TCR_IRGN_NC ((UL(0) << 8) | (UL(0) << 24)) 814f04d8f0SCatalin Marinas #define TCR_IRGN_WBWA ((UL(1) << 8) | (UL(1) << 24)) 824f04d8f0SCatalin Marinas #define TCR_IRGN_WT ((UL(2) << 8) | (UL(2) << 24)) 834f04d8f0SCatalin Marinas #define TCR_IRGN_WBnWA ((UL(3) << 8) | (UL(3) << 24)) 844f04d8f0SCatalin Marinas #define TCR_IRGN_MASK ((UL(3) << 8) | (UL(3) << 24)) 854f04d8f0SCatalin Marinas #define TCR_ORGN_NC ((UL(0) << 10) | (UL(0) << 26)) 864f04d8f0SCatalin Marinas #define TCR_ORGN_WBWA ((UL(1) << 10) | (UL(1) << 26)) 874f04d8f0SCatalin Marinas #define TCR_ORGN_WT ((UL(2) << 10) | (UL(2) << 26)) 884f04d8f0SCatalin Marinas #define TCR_ORGN_WBnWA ((UL(3) << 10) | (UL(3) << 26)) 894f04d8f0SCatalin Marinas #define TCR_ORGN_MASK ((UL(3) << 10) | (UL(3) << 26)) 904f04d8f0SCatalin Marinas #define TCR_SHARED ((UL(3) << 12) | (UL(3) << 28)) 914f04d8f0SCatalin Marinas #define TCR_TG0_64K (UL(1) << 14) 924f04d8f0SCatalin Marinas #define TCR_TG1_64K (UL(1) << 30) 934f04d8f0SCatalin Marinas #define TCR_IPS_40BIT (UL(2) << 32) 944f04d8f0SCatalin Marinas #define TCR_ASID16 (UL(1) << 36) 954f04d8f0SCatalin Marinas 964f04d8f0SCatalin Marinas #endif 97