1caab277bSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 24f04d8f0SCatalin Marinas /* 34f04d8f0SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 44f04d8f0SCatalin Marinas */ 54f04d8f0SCatalin Marinas #ifndef __ASM_PGTABLE_HWDEF_H 64f04d8f0SCatalin Marinas #define __ASM_PGTABLE_HWDEF_H 74f04d8f0SCatalin Marinas 8529c4b05SKristina Martsenko #include <asm/memory.h> 9529c4b05SKristina Martsenko 10686e7838SSuzuki K. Poulose /* 11686e7838SSuzuki K. Poulose * Number of page-table levels required to address 'va_bits' wide 12686e7838SSuzuki K. Poulose * address, without section mapping. We resolve the top (va_bits - PAGE_SHIFT) 13686e7838SSuzuki K. Poulose * bits with (PAGE_SHIFT - 3) bits at each page table level. Hence: 14686e7838SSuzuki K. Poulose * 15686e7838SSuzuki K. Poulose * levels = DIV_ROUND_UP((va_bits - PAGE_SHIFT), (PAGE_SHIFT - 3)) 16686e7838SSuzuki K. Poulose * 17686e7838SSuzuki K. Poulose * where DIV_ROUND_UP(n, d) => (((n) + (d) - 1) / (d)) 18686e7838SSuzuki K. Poulose * 19686e7838SSuzuki K. Poulose * We cannot include linux/kernel.h which defines DIV_ROUND_UP here 20686e7838SSuzuki K. Poulose * due to build issues. So we open code DIV_ROUND_UP here: 21686e7838SSuzuki K. Poulose * 22686e7838SSuzuki K. Poulose * ((((va_bits) - PAGE_SHIFT) + (PAGE_SHIFT - 3) - 1) / (PAGE_SHIFT - 3)) 23686e7838SSuzuki K. Poulose * 24686e7838SSuzuki K. Poulose * which gets simplified as : 25686e7838SSuzuki K. Poulose */ 26686e7838SSuzuki K. Poulose #define ARM64_HW_PGTABLE_LEVELS(va_bits) (((va_bits) - 4) / (PAGE_SHIFT - 3)) 27686e7838SSuzuki K. Poulose 28686e7838SSuzuki K. Poulose /* 29a6bbf5d4SArd Biesheuvel * Size mapped by an entry at level n ( -1 <= n <= 3) 30686e7838SSuzuki K. Poulose * We map (PAGE_SHIFT - 3) at all translation levels and PAGE_SHIFT bits 31686e7838SSuzuki K. Poulose * in the final page. The maximum number of translation levels supported by 32a6bbf5d4SArd Biesheuvel * the architecture is 5. Hence, starting at level n, we have further 33686e7838SSuzuki K. Poulose * ((4 - n) - 1) levels of translation excluding the offset within the page. 34686e7838SSuzuki K. Poulose * So, the total number of bits mapped by an entry at level n is : 35686e7838SSuzuki K. Poulose * 36686e7838SSuzuki K. Poulose * ((4 - n) - 1) * (PAGE_SHIFT - 3) + PAGE_SHIFT 37686e7838SSuzuki K. Poulose * 38686e7838SSuzuki K. Poulose * Rearranging it a bit we get : 39686e7838SSuzuki K. Poulose * (4 - n) * (PAGE_SHIFT - 3) + 3 40686e7838SSuzuki K. Poulose */ 41686e7838SSuzuki K. Poulose #define ARM64_HW_PGTABLE_LEVEL_SHIFT(n) ((PAGE_SHIFT - 3) * (4 - (n)) + 3) 42686e7838SSuzuki K. Poulose 436b4fee24SCatalin Marinas #define PTRS_PER_PTE (1 << (PAGE_SHIFT - 3)) 446b4fee24SCatalin Marinas 456b4fee24SCatalin Marinas /* 466b4fee24SCatalin Marinas * PMD_SHIFT determines the size a level 2 page table entry can map. 476b4fee24SCatalin Marinas */ 489f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 2 49686e7838SSuzuki K. Poulose #define PMD_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(2) 506b4fee24SCatalin Marinas #define PMD_SIZE (_AC(1, UL) << PMD_SHIFT) 516b4fee24SCatalin Marinas #define PMD_MASK (~(PMD_SIZE-1)) 522a2848e7SAnshuman Khandual #define PTRS_PER_PMD (1 << (PAGE_SHIFT - 3)) 534f04d8f0SCatalin Marinas #endif 544f04d8f0SCatalin Marinas 554f04d8f0SCatalin Marinas /* 566b4fee24SCatalin Marinas * PUD_SHIFT determines the size a level 1 page table entry can map. 576b4fee24SCatalin Marinas */ 589f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 3 59686e7838SSuzuki K. Poulose #define PUD_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(1) 606b4fee24SCatalin Marinas #define PUD_SIZE (_AC(1, UL) << PUD_SHIFT) 616b4fee24SCatalin Marinas #define PUD_MASK (~(PUD_SIZE-1)) 622a2848e7SAnshuman Khandual #define PTRS_PER_PUD (1 << (PAGE_SHIFT - 3)) 636b4fee24SCatalin Marinas #endif 646b4fee24SCatalin Marinas 65a6bbf5d4SArd Biesheuvel #if CONFIG_PGTABLE_LEVELS > 4 66a6bbf5d4SArd Biesheuvel #define P4D_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(0) 67a6bbf5d4SArd Biesheuvel #define P4D_SIZE (_AC(1, UL) << P4D_SHIFT) 68a6bbf5d4SArd Biesheuvel #define P4D_MASK (~(P4D_SIZE-1)) 69a6bbf5d4SArd Biesheuvel #define PTRS_PER_P4D (1 << (PAGE_SHIFT - 3)) 70a6bbf5d4SArd Biesheuvel #endif 71a6bbf5d4SArd Biesheuvel 726b4fee24SCatalin Marinas /* 736b4fee24SCatalin Marinas * PGDIR_SHIFT determines the size a top-level page table entry can map 74a6bbf5d4SArd Biesheuvel * (depending on the configuration, this level can be -1, 0, 1 or 2). 756b4fee24SCatalin Marinas */ 76686e7838SSuzuki K. Poulose #define PGDIR_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - CONFIG_PGTABLE_LEVELS) 776b4fee24SCatalin Marinas #define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT) 786b4fee24SCatalin Marinas #define PGDIR_MASK (~(PGDIR_SIZE-1)) 79218564b1SBhupesh Sharma #define PTRS_PER_PGD (1 << (VA_BITS - PGDIR_SHIFT)) 806b4fee24SCatalin Marinas 816b4fee24SCatalin Marinas /* 82ecf35a23SJeremy Linton * Contiguous page definitions. 83ecf35a23SJeremy Linton */ 84c0d6de32SGavin Shan #define CONT_PTE_SHIFT (CONFIG_ARM64_CONT_PTE_SHIFT + PAGE_SHIFT) 85a1634a54SGavin Shan #define CONT_PTES (1 << (CONT_PTE_SHIFT - PAGE_SHIFT)) 8666b3923aSDavid Woods #define CONT_PTE_SIZE (CONT_PTES * PAGE_SIZE) 8766b3923aSDavid Woods #define CONT_PTE_MASK (~(CONT_PTE_SIZE - 1)) 88e6765941SGavin Shan 89e6765941SGavin Shan #define CONT_PMD_SHIFT (CONFIG_ARM64_CONT_PMD_SHIFT + PMD_SHIFT) 90a1634a54SGavin Shan #define CONT_PMDS (1 << (CONT_PMD_SHIFT - PMD_SHIFT)) 9166b3923aSDavid Woods #define CONT_PMD_SIZE (CONT_PMDS * PMD_SIZE) 9266b3923aSDavid Woods #define CONT_PMD_MASK (~(CONT_PMD_SIZE - 1)) 93ecf35a23SJeremy Linton 94ecf35a23SJeremy Linton /* 954f04d8f0SCatalin Marinas * Hardware page table definitions. 964f04d8f0SCatalin Marinas * 97a6bbf5d4SArd Biesheuvel * Level -1 descriptor (PGD). 98a6bbf5d4SArd Biesheuvel */ 99a6bbf5d4SArd Biesheuvel #define PGD_TYPE_TABLE (_AT(pgdval_t, 3) << 0) 100a6bbf5d4SArd Biesheuvel #define PGD_TABLE_BIT (_AT(pgdval_t, 1) << 1) 101a6bbf5d4SArd Biesheuvel #define PGD_TYPE_MASK (_AT(pgdval_t, 3) << 0) 102a6bbf5d4SArd Biesheuvel #define PGD_TABLE_PXN (_AT(pgdval_t, 1) << 59) 103a6bbf5d4SArd Biesheuvel #define PGD_TABLE_UXN (_AT(pgdval_t, 1) << 60) 104a6bbf5d4SArd Biesheuvel 105a6bbf5d4SArd Biesheuvel /* 106c1fd78a7SArd Biesheuvel * Level 0 descriptor (P4D). 107c1fd78a7SArd Biesheuvel */ 108c1fd78a7SArd Biesheuvel #define P4D_TYPE_TABLE (_AT(p4dval_t, 3) << 0) 109c1fd78a7SArd Biesheuvel #define P4D_TABLE_BIT (_AT(p4dval_t, 1) << 1) 110c1fd78a7SArd Biesheuvel #define P4D_TYPE_MASK (_AT(p4dval_t, 3) << 0) 111c1fd78a7SArd Biesheuvel #define P4D_TYPE_SECT (_AT(p4dval_t, 1) << 0) 112c1fd78a7SArd Biesheuvel #define P4D_SECT_RDONLY (_AT(p4dval_t, 1) << 7) /* AP[2] */ 11387143f40SArd Biesheuvel #define P4D_TABLE_PXN (_AT(p4dval_t, 1) << 59) 11487143f40SArd Biesheuvel #define P4D_TABLE_UXN (_AT(p4dval_t, 1) << 60) 115c1fd78a7SArd Biesheuvel 116c1fd78a7SArd Biesheuvel /* 117084bd298SSteve Capper * Level 1 descriptor (PUD). 118084bd298SSteve Capper */ 119c79b954bSJungseok Lee #define PUD_TYPE_TABLE (_AT(pudval_t, 3) << 0) 12029d9bef1SPunit Agrawal #define PUD_TABLE_BIT (_AT(pudval_t, 1) << 1) 12129d9bef1SPunit Agrawal #define PUD_TYPE_MASK (_AT(pudval_t, 3) << 0) 12229d9bef1SPunit Agrawal #define PUD_TYPE_SECT (_AT(pudval_t, 1) << 0) 1237ea40889SPavel Tatashin #define PUD_SECT_RDONLY (_AT(pudval_t, 1) << 7) /* AP[2] */ 12487143f40SArd Biesheuvel #define PUD_TABLE_PXN (_AT(pudval_t, 1) << 59) 12587143f40SArd Biesheuvel #define PUD_TABLE_UXN (_AT(pudval_t, 1) << 60) 126084bd298SSteve Capper 127084bd298SSteve Capper /* 1284f04d8f0SCatalin Marinas * Level 2 descriptor (PMD). 1294f04d8f0SCatalin Marinas */ 1304f04d8f0SCatalin Marinas #define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0) 1314f04d8f0SCatalin Marinas #define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0) 1324f04d8f0SCatalin Marinas #define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0) 133084bd298SSteve Capper #define PMD_TABLE_BIT (_AT(pmdval_t, 1) << 1) 1344f04d8f0SCatalin Marinas 1354f04d8f0SCatalin Marinas /* 1364f04d8f0SCatalin Marinas * Section 1374f04d8f0SCatalin Marinas */ 138af074848SSteve Capper #define PMD_SECT_VALID (_AT(pmdval_t, 1) << 0) 139af074848SSteve Capper #define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */ 140af074848SSteve Capper #define PMD_SECT_RDONLY (_AT(pmdval_t, 1) << 7) /* AP[2] */ 1414f04d8f0SCatalin Marinas #define PMD_SECT_S (_AT(pmdval_t, 3) << 8) 1424f04d8f0SCatalin Marinas #define PMD_SECT_AF (_AT(pmdval_t, 1) << 10) 1434f04d8f0SCatalin Marinas #define PMD_SECT_NG (_AT(pmdval_t, 1) << 11) 144ecf35a23SJeremy Linton #define PMD_SECT_CONT (_AT(pmdval_t, 1) << 52) 1458e620b04SCatalin Marinas #define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53) 1468e620b04SCatalin Marinas #define PMD_SECT_UXN (_AT(pmdval_t, 1) << 54) 14787143f40SArd Biesheuvel #define PMD_TABLE_PXN (_AT(pmdval_t, 1) << 59) 14887143f40SArd Biesheuvel #define PMD_TABLE_UXN (_AT(pmdval_t, 1) << 60) 1494f04d8f0SCatalin Marinas 1504f04d8f0SCatalin Marinas /* 1514f04d8f0SCatalin Marinas * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 1524f04d8f0SCatalin Marinas */ 1534f04d8f0SCatalin Marinas #define PMD_ATTRINDX(t) (_AT(pmdval_t, (t)) << 2) 1544f04d8f0SCatalin Marinas #define PMD_ATTRINDX_MASK (_AT(pmdval_t, 7) << 2) 1554f04d8f0SCatalin Marinas 1564f04d8f0SCatalin Marinas /* 1574f04d8f0SCatalin Marinas * Level 3 descriptor (PTE). 1584f04d8f0SCatalin Marinas */ 159201d355cSAnshuman Khandual #define PTE_VALID (_AT(pteval_t, 1) << 0) 1604f04d8f0SCatalin Marinas #define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0) 1614f04d8f0SCatalin Marinas #define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0) 162084bd298SSteve Capper #define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1) 1634f04d8f0SCatalin Marinas #define PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ 1644f04d8f0SCatalin Marinas #define PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */ 1654f04d8f0SCatalin Marinas #define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ 1664f04d8f0SCatalin Marinas #define PTE_AF (_AT(pteval_t, 1) << 10) /* Access Flag */ 1674f04d8f0SCatalin Marinas #define PTE_NG (_AT(pteval_t, 1) << 11) /* nG */ 1688ef8f360SDave Martin #define PTE_GP (_AT(pteval_t, 1) << 50) /* BTI guarded */ 1692f4b829cSCatalin Marinas #define PTE_DBM (_AT(pteval_t, 1) << 51) /* Dirty Bit Management */ 170ecf35a23SJeremy Linton #define PTE_CONT (_AT(pteval_t, 1) << 52) /* Contiguous range */ 1718e620b04SCatalin Marinas #define PTE_PXN (_AT(pteval_t, 1) << 53) /* Privileged XN */ 1728e620b04SCatalin Marinas #define PTE_UXN (_AT(pteval_t, 1) << 54) /* User XN */ 173*895a3702SRyan Roberts #define PTE_SWBITS_MASK _AT(pteval_t, (BIT(63) | GENMASK(58, 55))) 1744f04d8f0SCatalin Marinas 175925a0eb4SArd Biesheuvel #define PTE_ADDR_LOW (((_AT(pteval_t, 1) << (50 - PAGE_SHIFT)) - 1) << PAGE_SHIFT) 17675387b92SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 177925a0eb4SArd Biesheuvel #ifdef CONFIG_ARM64_64K_PAGES 178e6d588a8SKristina Martsenko #define PTE_ADDR_HIGH (_AT(pteval_t, 0xf) << 12) 179a4ee2861SAnshuman Khandual #define PTE_ADDR_HIGH_SHIFT 36 180925a0eb4SArd Biesheuvel #define PHYS_TO_PTE_ADDR_MASK (PTE_ADDR_LOW | PTE_ADDR_HIGH) 18175387b92SKristina Martsenko #else 182925a0eb4SArd Biesheuvel #define PTE_ADDR_HIGH (_AT(pteval_t, 0x3) << 8) 183925a0eb4SArd Biesheuvel #define PTE_ADDR_HIGH_SHIFT 42 184925a0eb4SArd Biesheuvel #define PHYS_TO_PTE_ADDR_MASK GENMASK_ULL(49, 8) 185925a0eb4SArd Biesheuvel #endif 186e6d588a8SKristina Martsenko #endif 187e6d588a8SKristina Martsenko 1884f04d8f0SCatalin Marinas /* 1894f04d8f0SCatalin Marinas * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 1904f04d8f0SCatalin Marinas */ 1914f04d8f0SCatalin Marinas #define PTE_ATTRINDX(t) (_AT(pteval_t, (t)) << 2) 1924f04d8f0SCatalin Marinas #define PTE_ATTRINDX_MASK (_AT(pteval_t, 7) << 2) 1934f04d8f0SCatalin Marinas 1944f04d8f0SCatalin Marinas /* 195eeda243dSJoey Gouly * PIIndex[3:0] encoding (Permission Indirection Extension) 196eeda243dSJoey Gouly */ 197eeda243dSJoey Gouly #define PTE_PI_IDX_0 6 /* AP[1], USER */ 198eeda243dSJoey Gouly #define PTE_PI_IDX_1 51 /* DBM */ 199eeda243dSJoey Gouly #define PTE_PI_IDX_2 53 /* PXN */ 200eeda243dSJoey Gouly #define PTE_PI_IDX_3 54 /* UXN */ 201eeda243dSJoey Gouly 202eeda243dSJoey Gouly /* 20336311607SMarc Zyngier * Memory Attribute override for Stage-2 (MemAttr[3:0]) 20436311607SMarc Zyngier */ 20536311607SMarc Zyngier #define PTE_S2_MEMATTR(t) (_AT(pteval_t, (t)) << 2) 20636311607SMarc Zyngier 20736311607SMarc Zyngier /* 20887366d8cSRadha Mohan Chintakuntla * Highest possible physical address supported. 2094f04d8f0SCatalin Marinas */ 210982aa7c5SKristina Martsenko #define PHYS_MASK_SHIFT (CONFIG_ARM64_PA_BITS) 2114f04d8f0SCatalin Marinas #define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1) 2124f04d8f0SCatalin Marinas 2135ffdfaedSVladimir Murzin #define TTBR_CNP_BIT (UL(1) << 0) 2145ffdfaedSVladimir Murzin 2154f04d8f0SCatalin Marinas /* 2164f04d8f0SCatalin Marinas * TCR flags. 2174f04d8f0SCatalin Marinas */ 218dd006da2SArd Biesheuvel #define TCR_T0SZ_OFFSET 0 219dd006da2SArd Biesheuvel #define TCR_T1SZ_OFFSET 16 220dd006da2SArd Biesheuvel #define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_T0SZ_OFFSET) 221dd006da2SArd Biesheuvel #define TCR_T1SZ(x) ((UL(64) - (x)) << TCR_T1SZ_OFFSET) 222dd006da2SArd Biesheuvel #define TCR_TxSZ(x) (TCR_T0SZ(x) | TCR_T1SZ(x)) 223dd006da2SArd Biesheuvel #define TCR_TxSZ_WIDTH 6 224adf75899SMark Rutland #define TCR_T0SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET) 225bbdbc118SBhupesh Sharma #define TCR_T1SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T1SZ_OFFSET) 226a563f759SSuzuki K Poulose 227793d5d92SMarc Zyngier #define TCR_EPD0_SHIFT 7 228793d5d92SMarc Zyngier #define TCR_EPD0_MASK (UL(1) << TCR_EPD0_SHIFT) 229a563f759SSuzuki K Poulose #define TCR_IRGN0_SHIFT 8 230a563f759SSuzuki K Poulose #define TCR_IRGN0_MASK (UL(3) << TCR_IRGN0_SHIFT) 231a563f759SSuzuki K Poulose #define TCR_IRGN0_NC (UL(0) << TCR_IRGN0_SHIFT) 232a563f759SSuzuki K Poulose #define TCR_IRGN0_WBWA (UL(1) << TCR_IRGN0_SHIFT) 233a563f759SSuzuki K Poulose #define TCR_IRGN0_WT (UL(2) << TCR_IRGN0_SHIFT) 234a563f759SSuzuki K Poulose #define TCR_IRGN0_WBnWA (UL(3) << TCR_IRGN0_SHIFT) 235a563f759SSuzuki K Poulose 236793d5d92SMarc Zyngier #define TCR_EPD1_SHIFT 23 237793d5d92SMarc Zyngier #define TCR_EPD1_MASK (UL(1) << TCR_EPD1_SHIFT) 238a563f759SSuzuki K Poulose #define TCR_IRGN1_SHIFT 24 239a563f759SSuzuki K Poulose #define TCR_IRGN1_MASK (UL(3) << TCR_IRGN1_SHIFT) 240a563f759SSuzuki K Poulose #define TCR_IRGN1_NC (UL(0) << TCR_IRGN1_SHIFT) 241a563f759SSuzuki K Poulose #define TCR_IRGN1_WBWA (UL(1) << TCR_IRGN1_SHIFT) 242a563f759SSuzuki K Poulose #define TCR_IRGN1_WT (UL(2) << TCR_IRGN1_SHIFT) 243a563f759SSuzuki K Poulose #define TCR_IRGN1_WBnWA (UL(3) << TCR_IRGN1_SHIFT) 244a563f759SSuzuki K Poulose 245a563f759SSuzuki K Poulose #define TCR_IRGN_NC (TCR_IRGN0_NC | TCR_IRGN1_NC) 246a563f759SSuzuki K Poulose #define TCR_IRGN_WBWA (TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) 247a563f759SSuzuki K Poulose #define TCR_IRGN_WT (TCR_IRGN0_WT | TCR_IRGN1_WT) 248a563f759SSuzuki K Poulose #define TCR_IRGN_WBnWA (TCR_IRGN0_WBnWA | TCR_IRGN1_WBnWA) 249a563f759SSuzuki K Poulose #define TCR_IRGN_MASK (TCR_IRGN0_MASK | TCR_IRGN1_MASK) 250a563f759SSuzuki K Poulose 251a563f759SSuzuki K Poulose 252a563f759SSuzuki K Poulose #define TCR_ORGN0_SHIFT 10 253a563f759SSuzuki K Poulose #define TCR_ORGN0_MASK (UL(3) << TCR_ORGN0_SHIFT) 254a563f759SSuzuki K Poulose #define TCR_ORGN0_NC (UL(0) << TCR_ORGN0_SHIFT) 255a563f759SSuzuki K Poulose #define TCR_ORGN0_WBWA (UL(1) << TCR_ORGN0_SHIFT) 256a563f759SSuzuki K Poulose #define TCR_ORGN0_WT (UL(2) << TCR_ORGN0_SHIFT) 257a563f759SSuzuki K Poulose #define TCR_ORGN0_WBnWA (UL(3) << TCR_ORGN0_SHIFT) 258a563f759SSuzuki K Poulose 259a563f759SSuzuki K Poulose #define TCR_ORGN1_SHIFT 26 260a563f759SSuzuki K Poulose #define TCR_ORGN1_MASK (UL(3) << TCR_ORGN1_SHIFT) 261a563f759SSuzuki K Poulose #define TCR_ORGN1_NC (UL(0) << TCR_ORGN1_SHIFT) 262a563f759SSuzuki K Poulose #define TCR_ORGN1_WBWA (UL(1) << TCR_ORGN1_SHIFT) 263a563f759SSuzuki K Poulose #define TCR_ORGN1_WT (UL(2) << TCR_ORGN1_SHIFT) 264a563f759SSuzuki K Poulose #define TCR_ORGN1_WBnWA (UL(3) << TCR_ORGN1_SHIFT) 265a563f759SSuzuki K Poulose 266a563f759SSuzuki K Poulose #define TCR_ORGN_NC (TCR_ORGN0_NC | TCR_ORGN1_NC) 267a563f759SSuzuki K Poulose #define TCR_ORGN_WBWA (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA) 268a563f759SSuzuki K Poulose #define TCR_ORGN_WT (TCR_ORGN0_WT | TCR_ORGN1_WT) 269a563f759SSuzuki K Poulose #define TCR_ORGN_WBnWA (TCR_ORGN0_WBnWA | TCR_ORGN1_WBnWA) 270a563f759SSuzuki K Poulose #define TCR_ORGN_MASK (TCR_ORGN0_MASK | TCR_ORGN1_MASK) 271a563f759SSuzuki K Poulose 272a563f759SSuzuki K Poulose #define TCR_SH0_SHIFT 12 273a563f759SSuzuki K Poulose #define TCR_SH0_MASK (UL(3) << TCR_SH0_SHIFT) 274a563f759SSuzuki K Poulose #define TCR_SH0_INNER (UL(3) << TCR_SH0_SHIFT) 275a563f759SSuzuki K Poulose 276a563f759SSuzuki K Poulose #define TCR_SH1_SHIFT 28 277a563f759SSuzuki K Poulose #define TCR_SH1_MASK (UL(3) << TCR_SH1_SHIFT) 278a563f759SSuzuki K Poulose #define TCR_SH1_INNER (UL(3) << TCR_SH1_SHIFT) 279a563f759SSuzuki K Poulose #define TCR_SHARED (TCR_SH0_INNER | TCR_SH1_INNER) 280a563f759SSuzuki K Poulose 281a563f759SSuzuki K Poulose #define TCR_TG0_SHIFT 14 282a563f759SSuzuki K Poulose #define TCR_TG0_MASK (UL(3) << TCR_TG0_SHIFT) 283a563f759SSuzuki K Poulose #define TCR_TG0_4K (UL(0) << TCR_TG0_SHIFT) 284a563f759SSuzuki K Poulose #define TCR_TG0_64K (UL(1) << TCR_TG0_SHIFT) 285a563f759SSuzuki K Poulose #define TCR_TG0_16K (UL(2) << TCR_TG0_SHIFT) 286a563f759SSuzuki K Poulose 287a563f759SSuzuki K Poulose #define TCR_TG1_SHIFT 30 288a563f759SSuzuki K Poulose #define TCR_TG1_MASK (UL(3) << TCR_TG1_SHIFT) 289a563f759SSuzuki K Poulose #define TCR_TG1_16K (UL(1) << TCR_TG1_SHIFT) 290a563f759SSuzuki K Poulose #define TCR_TG1_4K (UL(2) << TCR_TG1_SHIFT) 291a563f759SSuzuki K Poulose #define TCR_TG1_64K (UL(3) << TCR_TG1_SHIFT) 292a563f759SSuzuki K Poulose 293787fd1d0SKristina Martsenko #define TCR_IPS_SHIFT 32 294787fd1d0SKristina Martsenko #define TCR_IPS_MASK (UL(7) << TCR_IPS_SHIFT) 2957655abb9SWill Deacon #define TCR_A1 (UL(1) << 22) 2964f04d8f0SCatalin Marinas #define TCR_ASID16 (UL(1) << 36) 297d50240a5SWill Deacon #define TCR_TBI0 (UL(1) << 37) 29821696c16SAndrey Konovalov #define TCR_TBI1 (UL(1) << 38) 2992f4b829cSCatalin Marinas #define TCR_HA (UL(1) << 39) 3002f4b829cSCatalin Marinas #define TCR_HD (UL(1) << 40) 3016ccc971eSMarc Zyngier #define TCR_TBID0 (UL(1) << 51) 30249b3cf03SPeter Collingbourne #define TCR_TBID1 (UL(1) << 52) 3033e32131aSZhang Lei #define TCR_NFD0 (UL(1) << 53) 304e03e61c3SWill Deacon #define TCR_NFD1 (UL(1) << 54) 3053e6c69a0SMark Brown #define TCR_E0PD0 (UL(1) << 55) 3063e6c69a0SMark Brown #define TCR_E0PD1 (UL(1) << 56) 307e921da6bSAnshuman Khandual #define TCR_TCMA0 (UL(1) << 57) 308e921da6bSAnshuman Khandual #define TCR_TCMA1 (UL(1) << 58) 309db95ea78SArd Biesheuvel #define TCR_DS (UL(1) << 59) 3104f04d8f0SCatalin Marinas 311529c4b05SKristina Martsenko /* 312529c4b05SKristina Martsenko * TTBR. 313529c4b05SKristina Martsenko */ 314529c4b05SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 315529c4b05SKristina Martsenko /* 316529c4b05SKristina Martsenko * TTBR_ELx[1] is RES0 in this configuration. 317529c4b05SKristina Martsenko */ 31819198abfSJoey Gouly #define TTBR_BADDR_MASK_52 GENMASK_ULL(47, 2) 319529c4b05SKristina Martsenko #endif 320529c4b05SKristina Martsenko 321b6d00d47SSteve Capper #ifdef CONFIG_ARM64_VA_BITS_52 322e842dfb5SSteve Capper /* Must be at least 64-byte aligned to prevent corruption of the TTBR */ 323e842dfb5SSteve Capper #define TTBR1_BADDR_4852_OFFSET (((UL(1) << (52 - PGDIR_SHIFT)) - \ 324e842dfb5SSteve Capper (UL(1) << (48 - PGDIR_SHIFT))) * 8) 325e842dfb5SSteve Capper #endif 326e842dfb5SSteve Capper 3274f04d8f0SCatalin Marinas #endif 328