1 /* 2 * Based on arch/arm/include/asm/mmu_context.h 3 * 4 * Copyright (C) 1996 Russell King. 5 * Copyright (C) 2012 ARM Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef __ASM_MMU_CONTEXT_H 20 #define __ASM_MMU_CONTEXT_H 21 22 #include <linux/compiler.h> 23 #include <linux/sched.h> 24 25 #include <asm/cacheflush.h> 26 #include <asm/cpufeature.h> 27 #include <asm/proc-fns.h> 28 #include <asm-generic/mm_hooks.h> 29 #include <asm/cputype.h> 30 #include <asm/pgtable.h> 31 #include <asm/sysreg.h> 32 #include <asm/tlbflush.h> 33 34 static inline void contextidr_thread_switch(struct task_struct *next) 35 { 36 if (!IS_ENABLED(CONFIG_PID_IN_CONTEXTIDR)) 37 return; 38 39 write_sysreg(task_pid_nr(next), contextidr_el1); 40 isb(); 41 } 42 43 /* 44 * Set TTBR0 to empty_zero_page. No translations will be possible via TTBR0. 45 */ 46 static inline void cpu_set_reserved_ttbr0(void) 47 { 48 unsigned long ttbr = virt_to_phys(empty_zero_page); 49 50 write_sysreg(ttbr, ttbr0_el1); 51 isb(); 52 } 53 54 /* 55 * TCR.T0SZ value to use when the ID map is active. Usually equals 56 * TCR_T0SZ(VA_BITS), unless system RAM is positioned very high in 57 * physical memory, in which case it will be smaller. 58 */ 59 extern u64 idmap_t0sz; 60 61 static inline bool __cpu_uses_extended_idmap(void) 62 { 63 return (!IS_ENABLED(CONFIG_ARM64_VA_BITS_48) && 64 unlikely(idmap_t0sz != TCR_T0SZ(VA_BITS))); 65 } 66 67 /* 68 * Set TCR.T0SZ to its default value (based on VA_BITS) 69 */ 70 static inline void __cpu_set_tcr_t0sz(unsigned long t0sz) 71 { 72 unsigned long tcr; 73 74 if (!__cpu_uses_extended_idmap()) 75 return; 76 77 tcr = read_sysreg(tcr_el1); 78 tcr &= ~TCR_T0SZ_MASK; 79 tcr |= t0sz << TCR_T0SZ_OFFSET; 80 write_sysreg(tcr, tcr_el1); 81 isb(); 82 } 83 84 #define cpu_set_default_tcr_t0sz() __cpu_set_tcr_t0sz(TCR_T0SZ(VA_BITS)) 85 #define cpu_set_idmap_tcr_t0sz() __cpu_set_tcr_t0sz(idmap_t0sz) 86 87 /* 88 * Remove the idmap from TTBR0_EL1 and install the pgd of the active mm. 89 * 90 * The idmap lives in the same VA range as userspace, but uses global entries 91 * and may use a different TCR_EL1.T0SZ. To avoid issues resulting from 92 * speculative TLB fetches, we must temporarily install the reserved page 93 * tables while we invalidate the TLBs and set up the correct TCR_EL1.T0SZ. 94 * 95 * If current is a not a user task, the mm covers the TTBR1_EL1 page tables, 96 * which should not be installed in TTBR0_EL1. In this case we can leave the 97 * reserved page tables in place. 98 */ 99 static inline void cpu_uninstall_idmap(void) 100 { 101 struct mm_struct *mm = current->active_mm; 102 103 cpu_set_reserved_ttbr0(); 104 local_flush_tlb_all(); 105 cpu_set_default_tcr_t0sz(); 106 107 if (mm != &init_mm && !system_uses_ttbr0_pan()) 108 cpu_switch_mm(mm->pgd, mm); 109 } 110 111 static inline void cpu_install_idmap(void) 112 { 113 cpu_set_reserved_ttbr0(); 114 local_flush_tlb_all(); 115 cpu_set_idmap_tcr_t0sz(); 116 117 cpu_switch_mm(idmap_pg_dir, &init_mm); 118 } 119 120 /* 121 * Atomically replaces the active TTBR1_EL1 PGD with a new VA-compatible PGD, 122 * avoiding the possibility of conflicting TLB entries being allocated. 123 */ 124 static inline void cpu_replace_ttbr1(pgd_t *pgd) 125 { 126 typedef void (ttbr_replace_func)(phys_addr_t); 127 extern ttbr_replace_func idmap_cpu_replace_ttbr1; 128 ttbr_replace_func *replace_phys; 129 130 phys_addr_t pgd_phys = virt_to_phys(pgd); 131 132 replace_phys = (void *)virt_to_phys(idmap_cpu_replace_ttbr1); 133 134 cpu_install_idmap(); 135 replace_phys(pgd_phys); 136 cpu_uninstall_idmap(); 137 } 138 139 /* 140 * It would be nice to return ASIDs back to the allocator, but unfortunately 141 * that introduces a race with a generation rollover where we could erroneously 142 * free an ASID allocated in a future generation. We could workaround this by 143 * freeing the ASID from the context of the dying mm (e.g. in arch_exit_mmap), 144 * but we'd then need to make sure that we didn't dirty any TLBs afterwards. 145 * Setting a reserved TTBR0 or EPD0 would work, but it all gets ugly when you 146 * take CPU migration into account. 147 */ 148 #define destroy_context(mm) do { } while(0) 149 void check_and_switch_context(struct mm_struct *mm, unsigned int cpu); 150 151 #define init_new_context(tsk,mm) ({ atomic64_set(&(mm)->context.id, 0); 0; }) 152 153 /* 154 * This is called when "tsk" is about to enter lazy TLB mode. 155 * 156 * mm: describes the currently active mm context 157 * tsk: task which is entering lazy tlb 158 * cpu: cpu number which is entering lazy tlb 159 * 160 * tsk->mm will be NULL 161 */ 162 static inline void 163 enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) 164 { 165 } 166 167 #ifdef CONFIG_ARM64_SW_TTBR0_PAN 168 static inline void update_saved_ttbr0(struct task_struct *tsk, 169 struct mm_struct *mm) 170 { 171 if (system_uses_ttbr0_pan()) { 172 BUG_ON(mm->pgd == swapper_pg_dir); 173 task_thread_info(tsk)->ttbr0 = 174 virt_to_phys(mm->pgd) | ASID(mm) << 48; 175 } 176 } 177 #else 178 static inline void update_saved_ttbr0(struct task_struct *tsk, 179 struct mm_struct *mm) 180 { 181 } 182 #endif 183 184 static inline void __switch_mm(struct mm_struct *next) 185 { 186 unsigned int cpu = smp_processor_id(); 187 188 /* 189 * init_mm.pgd does not contain any user mappings and it is always 190 * active for kernel addresses in TTBR1. Just set the reserved TTBR0. 191 */ 192 if (next == &init_mm) { 193 cpu_set_reserved_ttbr0(); 194 return; 195 } 196 197 check_and_switch_context(next, cpu); 198 } 199 200 static inline void 201 switch_mm(struct mm_struct *prev, struct mm_struct *next, 202 struct task_struct *tsk) 203 { 204 if (prev != next) 205 __switch_mm(next); 206 207 /* 208 * Update the saved TTBR0_EL1 of the scheduled-in task as the previous 209 * value may have not been initialised yet (activate_mm caller) or the 210 * ASID has changed since the last run (following the context switch 211 * of another thread of the same process). Avoid setting the reserved 212 * TTBR0_EL1 to swapper_pg_dir (init_mm; e.g. via idle_task_exit). 213 */ 214 if (next != &init_mm) 215 update_saved_ttbr0(tsk, next); 216 } 217 218 #define deactivate_mm(tsk,mm) do { } while (0) 219 #define activate_mm(prev,next) switch_mm(prev, next, current) 220 221 void verify_cpu_asid_bits(void); 222 223 #endif 224