1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Based on arch/arm/include/asm/mmu_context.h 4 * 5 * Copyright (C) 1996 Russell King. 6 * Copyright (C) 2012 ARM Ltd. 7 */ 8 #ifndef __ASM_MMU_CONTEXT_H 9 #define __ASM_MMU_CONTEXT_H 10 11 #ifndef __ASSEMBLY__ 12 13 #include <linux/compiler.h> 14 #include <linux/sched.h> 15 #include <linux/sched/hotplug.h> 16 #include <linux/mm_types.h> 17 #include <linux/pgtable.h> 18 19 #include <asm/cacheflush.h> 20 #include <asm/cpufeature.h> 21 #include <asm/daifflags.h> 22 #include <asm/proc-fns.h> 23 #include <asm-generic/mm_hooks.h> 24 #include <asm/cputype.h> 25 #include <asm/sysreg.h> 26 #include <asm/tlbflush.h> 27 28 extern bool rodata_full; 29 30 static inline void contextidr_thread_switch(struct task_struct *next) 31 { 32 if (!IS_ENABLED(CONFIG_PID_IN_CONTEXTIDR)) 33 return; 34 35 write_sysreg(task_pid_nr(next), contextidr_el1); 36 isb(); 37 } 38 39 /* 40 * Set TTBR0 to reserved_pg_dir. No translations will be possible via TTBR0. 41 */ 42 static inline void cpu_set_reserved_ttbr0_nosync(void) 43 { 44 unsigned long ttbr = phys_to_ttbr(__pa_symbol(reserved_pg_dir)); 45 46 write_sysreg(ttbr, ttbr0_el1); 47 } 48 49 static inline void cpu_set_reserved_ttbr0(void) 50 { 51 cpu_set_reserved_ttbr0_nosync(); 52 isb(); 53 } 54 55 void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm); 56 57 static inline void cpu_switch_mm(pgd_t *pgd, struct mm_struct *mm) 58 { 59 BUG_ON(pgd == swapper_pg_dir); 60 cpu_do_switch_mm(virt_to_phys(pgd),mm); 61 } 62 63 /* 64 * TCR.T0SZ value to use when the ID map is active. 65 */ 66 #define idmap_t0sz TCR_T0SZ(IDMAP_VA_BITS) 67 68 /* 69 * Ensure TCR.T0SZ is set to the provided value. 70 */ 71 static inline void __cpu_set_tcr_t0sz(unsigned long t0sz) 72 { 73 unsigned long tcr = read_sysreg(tcr_el1); 74 75 if ((tcr & TCR_T0SZ_MASK) >> TCR_T0SZ_OFFSET == t0sz) 76 return; 77 78 tcr &= ~TCR_T0SZ_MASK; 79 tcr |= t0sz << TCR_T0SZ_OFFSET; 80 write_sysreg(tcr, tcr_el1); 81 isb(); 82 } 83 84 #define cpu_set_default_tcr_t0sz() __cpu_set_tcr_t0sz(TCR_T0SZ(vabits_actual)) 85 #define cpu_set_idmap_tcr_t0sz() __cpu_set_tcr_t0sz(idmap_t0sz) 86 87 /* 88 * Remove the idmap from TTBR0_EL1 and install the pgd of the active mm. 89 * 90 * The idmap lives in the same VA range as userspace, but uses global entries 91 * and may use a different TCR_EL1.T0SZ. To avoid issues resulting from 92 * speculative TLB fetches, we must temporarily install the reserved page 93 * tables while we invalidate the TLBs and set up the correct TCR_EL1.T0SZ. 94 * 95 * If current is a not a user task, the mm covers the TTBR1_EL1 page tables, 96 * which should not be installed in TTBR0_EL1. In this case we can leave the 97 * reserved page tables in place. 98 */ 99 static inline void cpu_uninstall_idmap(void) 100 { 101 struct mm_struct *mm = current->active_mm; 102 103 cpu_set_reserved_ttbr0(); 104 local_flush_tlb_all(); 105 cpu_set_default_tcr_t0sz(); 106 107 if (mm != &init_mm && !system_uses_ttbr0_pan()) 108 cpu_switch_mm(mm->pgd, mm); 109 } 110 111 static inline void cpu_install_idmap(void) 112 { 113 cpu_set_reserved_ttbr0(); 114 local_flush_tlb_all(); 115 cpu_set_idmap_tcr_t0sz(); 116 117 cpu_switch_mm(lm_alias(idmap_pg_dir), &init_mm); 118 } 119 120 /* 121 * Load our new page tables. A strict BBM approach requires that we ensure that 122 * TLBs are free of any entries that may overlap with the global mappings we are 123 * about to install. 124 * 125 * For a real hibernate/resume/kexec cycle TTBR0 currently points to a zero 126 * page, but TLBs may contain stale ASID-tagged entries (e.g. for EFI runtime 127 * services), while for a userspace-driven test_resume cycle it points to 128 * userspace page tables (and we must point it at a zero page ourselves). 129 * 130 * We change T0SZ as part of installing the idmap. This is undone by 131 * cpu_uninstall_idmap() in __cpu_suspend_exit(). 132 */ 133 static inline void cpu_install_ttbr0(phys_addr_t ttbr0, unsigned long t0sz) 134 { 135 cpu_set_reserved_ttbr0(); 136 local_flush_tlb_all(); 137 __cpu_set_tcr_t0sz(t0sz); 138 139 /* avoid cpu_switch_mm() and its SW-PAN and CNP interactions */ 140 write_sysreg(ttbr0, ttbr0_el1); 141 isb(); 142 } 143 144 void __cpu_replace_ttbr1(pgd_t *pgdp, bool cnp); 145 146 static inline void cpu_enable_swapper_cnp(void) 147 { 148 __cpu_replace_ttbr1(lm_alias(swapper_pg_dir), true); 149 } 150 151 static inline void cpu_replace_ttbr1(pgd_t *pgdp) 152 { 153 /* 154 * Only for early TTBR1 replacement before cpucaps are finalized and 155 * before we've decided whether to use CNP. 156 */ 157 WARN_ON(system_capabilities_finalized()); 158 __cpu_replace_ttbr1(pgdp, false); 159 } 160 161 /* 162 * It would be nice to return ASIDs back to the allocator, but unfortunately 163 * that introduces a race with a generation rollover where we could erroneously 164 * free an ASID allocated in a future generation. We could workaround this by 165 * freeing the ASID from the context of the dying mm (e.g. in arch_exit_mmap), 166 * but we'd then need to make sure that we didn't dirty any TLBs afterwards. 167 * Setting a reserved TTBR0 or EPD0 would work, but it all gets ugly when you 168 * take CPU migration into account. 169 */ 170 void check_and_switch_context(struct mm_struct *mm); 171 172 #define init_new_context(tsk, mm) init_new_context(tsk, mm) 173 static inline int 174 init_new_context(struct task_struct *tsk, struct mm_struct *mm) 175 { 176 atomic64_set(&mm->context.id, 0); 177 refcount_set(&mm->context.pinned, 0); 178 return 0; 179 } 180 181 #ifdef CONFIG_ARM64_SW_TTBR0_PAN 182 static inline void update_saved_ttbr0(struct task_struct *tsk, 183 struct mm_struct *mm) 184 { 185 u64 ttbr; 186 187 if (!system_uses_ttbr0_pan()) 188 return; 189 190 if (mm == &init_mm) 191 ttbr = phys_to_ttbr(__pa_symbol(reserved_pg_dir)); 192 else 193 ttbr = phys_to_ttbr(virt_to_phys(mm->pgd)) | ASID(mm) << 48; 194 195 WRITE_ONCE(task_thread_info(tsk)->ttbr0, ttbr); 196 } 197 #else 198 static inline void update_saved_ttbr0(struct task_struct *tsk, 199 struct mm_struct *mm) 200 { 201 } 202 #endif 203 204 #define enter_lazy_tlb enter_lazy_tlb 205 static inline void 206 enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) 207 { 208 /* 209 * We don't actually care about the ttbr0 mapping, so point it at the 210 * zero page. 211 */ 212 update_saved_ttbr0(tsk, &init_mm); 213 } 214 215 static inline void __switch_mm(struct mm_struct *next) 216 { 217 /* 218 * init_mm.pgd does not contain any user mappings and it is always 219 * active for kernel addresses in TTBR1. Just set the reserved TTBR0. 220 */ 221 if (next == &init_mm) { 222 cpu_set_reserved_ttbr0(); 223 return; 224 } 225 226 check_and_switch_context(next); 227 } 228 229 static inline void 230 switch_mm(struct mm_struct *prev, struct mm_struct *next, 231 struct task_struct *tsk) 232 { 233 if (prev != next) 234 __switch_mm(next); 235 236 /* 237 * Update the saved TTBR0_EL1 of the scheduled-in task as the previous 238 * value may have not been initialised yet (activate_mm caller) or the 239 * ASID has changed since the last run (following the context switch 240 * of another thread of the same process). 241 */ 242 update_saved_ttbr0(tsk, next); 243 } 244 245 static inline const struct cpumask * 246 task_cpu_possible_mask(struct task_struct *p) 247 { 248 if (!static_branch_unlikely(&arm64_mismatched_32bit_el0)) 249 return cpu_possible_mask; 250 251 if (!is_compat_thread(task_thread_info(p))) 252 return cpu_possible_mask; 253 254 return system_32bit_el0_cpumask(); 255 } 256 #define task_cpu_possible_mask task_cpu_possible_mask 257 258 void verify_cpu_asid_bits(void); 259 void post_ttbr_update_workaround(void); 260 261 unsigned long arm64_mm_context_get(struct mm_struct *mm); 262 void arm64_mm_context_put(struct mm_struct *mm); 263 264 #define mm_untag_mask mm_untag_mask 265 static inline unsigned long mm_untag_mask(struct mm_struct *mm) 266 { 267 return -1UL >> 8; 268 } 269 270 #include <asm-generic/mmu_context.h> 271 272 #endif /* !__ASSEMBLY__ */ 273 274 #endif /* !__ASM_MMU_CONTEXT_H */ 275