1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Based on arch/arm/include/asm/mmu_context.h 4 * 5 * Copyright (C) 1996 Russell King. 6 * Copyright (C) 2012 ARM Ltd. 7 */ 8 #ifndef __ASM_MMU_CONTEXT_H 9 #define __ASM_MMU_CONTEXT_H 10 11 #ifndef __ASSEMBLY__ 12 13 #include <linux/compiler.h> 14 #include <linux/sched.h> 15 #include <linux/sched/hotplug.h> 16 #include <linux/mm_types.h> 17 #include <linux/pgtable.h> 18 19 #include <asm/cacheflush.h> 20 #include <asm/cpufeature.h> 21 #include <asm/daifflags.h> 22 #include <asm/proc-fns.h> 23 #include <asm-generic/mm_hooks.h> 24 #include <asm/cputype.h> 25 #include <asm/sysreg.h> 26 #include <asm/tlbflush.h> 27 28 extern bool rodata_full; 29 30 static inline void contextidr_thread_switch(struct task_struct *next) 31 { 32 if (!IS_ENABLED(CONFIG_PID_IN_CONTEXTIDR)) 33 return; 34 35 write_sysreg(task_pid_nr(next), contextidr_el1); 36 isb(); 37 } 38 39 /* 40 * Set TTBR0 to reserved_pg_dir. No translations will be possible via TTBR0. 41 */ 42 static inline void cpu_set_reserved_ttbr0_nosync(void) 43 { 44 unsigned long ttbr = phys_to_ttbr(__pa_symbol(reserved_pg_dir)); 45 46 write_sysreg(ttbr, ttbr0_el1); 47 } 48 49 static inline void cpu_set_reserved_ttbr0(void) 50 { 51 cpu_set_reserved_ttbr0_nosync(); 52 isb(); 53 } 54 55 void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm); 56 57 static inline void cpu_switch_mm(pgd_t *pgd, struct mm_struct *mm) 58 { 59 BUG_ON(pgd == swapper_pg_dir); 60 cpu_do_switch_mm(virt_to_phys(pgd),mm); 61 } 62 63 /* 64 * TCR.T0SZ value to use when the ID map is active. Usually equals 65 * TCR_T0SZ(VA_BITS), unless system RAM is positioned very high in 66 * physical memory, in which case it will be smaller. 67 */ 68 extern int idmap_t0sz; 69 70 /* 71 * Ensure TCR.T0SZ is set to the provided value. 72 */ 73 static inline void __cpu_set_tcr_t0sz(unsigned long t0sz) 74 { 75 unsigned long tcr = read_sysreg(tcr_el1); 76 77 if ((tcr & TCR_T0SZ_MASK) >> TCR_T0SZ_OFFSET == t0sz) 78 return; 79 80 tcr &= ~TCR_T0SZ_MASK; 81 tcr |= t0sz << TCR_T0SZ_OFFSET; 82 write_sysreg(tcr, tcr_el1); 83 isb(); 84 } 85 86 #define cpu_set_default_tcr_t0sz() __cpu_set_tcr_t0sz(TCR_T0SZ(vabits_actual)) 87 #define cpu_set_idmap_tcr_t0sz() __cpu_set_tcr_t0sz(idmap_t0sz) 88 89 /* 90 * Remove the idmap from TTBR0_EL1 and install the pgd of the active mm. 91 * 92 * The idmap lives in the same VA range as userspace, but uses global entries 93 * and may use a different TCR_EL1.T0SZ. To avoid issues resulting from 94 * speculative TLB fetches, we must temporarily install the reserved page 95 * tables while we invalidate the TLBs and set up the correct TCR_EL1.T0SZ. 96 * 97 * If current is a not a user task, the mm covers the TTBR1_EL1 page tables, 98 * which should not be installed in TTBR0_EL1. In this case we can leave the 99 * reserved page tables in place. 100 */ 101 static inline void cpu_uninstall_idmap(void) 102 { 103 struct mm_struct *mm = current->active_mm; 104 105 cpu_set_reserved_ttbr0(); 106 local_flush_tlb_all(); 107 cpu_set_default_tcr_t0sz(); 108 109 if (mm != &init_mm && !system_uses_ttbr0_pan()) 110 cpu_switch_mm(mm->pgd, mm); 111 } 112 113 static inline void __cpu_install_idmap(pgd_t *idmap) 114 { 115 cpu_set_reserved_ttbr0(); 116 local_flush_tlb_all(); 117 cpu_set_idmap_tcr_t0sz(); 118 119 cpu_switch_mm(lm_alias(idmap), &init_mm); 120 } 121 122 static inline void cpu_install_idmap(void) 123 { 124 __cpu_install_idmap(idmap_pg_dir); 125 } 126 127 /* 128 * Load our new page tables. A strict BBM approach requires that we ensure that 129 * TLBs are free of any entries that may overlap with the global mappings we are 130 * about to install. 131 * 132 * For a real hibernate/resume/kexec cycle TTBR0 currently points to a zero 133 * page, but TLBs may contain stale ASID-tagged entries (e.g. for EFI runtime 134 * services), while for a userspace-driven test_resume cycle it points to 135 * userspace page tables (and we must point it at a zero page ourselves). 136 * 137 * We change T0SZ as part of installing the idmap. This is undone by 138 * cpu_uninstall_idmap() in __cpu_suspend_exit(). 139 */ 140 static inline void cpu_install_ttbr0(phys_addr_t ttbr0, unsigned long t0sz) 141 { 142 cpu_set_reserved_ttbr0(); 143 local_flush_tlb_all(); 144 __cpu_set_tcr_t0sz(t0sz); 145 146 /* avoid cpu_switch_mm() and its SW-PAN and CNP interactions */ 147 write_sysreg(ttbr0, ttbr0_el1); 148 isb(); 149 } 150 151 /* 152 * Atomically replaces the active TTBR1_EL1 PGD with a new VA-compatible PGD, 153 * avoiding the possibility of conflicting TLB entries being allocated. 154 */ 155 static inline void __cpu_replace_ttbr1(pgd_t *pgdp, pgd_t *idmap, bool cnp) 156 { 157 typedef void (ttbr_replace_func)(phys_addr_t); 158 extern ttbr_replace_func idmap_cpu_replace_ttbr1; 159 ttbr_replace_func *replace_phys; 160 unsigned long daif; 161 162 /* phys_to_ttbr() zeros lower 2 bits of ttbr with 52-bit PA */ 163 phys_addr_t ttbr1 = phys_to_ttbr(virt_to_phys(pgdp)); 164 165 if (cnp) 166 ttbr1 |= TTBR_CNP_BIT; 167 168 replace_phys = (void *)__pa_symbol(idmap_cpu_replace_ttbr1); 169 170 __cpu_install_idmap(idmap); 171 172 /* 173 * We really don't want to take *any* exceptions while TTBR1 is 174 * in the process of being replaced so mask everything. 175 */ 176 daif = local_daif_save(); 177 replace_phys(ttbr1); 178 local_daif_restore(daif); 179 180 cpu_uninstall_idmap(); 181 } 182 183 static inline void cpu_enable_swapper_cnp(void) 184 { 185 __cpu_replace_ttbr1(lm_alias(swapper_pg_dir), idmap_pg_dir, true); 186 } 187 188 static inline void cpu_replace_ttbr1(pgd_t *pgdp, pgd_t *idmap) 189 { 190 /* 191 * Only for early TTBR1 replacement before cpucaps are finalized and 192 * before we've decided whether to use CNP. 193 */ 194 WARN_ON(system_capabilities_finalized()); 195 __cpu_replace_ttbr1(pgdp, idmap, false); 196 } 197 198 /* 199 * It would be nice to return ASIDs back to the allocator, but unfortunately 200 * that introduces a race with a generation rollover where we could erroneously 201 * free an ASID allocated in a future generation. We could workaround this by 202 * freeing the ASID from the context of the dying mm (e.g. in arch_exit_mmap), 203 * but we'd then need to make sure that we didn't dirty any TLBs afterwards. 204 * Setting a reserved TTBR0 or EPD0 would work, but it all gets ugly when you 205 * take CPU migration into account. 206 */ 207 void check_and_switch_context(struct mm_struct *mm); 208 209 #define init_new_context(tsk, mm) init_new_context(tsk, mm) 210 static inline int 211 init_new_context(struct task_struct *tsk, struct mm_struct *mm) 212 { 213 atomic64_set(&mm->context.id, 0); 214 refcount_set(&mm->context.pinned, 0); 215 return 0; 216 } 217 218 #ifdef CONFIG_ARM64_SW_TTBR0_PAN 219 static inline void update_saved_ttbr0(struct task_struct *tsk, 220 struct mm_struct *mm) 221 { 222 u64 ttbr; 223 224 if (!system_uses_ttbr0_pan()) 225 return; 226 227 if (mm == &init_mm) 228 ttbr = phys_to_ttbr(__pa_symbol(reserved_pg_dir)); 229 else 230 ttbr = phys_to_ttbr(virt_to_phys(mm->pgd)) | ASID(mm) << 48; 231 232 WRITE_ONCE(task_thread_info(tsk)->ttbr0, ttbr); 233 } 234 #else 235 static inline void update_saved_ttbr0(struct task_struct *tsk, 236 struct mm_struct *mm) 237 { 238 } 239 #endif 240 241 #define enter_lazy_tlb enter_lazy_tlb 242 static inline void 243 enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) 244 { 245 /* 246 * We don't actually care about the ttbr0 mapping, so point it at the 247 * zero page. 248 */ 249 update_saved_ttbr0(tsk, &init_mm); 250 } 251 252 static inline void __switch_mm(struct mm_struct *next) 253 { 254 /* 255 * init_mm.pgd does not contain any user mappings and it is always 256 * active for kernel addresses in TTBR1. Just set the reserved TTBR0. 257 */ 258 if (next == &init_mm) { 259 cpu_set_reserved_ttbr0(); 260 return; 261 } 262 263 check_and_switch_context(next); 264 } 265 266 static inline void 267 switch_mm(struct mm_struct *prev, struct mm_struct *next, 268 struct task_struct *tsk) 269 { 270 if (prev != next) 271 __switch_mm(next); 272 273 /* 274 * Update the saved TTBR0_EL1 of the scheduled-in task as the previous 275 * value may have not been initialised yet (activate_mm caller) or the 276 * ASID has changed since the last run (following the context switch 277 * of another thread of the same process). 278 */ 279 update_saved_ttbr0(tsk, next); 280 } 281 282 static inline const struct cpumask * 283 task_cpu_possible_mask(struct task_struct *p) 284 { 285 if (!static_branch_unlikely(&arm64_mismatched_32bit_el0)) 286 return cpu_possible_mask; 287 288 if (!is_compat_thread(task_thread_info(p))) 289 return cpu_possible_mask; 290 291 return system_32bit_el0_cpumask(); 292 } 293 #define task_cpu_possible_mask task_cpu_possible_mask 294 295 void verify_cpu_asid_bits(void); 296 void post_ttbr_update_workaround(void); 297 298 unsigned long arm64_mm_context_get(struct mm_struct *mm); 299 void arm64_mm_context_put(struct mm_struct *mm); 300 301 #define mm_untag_mask mm_untag_mask 302 static inline unsigned long mm_untag_mask(struct mm_struct *mm) 303 { 304 return -1UL >> 8; 305 } 306 307 #include <asm-generic/mmu_context.h> 308 309 #endif /* !__ASSEMBLY__ */ 310 311 #endif /* !__ASM_MMU_CONTEXT_H */ 312