1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 ARM Ltd. 4 */ 5 #ifndef __ASM_MMU_H 6 #define __ASM_MMU_H 7 8 #include <asm/cputype.h> 9 10 #define MMCF_AARCH32 0x1 /* mm context flag for AArch32 executables */ 11 #define USER_ASID_BIT 48 12 #define USER_ASID_FLAG (UL(1) << USER_ASID_BIT) 13 14 #ifndef __ASSEMBLER__ 15 16 #include <linux/refcount.h> 17 #include <asm/cpufeature.h> 18 19 typedef struct { 20 atomic64_t id; 21 #ifdef CONFIG_COMPAT 22 void *sigpage; 23 #endif 24 refcount_t pinned; 25 void *vdso; 26 unsigned long flags; 27 u8 pkey_allocation_map; 28 } mm_context_t; 29 30 /* 31 * We use atomic64_read() here because the ASID for an 'mm_struct' can 32 * be reallocated when scheduling one of its threads following a 33 * rollover event (see new_context() and flush_context()). In this case, 34 * a concurrent TLBI (e.g. via try_to_unmap_one() and ptep_clear_flush()) 35 * may use a stale ASID. This is fine in principle as the new ASID is 36 * guaranteed to be clean in the TLB, but the TLBI routines have to take 37 * care to handle the following race: 38 * 39 * CPU 0 CPU 1 CPU 2 40 * 41 * // ptep_clear_flush(mm) 42 * xchg_relaxed(pte, 0) 43 * DSB ISHST 44 * old = ASID(mm) 45 * | <rollover> 46 * | new = new_context(mm) 47 * \-----------------> atomic_set(mm->context.id, new) 48 * cpu_switch_mm(mm) 49 * // Hardware walk of pte using new ASID 50 * TLBI(old) 51 * 52 * In this scenario, the barrier on CPU 0 and the dependency on CPU 1 53 * ensure that the page-table walker on CPU 1 *must* see the invalid PTE 54 * written by CPU 0. 55 */ 56 #define ASID(mm) (atomic64_read(&(mm)->context.id) & 0xffff) 57 58 static inline bool arm64_kernel_unmapped_at_el0(void) 59 { 60 return alternative_has_cap_unlikely(ARM64_UNMAP_KERNEL_AT_EL0); 61 } 62 63 extern void arm64_memblock_init(void); 64 extern void paging_init(void); 65 extern void bootmem_init(void); 66 extern void create_mapping_noalloc(phys_addr_t phys, unsigned long virt, 67 phys_addr_t size, pgprot_t prot); 68 extern void create_pgd_mapping(struct mm_struct *mm, phys_addr_t phys, 69 unsigned long virt, phys_addr_t size, 70 pgprot_t prot, bool page_mappings_only); 71 extern void *fixmap_remap_fdt(phys_addr_t dt_phys, int *size, pgprot_t prot); 72 extern void mark_linear_text_alias_ro(void); 73 extern int split_kernel_leaf_mapping(unsigned long start, unsigned long end); 74 extern void linear_map_maybe_split_to_ptes(void); 75 76 /* 77 * This check is triggered during the early boot before the cpufeature 78 * is initialised. Checking the status on the local CPU allows the boot 79 * CPU to detect the need for non-global mappings and thus avoiding a 80 * pagetable re-write after all the CPUs are booted. This check will be 81 * anyway run on individual CPUs, allowing us to get the consistent 82 * state once the SMP CPUs are up and thus make the switch to non-global 83 * mappings if required. 84 */ 85 static inline bool kaslr_requires_kpti(void) 86 { 87 /* 88 * E0PD does a similar job to KPTI so can be used instead 89 * where available. 90 */ 91 if (IS_ENABLED(CONFIG_ARM64_E0PD)) { 92 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1); 93 if (cpuid_feature_extract_unsigned_field(mmfr2, 94 ID_AA64MMFR2_EL1_E0PD_SHIFT)) 95 return false; 96 } 97 98 return true; 99 } 100 101 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 102 void kpti_install_ng_mappings(void); 103 #else 104 static inline void kpti_install_ng_mappings(void) {} 105 #endif 106 107 extern bool page_alloc_available; 108 109 #endif /* !__ASSEMBLER__ */ 110 #endif 111