1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __ARM64_KVM_NESTED_H 3 #define __ARM64_KVM_NESTED_H 4 5 #include <linux/bitfield.h> 6 #include <linux/kvm_host.h> 7 #include <asm/kvm_emulate.h> 8 #include <asm/kvm_pgtable.h> 9 10 static inline bool vcpu_has_nv(const struct kvm_vcpu *vcpu) 11 { 12 return (!__is_defined(__KVM_NVHE_HYPERVISOR__) && 13 cpus_have_final_cap(ARM64_HAS_NESTED_VIRT) && 14 vcpu_has_feature(vcpu, KVM_ARM_VCPU_HAS_EL2)); 15 } 16 17 /* Translation helpers from non-VHE EL2 to EL1 */ 18 static inline u64 tcr_el2_ps_to_tcr_el1_ips(u64 tcr_el2) 19 { 20 return (u64)FIELD_GET(TCR_EL2_PS_MASK, tcr_el2) << TCR_IPS_SHIFT; 21 } 22 23 static inline u64 translate_tcr_el2_to_tcr_el1(u64 tcr) 24 { 25 return TCR_EPD1_MASK | /* disable TTBR1_EL1 */ 26 ((tcr & TCR_EL2_TBI) ? TCR_TBI0 : 0) | 27 tcr_el2_ps_to_tcr_el1_ips(tcr) | 28 (tcr & TCR_EL2_TG0_MASK) | 29 (tcr & TCR_EL2_ORGN0_MASK) | 30 (tcr & TCR_EL2_IRGN0_MASK) | 31 (tcr & TCR_EL2_T0SZ_MASK); 32 } 33 34 static inline u64 translate_cptr_el2_to_cpacr_el1(u64 cptr_el2) 35 { 36 u64 cpacr_el1 = CPACR_EL1_RES1; 37 38 if (cptr_el2 & CPTR_EL2_TTA) 39 cpacr_el1 |= CPACR_EL1_TTA; 40 if (!(cptr_el2 & CPTR_EL2_TFP)) 41 cpacr_el1 |= CPACR_EL1_FPEN; 42 if (!(cptr_el2 & CPTR_EL2_TZ)) 43 cpacr_el1 |= CPACR_EL1_ZEN; 44 45 cpacr_el1 |= cptr_el2 & (CPTR_EL2_TCPAC | CPTR_EL2_TAM); 46 47 return cpacr_el1; 48 } 49 50 static inline u64 translate_sctlr_el2_to_sctlr_el1(u64 val) 51 { 52 /* Only preserve the minimal set of bits we support */ 53 val &= (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | SCTLR_ELx_SA | 54 SCTLR_ELx_I | SCTLR_ELx_IESB | SCTLR_ELx_WXN | SCTLR_ELx_EE); 55 val |= SCTLR_EL1_RES1; 56 57 return val; 58 } 59 60 static inline u64 translate_ttbr0_el2_to_ttbr0_el1(u64 ttbr0) 61 { 62 /* Clear the ASID field */ 63 return ttbr0 & ~GENMASK_ULL(63, 48); 64 } 65 66 extern bool forward_smc_trap(struct kvm_vcpu *vcpu); 67 extern bool forward_debug_exception(struct kvm_vcpu *vcpu); 68 extern void kvm_init_nested(struct kvm *kvm); 69 extern int kvm_vcpu_init_nested(struct kvm_vcpu *vcpu); 70 extern void kvm_init_nested_s2_mmu(struct kvm_s2_mmu *mmu); 71 extern struct kvm_s2_mmu *lookup_s2_mmu(struct kvm_vcpu *vcpu); 72 73 union tlbi_info; 74 75 extern void kvm_s2_mmu_iterate_by_vmid(struct kvm *kvm, u16 vmid, 76 const union tlbi_info *info, 77 void (*)(struct kvm_s2_mmu *, 78 const union tlbi_info *)); 79 extern void kvm_vcpu_load_hw_mmu(struct kvm_vcpu *vcpu); 80 extern void kvm_vcpu_put_hw_mmu(struct kvm_vcpu *vcpu); 81 82 extern void check_nested_vcpu_requests(struct kvm_vcpu *vcpu); 83 extern void kvm_nested_flush_hwstate(struct kvm_vcpu *vcpu); 84 extern void kvm_nested_sync_hwstate(struct kvm_vcpu *vcpu); 85 86 extern void kvm_nested_setup_mdcr_el2(struct kvm_vcpu *vcpu); 87 88 struct kvm_s2_trans { 89 phys_addr_t output; 90 unsigned long block_size; 91 bool writable; 92 bool readable; 93 int level; 94 u32 esr; 95 u64 desc; 96 }; 97 98 static inline phys_addr_t kvm_s2_trans_output(struct kvm_s2_trans *trans) 99 { 100 return trans->output; 101 } 102 103 static inline unsigned long kvm_s2_trans_size(struct kvm_s2_trans *trans) 104 { 105 return trans->block_size; 106 } 107 108 static inline u32 kvm_s2_trans_esr(struct kvm_s2_trans *trans) 109 { 110 return trans->esr; 111 } 112 113 static inline bool kvm_s2_trans_readable(struct kvm_s2_trans *trans) 114 { 115 return trans->readable; 116 } 117 118 static inline bool kvm_s2_trans_writable(struct kvm_s2_trans *trans) 119 { 120 return trans->writable; 121 } 122 123 static inline bool kvm_s2_trans_executable(struct kvm_s2_trans *trans) 124 { 125 return !(trans->desc & BIT(54)); 126 } 127 128 extern int kvm_walk_nested_s2(struct kvm_vcpu *vcpu, phys_addr_t gipa, 129 struct kvm_s2_trans *result); 130 extern int kvm_s2_handle_perm_fault(struct kvm_vcpu *vcpu, 131 struct kvm_s2_trans *trans); 132 extern int kvm_inject_s2_fault(struct kvm_vcpu *vcpu, u64 esr_el2); 133 extern void kvm_nested_s2_wp(struct kvm *kvm); 134 extern void kvm_nested_s2_unmap(struct kvm *kvm, bool may_block); 135 extern void kvm_nested_s2_flush(struct kvm *kvm); 136 137 unsigned long compute_tlb_inval_range(struct kvm_s2_mmu *mmu, u64 val); 138 139 static inline bool kvm_supported_tlbi_s1e1_op(struct kvm_vcpu *vpcu, u32 instr) 140 { 141 struct kvm *kvm = vpcu->kvm; 142 u8 CRm = sys_reg_CRm(instr); 143 144 if (!(sys_reg_Op0(instr) == TLBI_Op0 && 145 sys_reg_Op1(instr) == TLBI_Op1_EL1)) 146 return false; 147 148 if (!(sys_reg_CRn(instr) == TLBI_CRn_XS || 149 (sys_reg_CRn(instr) == TLBI_CRn_nXS && 150 kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)))) 151 return false; 152 153 if (CRm == TLBI_CRm_nROS && 154 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 155 return false; 156 157 if ((CRm == TLBI_CRm_RIS || CRm == TLBI_CRm_ROS || 158 CRm == TLBI_CRm_RNS) && 159 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 160 return false; 161 162 return true; 163 } 164 165 static inline bool kvm_supported_tlbi_s1e2_op(struct kvm_vcpu *vpcu, u32 instr) 166 { 167 struct kvm *kvm = vpcu->kvm; 168 u8 CRm = sys_reg_CRm(instr); 169 170 if (!(sys_reg_Op0(instr) == TLBI_Op0 && 171 sys_reg_Op1(instr) == TLBI_Op1_EL2)) 172 return false; 173 174 if (!(sys_reg_CRn(instr) == TLBI_CRn_XS || 175 (sys_reg_CRn(instr) == TLBI_CRn_nXS && 176 kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)))) 177 return false; 178 179 if (CRm == TLBI_CRm_IPAIS || CRm == TLBI_CRm_IPAONS) 180 return false; 181 182 if (CRm == TLBI_CRm_nROS && 183 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 184 return false; 185 186 if ((CRm == TLBI_CRm_RIS || CRm == TLBI_CRm_ROS || 187 CRm == TLBI_CRm_RNS) && 188 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 189 return false; 190 191 return true; 192 } 193 194 int kvm_init_nv_sysregs(struct kvm_vcpu *vcpu); 195 u64 limit_nv_id_reg(struct kvm *kvm, u32 reg, u64 val); 196 197 #ifdef CONFIG_ARM64_PTR_AUTH 198 bool kvm_auth_eretax(struct kvm_vcpu *vcpu, u64 *elr); 199 #else 200 static inline bool kvm_auth_eretax(struct kvm_vcpu *vcpu, u64 *elr) 201 { 202 /* We really should never execute this... */ 203 WARN_ON_ONCE(1); 204 *elr = 0xbad9acc0debadbad; 205 return false; 206 } 207 #endif 208 209 #define KVM_NV_GUEST_MAP_SZ (KVM_PGTABLE_PROT_SW1 | KVM_PGTABLE_PROT_SW0) 210 211 static inline u64 kvm_encode_nested_level(struct kvm_s2_trans *trans) 212 { 213 return FIELD_PREP(KVM_NV_GUEST_MAP_SZ, trans->level); 214 } 215 216 /* Adjust alignment for the contiguous bit as per StageOA() */ 217 #define contiguous_bit_shift(d, wi, l) \ 218 ({ \ 219 u8 shift = 0; \ 220 \ 221 if ((d) & PTE_CONT) { \ 222 switch (BIT((wi)->pgshift)) { \ 223 case SZ_4K: \ 224 shift = 4; \ 225 break; \ 226 case SZ_16K: \ 227 shift = (l) == 2 ? 5 : 7; \ 228 break; \ 229 case SZ_64K: \ 230 shift = 5; \ 231 break; \ 232 } \ 233 } \ 234 \ 235 shift; \ 236 }) 237 238 static inline u64 decode_range_tlbi(u64 val, u64 *range, u16 *asid) 239 { 240 u64 base, tg, num, scale; 241 int shift; 242 243 tg = FIELD_GET(GENMASK(47, 46), val); 244 245 switch(tg) { 246 case 1: 247 shift = 12; 248 break; 249 case 2: 250 shift = 14; 251 break; 252 case 3: 253 default: /* IMPDEF: handle tg==0 as 64k */ 254 shift = 16; 255 break; 256 } 257 258 base = (val & GENMASK(36, 0)) << shift; 259 260 if (asid) 261 *asid = FIELD_GET(TLBIR_ASID_MASK, val); 262 263 scale = FIELD_GET(GENMASK(45, 44), val); 264 num = FIELD_GET(GENMASK(43, 39), val); 265 *range = __TLBI_RANGE_PAGES(num, scale) << shift; 266 267 return base; 268 } 269 270 static inline unsigned int ps_to_output_size(unsigned int ps, bool pa52bit) 271 { 272 switch (ps) { 273 case 0: return 32; 274 case 1: return 36; 275 case 2: return 40; 276 case 3: return 42; 277 case 4: return 44; 278 case 5: return 48; 279 case 6: if (pa52bit) 280 return 52; 281 fallthrough; 282 default: 283 return 48; 284 } 285 } 286 287 enum trans_regime { 288 TR_EL10, 289 TR_EL20, 290 TR_EL2, 291 }; 292 293 struct s1_walk_info; 294 295 struct s1_walk_context { 296 struct s1_walk_info *wi; 297 u64 table_ipa; 298 int level; 299 }; 300 301 struct s1_walk_filter { 302 int (*fn)(struct s1_walk_context *, void *); 303 void *priv; 304 }; 305 306 struct s1_walk_info { 307 struct s1_walk_filter *filter; 308 u64 baddr; 309 enum trans_regime regime; 310 unsigned int max_oa_bits; 311 unsigned int pgshift; 312 unsigned int txsz; 313 int sl; 314 u8 sh; 315 bool as_el0; 316 bool hpd; 317 bool e0poe; 318 bool poe; 319 bool pan; 320 bool be; 321 bool s2; 322 bool pa52bit; 323 }; 324 325 struct s1_walk_result { 326 union { 327 struct { 328 u64 desc; 329 u64 pa; 330 s8 level; 331 u8 APTable; 332 bool nG; 333 u16 asid; 334 bool UXNTable; 335 bool PXNTable; 336 bool uwxn; 337 bool uov; 338 bool ur; 339 bool uw; 340 bool ux; 341 bool pwxn; 342 bool pov; 343 bool pr; 344 bool pw; 345 bool px; 346 }; 347 struct { 348 u8 fst; 349 bool ptw; 350 bool s2; 351 }; 352 }; 353 bool failed; 354 }; 355 356 int __kvm_translate_va(struct kvm_vcpu *vcpu, struct s1_walk_info *wi, 357 struct s1_walk_result *wr, u64 va); 358 int __kvm_find_s1_desc_level(struct kvm_vcpu *vcpu, u64 va, u64 ipa, 359 int *level); 360 361 /* VNCR management */ 362 int kvm_vcpu_allocate_vncr_tlb(struct kvm_vcpu *vcpu); 363 int kvm_handle_vncr_abort(struct kvm_vcpu *vcpu); 364 void kvm_handle_s1e2_tlbi(struct kvm_vcpu *vcpu, u32 inst, u64 val); 365 366 #define vncr_fixmap(c) \ 367 ({ \ 368 u32 __c = (c); \ 369 BUG_ON(__c >= NR_CPUS); \ 370 (FIX_VNCR - __c); \ 371 }) 372 373 #endif /* __ARM64_KVM_NESTED_H */ 374