1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __ARM64_KVM_NESTED_H 3 #define __ARM64_KVM_NESTED_H 4 5 #include <linux/bitfield.h> 6 #include <linux/kvm_host.h> 7 #include <asm/kvm_emulate.h> 8 #include <asm/kvm_pgtable.h> 9 10 static inline bool vcpu_has_nv(const struct kvm_vcpu *vcpu) 11 { 12 return (!__is_defined(__KVM_NVHE_HYPERVISOR__) && 13 cpus_have_final_cap(ARM64_HAS_NESTED_VIRT) && 14 vcpu_has_feature(vcpu, KVM_ARM_VCPU_HAS_EL2)); 15 } 16 17 /* Translation helpers from non-VHE EL2 to EL1 */ 18 static inline u64 tcr_el2_ps_to_tcr_el1_ips(u64 tcr_el2) 19 { 20 return (u64)FIELD_GET(TCR_EL2_PS_MASK, tcr_el2) << TCR_IPS_SHIFT; 21 } 22 23 static inline u64 translate_tcr_el2_to_tcr_el1(u64 tcr) 24 { 25 return TCR_EPD1_MASK | /* disable TTBR1_EL1 */ 26 ((tcr & TCR_EL2_TBI) ? TCR_TBI0 : 0) | 27 tcr_el2_ps_to_tcr_el1_ips(tcr) | 28 (tcr & TCR_EL2_TG0_MASK) | 29 (tcr & TCR_EL2_ORGN0_MASK) | 30 (tcr & TCR_EL2_IRGN0_MASK) | 31 (tcr & TCR_EL2_T0SZ_MASK); 32 } 33 34 static inline u64 translate_cptr_el2_to_cpacr_el1(u64 cptr_el2) 35 { 36 u64 cpacr_el1 = CPACR_EL1_RES1; 37 38 if (cptr_el2 & CPTR_EL2_TTA) 39 cpacr_el1 |= CPACR_EL1_TTA; 40 if (!(cptr_el2 & CPTR_EL2_TFP)) 41 cpacr_el1 |= CPACR_EL1_FPEN; 42 if (!(cptr_el2 & CPTR_EL2_TZ)) 43 cpacr_el1 |= CPACR_EL1_ZEN; 44 45 cpacr_el1 |= cptr_el2 & (CPTR_EL2_TCPAC | CPTR_EL2_TAM); 46 47 return cpacr_el1; 48 } 49 50 static inline u64 translate_sctlr_el2_to_sctlr_el1(u64 val) 51 { 52 /* Only preserve the minimal set of bits we support */ 53 val &= (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | SCTLR_ELx_SA | 54 SCTLR_ELx_I | SCTLR_ELx_IESB | SCTLR_ELx_WXN | SCTLR_ELx_EE); 55 val |= SCTLR_EL1_RES1; 56 57 return val; 58 } 59 60 static inline u64 translate_ttbr0_el2_to_ttbr0_el1(u64 ttbr0) 61 { 62 /* Clear the ASID field */ 63 return ttbr0 & ~GENMASK_ULL(63, 48); 64 } 65 66 extern bool forward_smc_trap(struct kvm_vcpu *vcpu); 67 extern bool forward_debug_exception(struct kvm_vcpu *vcpu); 68 extern void kvm_init_nested(struct kvm *kvm); 69 extern int kvm_vcpu_init_nested(struct kvm_vcpu *vcpu); 70 extern void kvm_init_nested_s2_mmu(struct kvm_s2_mmu *mmu); 71 extern struct kvm_s2_mmu *lookup_s2_mmu(struct kvm_vcpu *vcpu); 72 73 union tlbi_info; 74 75 extern void kvm_s2_mmu_iterate_by_vmid(struct kvm *kvm, u16 vmid, 76 const union tlbi_info *info, 77 void (*)(struct kvm_s2_mmu *, 78 const union tlbi_info *)); 79 extern void kvm_vcpu_load_hw_mmu(struct kvm_vcpu *vcpu); 80 extern void kvm_vcpu_put_hw_mmu(struct kvm_vcpu *vcpu); 81 82 extern void check_nested_vcpu_requests(struct kvm_vcpu *vcpu); 83 extern void kvm_nested_flush_hwstate(struct kvm_vcpu *vcpu); 84 extern void kvm_nested_sync_hwstate(struct kvm_vcpu *vcpu); 85 86 struct kvm_s2_trans { 87 phys_addr_t output; 88 unsigned long block_size; 89 bool writable; 90 bool readable; 91 int level; 92 u32 esr; 93 u64 desc; 94 }; 95 96 static inline phys_addr_t kvm_s2_trans_output(struct kvm_s2_trans *trans) 97 { 98 return trans->output; 99 } 100 101 static inline unsigned long kvm_s2_trans_size(struct kvm_s2_trans *trans) 102 { 103 return trans->block_size; 104 } 105 106 static inline u32 kvm_s2_trans_esr(struct kvm_s2_trans *trans) 107 { 108 return trans->esr; 109 } 110 111 static inline bool kvm_s2_trans_readable(struct kvm_s2_trans *trans) 112 { 113 return trans->readable; 114 } 115 116 static inline bool kvm_s2_trans_writable(struct kvm_s2_trans *trans) 117 { 118 return trans->writable; 119 } 120 121 static inline bool kvm_s2_trans_executable(struct kvm_s2_trans *trans) 122 { 123 return !(trans->desc & BIT(54)); 124 } 125 126 extern int kvm_walk_nested_s2(struct kvm_vcpu *vcpu, phys_addr_t gipa, 127 struct kvm_s2_trans *result); 128 extern int kvm_s2_handle_perm_fault(struct kvm_vcpu *vcpu, 129 struct kvm_s2_trans *trans); 130 extern int kvm_inject_s2_fault(struct kvm_vcpu *vcpu, u64 esr_el2); 131 extern void kvm_nested_s2_wp(struct kvm *kvm); 132 extern void kvm_nested_s2_unmap(struct kvm *kvm, bool may_block); 133 extern void kvm_nested_s2_flush(struct kvm *kvm); 134 135 unsigned long compute_tlb_inval_range(struct kvm_s2_mmu *mmu, u64 val); 136 137 static inline bool kvm_supported_tlbi_s1e1_op(struct kvm_vcpu *vpcu, u32 instr) 138 { 139 struct kvm *kvm = vpcu->kvm; 140 u8 CRm = sys_reg_CRm(instr); 141 142 if (!(sys_reg_Op0(instr) == TLBI_Op0 && 143 sys_reg_Op1(instr) == TLBI_Op1_EL1)) 144 return false; 145 146 if (!(sys_reg_CRn(instr) == TLBI_CRn_XS || 147 (sys_reg_CRn(instr) == TLBI_CRn_nXS && 148 kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)))) 149 return false; 150 151 if (CRm == TLBI_CRm_nROS && 152 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 153 return false; 154 155 if ((CRm == TLBI_CRm_RIS || CRm == TLBI_CRm_ROS || 156 CRm == TLBI_CRm_RNS) && 157 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 158 return false; 159 160 return true; 161 } 162 163 static inline bool kvm_supported_tlbi_s1e2_op(struct kvm_vcpu *vpcu, u32 instr) 164 { 165 struct kvm *kvm = vpcu->kvm; 166 u8 CRm = sys_reg_CRm(instr); 167 168 if (!(sys_reg_Op0(instr) == TLBI_Op0 && 169 sys_reg_Op1(instr) == TLBI_Op1_EL2)) 170 return false; 171 172 if (!(sys_reg_CRn(instr) == TLBI_CRn_XS || 173 (sys_reg_CRn(instr) == TLBI_CRn_nXS && 174 kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)))) 175 return false; 176 177 if (CRm == TLBI_CRm_IPAIS || CRm == TLBI_CRm_IPAONS) 178 return false; 179 180 if (CRm == TLBI_CRm_nROS && 181 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 182 return false; 183 184 if ((CRm == TLBI_CRm_RIS || CRm == TLBI_CRm_ROS || 185 CRm == TLBI_CRm_RNS) && 186 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 187 return false; 188 189 return true; 190 } 191 192 int kvm_init_nv_sysregs(struct kvm_vcpu *vcpu); 193 u64 limit_nv_id_reg(struct kvm *kvm, u32 reg, u64 val); 194 195 #ifdef CONFIG_ARM64_PTR_AUTH 196 bool kvm_auth_eretax(struct kvm_vcpu *vcpu, u64 *elr); 197 #else 198 static inline bool kvm_auth_eretax(struct kvm_vcpu *vcpu, u64 *elr) 199 { 200 /* We really should never execute this... */ 201 WARN_ON_ONCE(1); 202 *elr = 0xbad9acc0debadbad; 203 return false; 204 } 205 #endif 206 207 #define KVM_NV_GUEST_MAP_SZ (KVM_PGTABLE_PROT_SW1 | KVM_PGTABLE_PROT_SW0) 208 209 static inline u64 kvm_encode_nested_level(struct kvm_s2_trans *trans) 210 { 211 return FIELD_PREP(KVM_NV_GUEST_MAP_SZ, trans->level); 212 } 213 214 /* Adjust alignment for the contiguous bit as per StageOA() */ 215 #define contiguous_bit_shift(d, wi, l) \ 216 ({ \ 217 u8 shift = 0; \ 218 \ 219 if ((d) & PTE_CONT) { \ 220 switch (BIT((wi)->pgshift)) { \ 221 case SZ_4K: \ 222 shift = 4; \ 223 break; \ 224 case SZ_16K: \ 225 shift = (l) == 2 ? 5 : 7; \ 226 break; \ 227 case SZ_64K: \ 228 shift = 5; \ 229 break; \ 230 } \ 231 } \ 232 \ 233 shift; \ 234 }) 235 236 static inline u64 decode_range_tlbi(u64 val, u64 *range, u16 *asid) 237 { 238 u64 base, tg, num, scale; 239 int shift; 240 241 tg = FIELD_GET(GENMASK(47, 46), val); 242 243 switch(tg) { 244 case 1: 245 shift = 12; 246 break; 247 case 2: 248 shift = 14; 249 break; 250 case 3: 251 default: /* IMPDEF: handle tg==0 as 64k */ 252 shift = 16; 253 break; 254 } 255 256 base = (val & GENMASK(36, 0)) << shift; 257 258 if (asid) 259 *asid = FIELD_GET(TLBIR_ASID_MASK, val); 260 261 scale = FIELD_GET(GENMASK(45, 44), val); 262 num = FIELD_GET(GENMASK(43, 39), val); 263 *range = __TLBI_RANGE_PAGES(num, scale) << shift; 264 265 return base; 266 } 267 268 static inline unsigned int ps_to_output_size(unsigned int ps) 269 { 270 switch (ps) { 271 case 0: return 32; 272 case 1: return 36; 273 case 2: return 40; 274 case 3: return 42; 275 case 4: return 44; 276 case 5: 277 default: 278 return 48; 279 } 280 } 281 282 enum trans_regime { 283 TR_EL10, 284 TR_EL20, 285 TR_EL2, 286 }; 287 288 struct s1_walk_info { 289 u64 baddr; 290 enum trans_regime regime; 291 unsigned int max_oa_bits; 292 unsigned int pgshift; 293 unsigned int txsz; 294 int sl; 295 bool as_el0; 296 bool hpd; 297 bool e0poe; 298 bool poe; 299 bool pan; 300 bool be; 301 bool s2; 302 }; 303 304 struct s1_walk_result { 305 union { 306 struct { 307 u64 desc; 308 u64 pa; 309 s8 level; 310 u8 APTable; 311 bool nG; 312 u16 asid; 313 bool UXNTable; 314 bool PXNTable; 315 bool uwxn; 316 bool uov; 317 bool ur; 318 bool uw; 319 bool ux; 320 bool pwxn; 321 bool pov; 322 bool pr; 323 bool pw; 324 bool px; 325 }; 326 struct { 327 u8 fst; 328 bool ptw; 329 bool s2; 330 }; 331 }; 332 bool failed; 333 }; 334 335 int __kvm_translate_va(struct kvm_vcpu *vcpu, struct s1_walk_info *wi, 336 struct s1_walk_result *wr, u64 va); 337 338 /* VNCR management */ 339 int kvm_vcpu_allocate_vncr_tlb(struct kvm_vcpu *vcpu); 340 int kvm_handle_vncr_abort(struct kvm_vcpu *vcpu); 341 void kvm_handle_s1e2_tlbi(struct kvm_vcpu *vcpu, u32 inst, u64 val); 342 343 #define vncr_fixmap(c) \ 344 ({ \ 345 u32 __c = (c); \ 346 BUG_ON(__c >= NR_CPUS); \ 347 (FIX_VNCR - __c); \ 348 }) 349 350 #endif /* __ARM64_KVM_NESTED_H */ 351