1*e1f358b5SSteven Price /* SPDX-License-Identifier: GPL-2.0 */ 2*e1f358b5SSteven Price /* 3*e1f358b5SSteven Price * Copyright (C) 2020-2021 ARM Ltd. 4*e1f358b5SSteven Price */ 5*e1f358b5SSteven Price #ifndef __ASM_KVM_MTE_H 6*e1f358b5SSteven Price #define __ASM_KVM_MTE_H 7*e1f358b5SSteven Price 8*e1f358b5SSteven Price #ifdef __ASSEMBLY__ 9*e1f358b5SSteven Price 10*e1f358b5SSteven Price #include <asm/sysreg.h> 11*e1f358b5SSteven Price 12*e1f358b5SSteven Price #ifdef CONFIG_ARM64_MTE 13*e1f358b5SSteven Price 14*e1f358b5SSteven Price .macro mte_switch_to_guest g_ctxt, h_ctxt, reg1 15*e1f358b5SSteven Price alternative_if_not ARM64_MTE 16*e1f358b5SSteven Price b .L__skip_switch\@ 17*e1f358b5SSteven Price alternative_else_nop_endif 18*e1f358b5SSteven Price mrs \reg1, hcr_el2 19*e1f358b5SSteven Price tbz \reg1, #(HCR_ATA_SHIFT), .L__skip_switch\@ 20*e1f358b5SSteven Price 21*e1f358b5SSteven Price mrs_s \reg1, SYS_RGSR_EL1 22*e1f358b5SSteven Price str \reg1, [\h_ctxt, #CPU_RGSR_EL1] 23*e1f358b5SSteven Price mrs_s \reg1, SYS_GCR_EL1 24*e1f358b5SSteven Price str \reg1, [\h_ctxt, #CPU_GCR_EL1] 25*e1f358b5SSteven Price 26*e1f358b5SSteven Price ldr \reg1, [\g_ctxt, #CPU_RGSR_EL1] 27*e1f358b5SSteven Price msr_s SYS_RGSR_EL1, \reg1 28*e1f358b5SSteven Price ldr \reg1, [\g_ctxt, #CPU_GCR_EL1] 29*e1f358b5SSteven Price msr_s SYS_GCR_EL1, \reg1 30*e1f358b5SSteven Price 31*e1f358b5SSteven Price .L__skip_switch\@: 32*e1f358b5SSteven Price .endm 33*e1f358b5SSteven Price 34*e1f358b5SSteven Price .macro mte_switch_to_hyp g_ctxt, h_ctxt, reg1 35*e1f358b5SSteven Price alternative_if_not ARM64_MTE 36*e1f358b5SSteven Price b .L__skip_switch\@ 37*e1f358b5SSteven Price alternative_else_nop_endif 38*e1f358b5SSteven Price mrs \reg1, hcr_el2 39*e1f358b5SSteven Price tbz \reg1, #(HCR_ATA_SHIFT), .L__skip_switch\@ 40*e1f358b5SSteven Price 41*e1f358b5SSteven Price mrs_s \reg1, SYS_RGSR_EL1 42*e1f358b5SSteven Price str \reg1, [\g_ctxt, #CPU_RGSR_EL1] 43*e1f358b5SSteven Price mrs_s \reg1, SYS_GCR_EL1 44*e1f358b5SSteven Price str \reg1, [\g_ctxt, #CPU_GCR_EL1] 45*e1f358b5SSteven Price 46*e1f358b5SSteven Price ldr \reg1, [\h_ctxt, #CPU_RGSR_EL1] 47*e1f358b5SSteven Price msr_s SYS_RGSR_EL1, \reg1 48*e1f358b5SSteven Price ldr \reg1, [\h_ctxt, #CPU_GCR_EL1] 49*e1f358b5SSteven Price msr_s SYS_GCR_EL1, \reg1 50*e1f358b5SSteven Price 51*e1f358b5SSteven Price isb 52*e1f358b5SSteven Price 53*e1f358b5SSteven Price .L__skip_switch\@: 54*e1f358b5SSteven Price .endm 55*e1f358b5SSteven Price 56*e1f358b5SSteven Price #else /* !CONFIG_ARM64_MTE */ 57*e1f358b5SSteven Price 58*e1f358b5SSteven Price .macro mte_switch_to_guest g_ctxt, h_ctxt, reg1 59*e1f358b5SSteven Price .endm 60*e1f358b5SSteven Price 61*e1f358b5SSteven Price .macro mte_switch_to_hyp g_ctxt, h_ctxt, reg1 62*e1f358b5SSteven Price .endm 63*e1f358b5SSteven Price 64*e1f358b5SSteven Price #endif /* CONFIG_ARM64_MTE */ 65*e1f358b5SSteven Price #endif /* __ASSEMBLY__ */ 66*e1f358b5SSteven Price #endif /* __ASM_KVM_MTE_H */ 67