1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #ifndef __ARM64_KVM_MMU_H__ 8 #define __ARM64_KVM_MMU_H__ 9 10 #include <asm/page.h> 11 #include <asm/memory.h> 12 #include <asm/mmu.h> 13 #include <asm/cpufeature.h> 14 15 /* 16 * As ARMv8.0 only has the TTBR0_EL2 register, we cannot express 17 * "negative" addresses. This makes it impossible to directly share 18 * mappings with the kernel. 19 * 20 * Instead, give the HYP mode its own VA region at a fixed offset from 21 * the kernel by just masking the top bits (which are all ones for a 22 * kernel address). We need to find out how many bits to mask. 23 * 24 * We want to build a set of page tables that cover both parts of the 25 * idmap (the trampoline page used to initialize EL2), and our normal 26 * runtime VA space, at the same time. 27 * 28 * Given that the kernel uses VA_BITS for its entire address space, 29 * and that half of that space (VA_BITS - 1) is used for the linear 30 * mapping, we can also limit the EL2 space to (VA_BITS - 1). 31 * 32 * The main question is "Within the VA_BITS space, does EL2 use the 33 * top or the bottom half of that space to shadow the kernel's linear 34 * mapping?". As we need to idmap the trampoline page, this is 35 * determined by the range in which this page lives. 36 * 37 * If the page is in the bottom half, we have to use the top half. If 38 * the page is in the top half, we have to use the bottom half: 39 * 40 * T = __pa_symbol(__hyp_idmap_text_start) 41 * if (T & BIT(VA_BITS - 1)) 42 * HYP_VA_MIN = 0 //idmap in upper half 43 * else 44 * HYP_VA_MIN = 1 << (VA_BITS - 1) 45 * HYP_VA_MAX = HYP_VA_MIN + (1 << (VA_BITS - 1)) - 1 46 * 47 * When using VHE, there are no separate hyp mappings and all KVM 48 * functionality is already mapped as part of the main kernel 49 * mappings, and none of this applies in that case. 50 */ 51 52 #ifdef __ASSEMBLY__ 53 54 #include <asm/alternative.h> 55 56 /* 57 * Convert a kernel VA into a HYP VA. 58 * reg: VA to be converted. 59 * 60 * The actual code generation takes place in kvm_update_va_mask, and 61 * the instructions below are only there to reserve the space and 62 * perform the register allocation (kvm_update_va_mask uses the 63 * specific registers encoded in the instructions). 64 */ 65 .macro kern_hyp_va reg 66 #ifndef __KVM_VHE_HYPERVISOR__ 67 alternative_cb ARM64_ALWAYS_SYSTEM, kvm_update_va_mask 68 and \reg, \reg, #1 /* mask with va_mask */ 69 ror \reg, \reg, #1 /* rotate to the first tag bit */ 70 add \reg, \reg, #0 /* insert the low 12 bits of the tag */ 71 add \reg, \reg, #0, lsl 12 /* insert the top 12 bits of the tag */ 72 ror \reg, \reg, #63 /* rotate back */ 73 alternative_cb_end 74 #endif 75 .endm 76 77 /* 78 * Convert a hypervisor VA to a PA 79 * reg: hypervisor address to be converted in place 80 * tmp: temporary register 81 */ 82 .macro hyp_pa reg, tmp 83 ldr_l \tmp, hyp_physvirt_offset 84 add \reg, \reg, \tmp 85 .endm 86 87 /* 88 * Convert a hypervisor VA to a kernel image address 89 * reg: hypervisor address to be converted in place 90 * tmp: temporary register 91 * 92 * The actual code generation takes place in kvm_get_kimage_voffset, and 93 * the instructions below are only there to reserve the space and 94 * perform the register allocation (kvm_get_kimage_voffset uses the 95 * specific registers encoded in the instructions). 96 */ 97 .macro hyp_kimg_va reg, tmp 98 /* Convert hyp VA -> PA. */ 99 hyp_pa \reg, \tmp 100 101 /* Load kimage_voffset. */ 102 alternative_cb ARM64_ALWAYS_SYSTEM, kvm_get_kimage_voffset 103 movz \tmp, #0 104 movk \tmp, #0, lsl #16 105 movk \tmp, #0, lsl #32 106 movk \tmp, #0, lsl #48 107 alternative_cb_end 108 109 /* Convert PA -> kimg VA. */ 110 add \reg, \reg, \tmp 111 .endm 112 113 #else 114 115 #include <linux/pgtable.h> 116 #include <asm/pgalloc.h> 117 #include <asm/cache.h> 118 #include <asm/cacheflush.h> 119 #include <asm/mmu_context.h> 120 #include <asm/kvm_emulate.h> 121 #include <asm/kvm_host.h> 122 123 void kvm_update_va_mask(struct alt_instr *alt, 124 __le32 *origptr, __le32 *updptr, int nr_inst); 125 void kvm_compute_layout(void); 126 void kvm_apply_hyp_relocations(void); 127 128 #define __hyp_pa(x) (((phys_addr_t)(x)) + hyp_physvirt_offset) 129 130 static __always_inline unsigned long __kern_hyp_va(unsigned long v) 131 { 132 #ifndef __KVM_VHE_HYPERVISOR__ 133 asm volatile(ALTERNATIVE_CB("and %0, %0, #1\n" 134 "ror %0, %0, #1\n" 135 "add %0, %0, #0\n" 136 "add %0, %0, #0, lsl 12\n" 137 "ror %0, %0, #63\n", 138 ARM64_ALWAYS_SYSTEM, 139 kvm_update_va_mask) 140 : "+r" (v)); 141 #endif 142 return v; 143 } 144 145 #define kern_hyp_va(v) ((typeof(v))(__kern_hyp_va((unsigned long)(v)))) 146 147 /* 148 * We currently support using a VM-specified IPA size. For backward 149 * compatibility, the default IPA size is fixed to 40bits. 150 */ 151 #define KVM_PHYS_SHIFT (40) 152 153 #define kvm_phys_shift(mmu) VTCR_EL2_IPA((mmu)->vtcr) 154 #define kvm_phys_size(mmu) (_AC(1, ULL) << kvm_phys_shift(mmu)) 155 #define kvm_phys_mask(mmu) (kvm_phys_size(mmu) - _AC(1, ULL)) 156 157 #include <asm/kvm_pgtable.h> 158 #include <asm/stage2_pgtable.h> 159 160 int kvm_share_hyp(void *from, void *to); 161 void kvm_unshare_hyp(void *from, void *to); 162 int create_hyp_mappings(void *from, void *to, enum kvm_pgtable_prot prot); 163 int __create_hyp_mappings(unsigned long start, unsigned long size, 164 unsigned long phys, enum kvm_pgtable_prot prot); 165 int hyp_alloc_private_va_range(size_t size, unsigned long *haddr); 166 int create_hyp_io_mappings(phys_addr_t phys_addr, size_t size, 167 void __iomem **kaddr, 168 void __iomem **haddr); 169 int create_hyp_exec_mappings(phys_addr_t phys_addr, size_t size, 170 void **haddr); 171 int create_hyp_stack(phys_addr_t phys_addr, unsigned long *haddr); 172 void __init free_hyp_pgds(void); 173 174 void stage2_unmap_vm(struct kvm *kvm); 175 int kvm_init_stage2_mmu(struct kvm *kvm, struct kvm_s2_mmu *mmu, unsigned long type); 176 void kvm_uninit_stage2_mmu(struct kvm *kvm); 177 void kvm_free_stage2_pgd(struct kvm_s2_mmu *mmu); 178 int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa, 179 phys_addr_t pa, unsigned long size, bool writable); 180 181 int kvm_handle_guest_abort(struct kvm_vcpu *vcpu); 182 183 phys_addr_t kvm_mmu_get_httbr(void); 184 phys_addr_t kvm_get_idmap_vector(void); 185 int __init kvm_mmu_init(u32 *hyp_va_bits); 186 187 static inline void *__kvm_vector_slot2addr(void *base, 188 enum arm64_hyp_spectre_vector slot) 189 { 190 int idx = slot - (slot != HYP_VECTOR_DIRECT); 191 192 return base + (idx * SZ_2K); 193 } 194 195 struct kvm; 196 197 #define kvm_flush_dcache_to_poc(a,l) \ 198 dcache_clean_inval_poc((unsigned long)(a), (unsigned long)(a)+(l)) 199 200 static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu) 201 { 202 u64 cache_bits = SCTLR_ELx_M | SCTLR_ELx_C; 203 int reg; 204 205 if (vcpu_is_el2(vcpu)) 206 reg = SCTLR_EL2; 207 else 208 reg = SCTLR_EL1; 209 210 return (vcpu_read_sys_reg(vcpu, reg) & cache_bits) == cache_bits; 211 } 212 213 static inline void __clean_dcache_guest_page(void *va, size_t size) 214 { 215 /* 216 * With FWB, we ensure that the guest always accesses memory using 217 * cacheable attributes, and we don't have to clean to PoC when 218 * faulting in pages. Furthermore, FWB implies IDC, so cleaning to 219 * PoU is not required either in this case. 220 */ 221 if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 222 return; 223 224 kvm_flush_dcache_to_poc(va, size); 225 } 226 227 static inline size_t __invalidate_icache_max_range(void) 228 { 229 u8 iminline; 230 u64 ctr; 231 232 asm volatile(ALTERNATIVE_CB("movz %0, #0\n" 233 "movk %0, #0, lsl #16\n" 234 "movk %0, #0, lsl #32\n" 235 "movk %0, #0, lsl #48\n", 236 ARM64_ALWAYS_SYSTEM, 237 kvm_compute_final_ctr_el0) 238 : "=r" (ctr)); 239 240 iminline = SYS_FIELD_GET(CTR_EL0, IminLine, ctr) + 2; 241 return MAX_DVM_OPS << iminline; 242 } 243 244 static inline void __invalidate_icache_guest_page(void *va, size_t size) 245 { 246 /* 247 * VPIPT I-cache maintenance must be done from EL2. See comment in the 248 * nVHE flavor of __kvm_tlb_flush_vmid_ipa(). 249 */ 250 if (icache_is_vpipt() && read_sysreg(CurrentEL) != CurrentEL_EL2) 251 return; 252 253 /* 254 * Blow the whole I-cache if it is aliasing (i.e. VIPT) or the 255 * invalidation range exceeds our arbitrary limit on invadations by 256 * cache line. 257 */ 258 if (icache_is_aliasing() || size > __invalidate_icache_max_range()) 259 icache_inval_all_pou(); 260 else 261 icache_inval_pou((unsigned long)va, (unsigned long)va + size); 262 } 263 264 void kvm_set_way_flush(struct kvm_vcpu *vcpu); 265 void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled); 266 267 static inline unsigned int kvm_get_vmid_bits(void) 268 { 269 int reg = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 270 271 return get_vmid_bits(reg); 272 } 273 274 /* 275 * We are not in the kvm->srcu critical section most of the time, so we take 276 * the SRCU read lock here. Since we copy the data from the user page, we 277 * can immediately drop the lock again. 278 */ 279 static inline int kvm_read_guest_lock(struct kvm *kvm, 280 gpa_t gpa, void *data, unsigned long len) 281 { 282 int srcu_idx = srcu_read_lock(&kvm->srcu); 283 int ret = kvm_read_guest(kvm, gpa, data, len); 284 285 srcu_read_unlock(&kvm->srcu, srcu_idx); 286 287 return ret; 288 } 289 290 static inline int kvm_write_guest_lock(struct kvm *kvm, gpa_t gpa, 291 const void *data, unsigned long len) 292 { 293 int srcu_idx = srcu_read_lock(&kvm->srcu); 294 int ret = kvm_write_guest(kvm, gpa, data, len); 295 296 srcu_read_unlock(&kvm->srcu, srcu_idx); 297 298 return ret; 299 } 300 301 #define kvm_phys_to_vttbr(addr) phys_to_ttbr(addr) 302 303 /* 304 * When this is (directly or indirectly) used on the TLB invalidation 305 * path, we rely on a previously issued DSB so that page table updates 306 * and VMID reads are correctly ordered. 307 */ 308 static __always_inline u64 kvm_get_vttbr(struct kvm_s2_mmu *mmu) 309 { 310 struct kvm_vmid *vmid = &mmu->vmid; 311 u64 vmid_field, baddr; 312 u64 cnp = system_supports_cnp() ? VTTBR_CNP_BIT : 0; 313 314 baddr = mmu->pgd_phys; 315 vmid_field = atomic64_read(&vmid->id) << VTTBR_VMID_SHIFT; 316 vmid_field &= VTTBR_VMID_MASK(kvm_arm_vmid_bits); 317 return kvm_phys_to_vttbr(baddr) | vmid_field | cnp; 318 } 319 320 /* 321 * Must be called from hyp code running at EL2 with an updated VTTBR 322 * and interrupts disabled. 323 */ 324 static __always_inline void __load_stage2(struct kvm_s2_mmu *mmu, 325 struct kvm_arch *arch) 326 { 327 write_sysreg(mmu->vtcr, vtcr_el2); 328 write_sysreg(kvm_get_vttbr(mmu), vttbr_el2); 329 330 /* 331 * ARM errata 1165522 and 1530923 require the actual execution of the 332 * above before we can switch to the EL1/EL0 translation regime used by 333 * the guest. 334 */ 335 asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT)); 336 } 337 338 static inline struct kvm *kvm_s2_mmu_to_kvm(struct kvm_s2_mmu *mmu) 339 { 340 return container_of(mmu->arch, struct kvm, arch); 341 } 342 #endif /* __ASSEMBLY__ */ 343 #endif /* __ARM64_KVM_MMU_H__ */ 344