1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #ifndef __ARM64_KVM_MMU_H__ 8 #define __ARM64_KVM_MMU_H__ 9 10 #include <asm/page.h> 11 #include <asm/memory.h> 12 #include <asm/mmu.h> 13 #include <asm/cpufeature.h> 14 15 /* 16 * As ARMv8.0 only has the TTBR0_EL2 register, we cannot express 17 * "negative" addresses. This makes it impossible to directly share 18 * mappings with the kernel. 19 * 20 * Instead, give the HYP mode its own VA region at a fixed offset from 21 * the kernel by just masking the top bits (which are all ones for a 22 * kernel address). We need to find out how many bits to mask. 23 * 24 * We want to build a set of page tables that cover both parts of the 25 * idmap (the trampoline page used to initialize EL2), and our normal 26 * runtime VA space, at the same time. 27 * 28 * Given that the kernel uses VA_BITS for its entire address space, 29 * and that half of that space (VA_BITS - 1) is used for the linear 30 * mapping, we can also limit the EL2 space to (VA_BITS - 1). 31 * 32 * The main question is "Within the VA_BITS space, does EL2 use the 33 * top or the bottom half of that space to shadow the kernel's linear 34 * mapping?". As we need to idmap the trampoline page, this is 35 * determined by the range in which this page lives. 36 * 37 * If the page is in the bottom half, we have to use the top half. If 38 * the page is in the top half, we have to use the bottom half: 39 * 40 * T = __pa_symbol(__hyp_idmap_text_start) 41 * if (T & BIT(VA_BITS - 1)) 42 * HYP_VA_MIN = 0 //idmap in upper half 43 * else 44 * HYP_VA_MIN = 1 << (VA_BITS - 1) 45 * HYP_VA_MAX = HYP_VA_MIN + (1 << (VA_BITS - 1)) - 1 46 * 47 * When using VHE, there are no separate hyp mappings and all KVM 48 * functionality is already mapped as part of the main kernel 49 * mappings, and none of this applies in that case. 50 */ 51 52 #ifdef __ASSEMBLY__ 53 54 #include <asm/alternative.h> 55 56 /* 57 * Convert a kernel VA into a HYP VA. 58 * reg: VA to be converted. 59 * 60 * The actual code generation takes place in kvm_update_va_mask, and 61 * the instructions below are only there to reserve the space and 62 * perform the register allocation (kvm_update_va_mask uses the 63 * specific registers encoded in the instructions). 64 */ 65 .macro kern_hyp_va reg 66 alternative_cb kvm_update_va_mask 67 and \reg, \reg, #1 /* mask with va_mask */ 68 ror \reg, \reg, #1 /* rotate to the first tag bit */ 69 add \reg, \reg, #0 /* insert the low 12 bits of the tag */ 70 add \reg, \reg, #0, lsl 12 /* insert the top 12 bits of the tag */ 71 ror \reg, \reg, #63 /* rotate back */ 72 alternative_cb_end 73 .endm 74 75 /* 76 * Convert a kernel image address to a PA 77 * reg: kernel address to be converted in place 78 * tmp: temporary register 79 * 80 * The actual code generation takes place in kvm_get_kimage_voffset, and 81 * the instructions below are only there to reserve the space and 82 * perform the register allocation (kvm_get_kimage_voffset uses the 83 * specific registers encoded in the instructions). 84 */ 85 .macro kimg_pa reg, tmp 86 alternative_cb kvm_get_kimage_voffset 87 movz \tmp, #0 88 movk \tmp, #0, lsl #16 89 movk \tmp, #0, lsl #32 90 movk \tmp, #0, lsl #48 91 alternative_cb_end 92 93 /* reg = __pa(reg) */ 94 sub \reg, \reg, \tmp 95 .endm 96 97 /* 98 * Convert a kernel image address to a hyp VA 99 * reg: kernel address to be converted in place 100 * tmp: temporary register 101 * 102 * The actual code generation takes place in kvm_get_kimage_voffset, and 103 * the instructions below are only there to reserve the space and 104 * perform the register allocation (kvm_update_kimg_phys_offset uses the 105 * specific registers encoded in the instructions). 106 */ 107 .macro kimg_hyp_va reg, tmp 108 alternative_cb kvm_update_kimg_phys_offset 109 movz \tmp, #0 110 movk \tmp, #0, lsl #16 111 movk \tmp, #0, lsl #32 112 movk \tmp, #0, lsl #48 113 alternative_cb_end 114 115 sub \reg, \reg, \tmp 116 mov_q \tmp, PAGE_OFFSET 117 orr \reg, \reg, \tmp 118 kern_hyp_va \reg 119 .endm 120 121 #else 122 123 #include <linux/pgtable.h> 124 #include <asm/pgalloc.h> 125 #include <asm/cache.h> 126 #include <asm/cacheflush.h> 127 #include <asm/mmu_context.h> 128 129 void kvm_update_va_mask(struct alt_instr *alt, 130 __le32 *origptr, __le32 *updptr, int nr_inst); 131 void kvm_compute_layout(void); 132 133 static __always_inline unsigned long __kern_hyp_va(unsigned long v) 134 { 135 asm volatile(ALTERNATIVE_CB("and %0, %0, #1\n" 136 "ror %0, %0, #1\n" 137 "add %0, %0, #0\n" 138 "add %0, %0, #0, lsl 12\n" 139 "ror %0, %0, #63\n", 140 kvm_update_va_mask) 141 : "+r" (v)); 142 return v; 143 } 144 145 #define kern_hyp_va(v) ((typeof(v))(__kern_hyp_va((unsigned long)(v)))) 146 147 static __always_inline unsigned long __kimg_hyp_va(unsigned long v) 148 { 149 unsigned long offset; 150 151 asm volatile(ALTERNATIVE_CB("movz %0, #0\n" 152 "movk %0, #0, lsl #16\n" 153 "movk %0, #0, lsl #32\n" 154 "movk %0, #0, lsl #48\n", 155 kvm_update_kimg_phys_offset) 156 : "=r" (offset)); 157 158 return __kern_hyp_va((v - offset) | PAGE_OFFSET); 159 } 160 161 #define kimg_fn_hyp_va(v) ((typeof(*v))(__kimg_hyp_va((unsigned long)(v)))) 162 163 #define kimg_fn_ptr(x) (typeof(x) **)(x) 164 165 /* 166 * We currently support using a VM-specified IPA size. For backward 167 * compatibility, the default IPA size is fixed to 40bits. 168 */ 169 #define KVM_PHYS_SHIFT (40) 170 171 #define kvm_phys_shift(kvm) VTCR_EL2_IPA(kvm->arch.vtcr) 172 #define kvm_phys_size(kvm) (_AC(1, ULL) << kvm_phys_shift(kvm)) 173 #define kvm_phys_mask(kvm) (kvm_phys_size(kvm) - _AC(1, ULL)) 174 175 #include <asm/kvm_pgtable.h> 176 #include <asm/stage2_pgtable.h> 177 178 int create_hyp_mappings(void *from, void *to, enum kvm_pgtable_prot prot); 179 int create_hyp_io_mappings(phys_addr_t phys_addr, size_t size, 180 void __iomem **kaddr, 181 void __iomem **haddr); 182 int create_hyp_exec_mappings(phys_addr_t phys_addr, size_t size, 183 void **haddr); 184 void free_hyp_pgds(void); 185 186 void stage2_unmap_vm(struct kvm *kvm); 187 int kvm_init_stage2_mmu(struct kvm *kvm, struct kvm_s2_mmu *mmu); 188 void kvm_free_stage2_pgd(struct kvm_s2_mmu *mmu); 189 int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa, 190 phys_addr_t pa, unsigned long size, bool writable); 191 192 int kvm_handle_guest_abort(struct kvm_vcpu *vcpu); 193 194 phys_addr_t kvm_mmu_get_httbr(void); 195 phys_addr_t kvm_get_idmap_vector(void); 196 int kvm_mmu_init(void); 197 198 struct kvm; 199 200 #define kvm_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l)) 201 202 static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu) 203 { 204 return (vcpu_read_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101; 205 } 206 207 static inline void __clean_dcache_guest_page(kvm_pfn_t pfn, unsigned long size) 208 { 209 void *va = page_address(pfn_to_page(pfn)); 210 211 /* 212 * With FWB, we ensure that the guest always accesses memory using 213 * cacheable attributes, and we don't have to clean to PoC when 214 * faulting in pages. Furthermore, FWB implies IDC, so cleaning to 215 * PoU is not required either in this case. 216 */ 217 if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) 218 return; 219 220 kvm_flush_dcache_to_poc(va, size); 221 } 222 223 static inline void __invalidate_icache_guest_page(kvm_pfn_t pfn, 224 unsigned long size) 225 { 226 if (icache_is_aliasing()) { 227 /* any kind of VIPT cache */ 228 __flush_icache_all(); 229 } else if (is_kernel_in_hyp_mode() || !icache_is_vpipt()) { 230 /* PIPT or VPIPT at EL2 (see comment in __kvm_tlb_flush_vmid_ipa) */ 231 void *va = page_address(pfn_to_page(pfn)); 232 233 invalidate_icache_range((unsigned long)va, 234 (unsigned long)va + size); 235 } 236 } 237 238 void kvm_set_way_flush(struct kvm_vcpu *vcpu); 239 void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled); 240 241 static inline unsigned int kvm_get_vmid_bits(void) 242 { 243 int reg = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 244 245 return get_vmid_bits(reg); 246 } 247 248 /* 249 * We are not in the kvm->srcu critical section most of the time, so we take 250 * the SRCU read lock here. Since we copy the data from the user page, we 251 * can immediately drop the lock again. 252 */ 253 static inline int kvm_read_guest_lock(struct kvm *kvm, 254 gpa_t gpa, void *data, unsigned long len) 255 { 256 int srcu_idx = srcu_read_lock(&kvm->srcu); 257 int ret = kvm_read_guest(kvm, gpa, data, len); 258 259 srcu_read_unlock(&kvm->srcu, srcu_idx); 260 261 return ret; 262 } 263 264 static inline int kvm_write_guest_lock(struct kvm *kvm, gpa_t gpa, 265 const void *data, unsigned long len) 266 { 267 int srcu_idx = srcu_read_lock(&kvm->srcu); 268 int ret = kvm_write_guest(kvm, gpa, data, len); 269 270 srcu_read_unlock(&kvm->srcu, srcu_idx); 271 272 return ret; 273 } 274 275 #define kvm_phys_to_vttbr(addr) phys_to_ttbr(addr) 276 277 static __always_inline u64 kvm_get_vttbr(struct kvm_s2_mmu *mmu) 278 { 279 struct kvm_vmid *vmid = &mmu->vmid; 280 u64 vmid_field, baddr; 281 u64 cnp = system_supports_cnp() ? VTTBR_CNP_BIT : 0; 282 283 baddr = mmu->pgd_phys; 284 vmid_field = (u64)vmid->vmid << VTTBR_VMID_SHIFT; 285 return kvm_phys_to_vttbr(baddr) | vmid_field | cnp; 286 } 287 288 /* 289 * Must be called from hyp code running at EL2 with an updated VTTBR 290 * and interrupts disabled. 291 */ 292 static __always_inline void __load_guest_stage2(struct kvm_s2_mmu *mmu) 293 { 294 write_sysreg(kern_hyp_va(mmu->kvm)->arch.vtcr, vtcr_el2); 295 write_sysreg(kvm_get_vttbr(mmu), vttbr_el2); 296 297 /* 298 * ARM errata 1165522 and 1530923 require the actual execution of the 299 * above before we can switch to the EL1/EL0 translation regime used by 300 * the guest. 301 */ 302 asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT)); 303 } 304 305 #endif /* __ASSEMBLY__ */ 306 #endif /* __ARM64_KVM_MMU_H__ */ 307