1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/asm/kvm_host.h: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 */ 10 11 #ifndef __ARM64_KVM_HOST_H__ 12 #define __ARM64_KVM_HOST_H__ 13 14 #include <linux/arm-smccc.h> 15 #include <linux/bitmap.h> 16 #include <linux/types.h> 17 #include <linux/jump_label.h> 18 #include <linux/kvm_types.h> 19 #include <linux/maple_tree.h> 20 #include <linux/percpu.h> 21 #include <linux/psci.h> 22 #include <asm/arch_gicv3.h> 23 #include <asm/barrier.h> 24 #include <asm/cpufeature.h> 25 #include <asm/cputype.h> 26 #include <asm/daifflags.h> 27 #include <asm/fpsimd.h> 28 #include <asm/kvm.h> 29 #include <asm/kvm_asm.h> 30 #include <asm/vncr_mapping.h> 31 32 #define __KVM_HAVE_ARCH_INTC_INITIALIZED 33 34 #define KVM_HALT_POLL_NS_DEFAULT 500000 35 36 #include <kvm/arm_vgic.h> 37 #include <kvm/arm_arch_timer.h> 38 #include <kvm/arm_pmu.h> 39 40 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS 41 42 #define KVM_VCPU_MAX_FEATURES 9 43 #define KVM_VCPU_VALID_FEATURES (BIT(KVM_VCPU_MAX_FEATURES) - 1) 44 45 #define KVM_REQ_SLEEP \ 46 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 47 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1) 48 #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2) 49 #define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(3) 50 #define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4) 51 #define KVM_REQ_RELOAD_PMU KVM_ARCH_REQ(5) 52 #define KVM_REQ_SUSPEND KVM_ARCH_REQ(6) 53 #define KVM_REQ_RESYNC_PMU_EL0 KVM_ARCH_REQ(7) 54 #define KVM_REQ_NESTED_S2_UNMAP KVM_ARCH_REQ(8) 55 #define KVM_REQ_GUEST_HYP_IRQ_PENDING KVM_ARCH_REQ(9) 56 #define KVM_REQ_MAP_L1_VNCR_EL2 KVM_ARCH_REQ(10) 57 58 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \ 59 KVM_DIRTY_LOG_INITIALLY_SET) 60 61 #define KVM_HAVE_MMU_RWLOCK 62 63 /* 64 * Mode of operation configurable with kvm-arm.mode early param. 65 * See Documentation/admin-guide/kernel-parameters.txt for more information. 66 */ 67 enum kvm_mode { 68 KVM_MODE_DEFAULT, 69 KVM_MODE_PROTECTED, 70 KVM_MODE_NV, 71 KVM_MODE_NONE, 72 }; 73 #ifdef CONFIG_KVM 74 enum kvm_mode kvm_get_mode(void); 75 #else 76 static inline enum kvm_mode kvm_get_mode(void) { return KVM_MODE_NONE; }; 77 #endif 78 79 extern unsigned int __ro_after_init kvm_sve_max_vl; 80 extern unsigned int __ro_after_init kvm_host_sve_max_vl; 81 int __init kvm_arm_init_sve(void); 82 83 u32 __attribute_const__ kvm_target_cpu(void); 84 void kvm_reset_vcpu(struct kvm_vcpu *vcpu); 85 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu); 86 87 struct kvm_hyp_memcache { 88 phys_addr_t head; 89 unsigned long nr_pages; 90 struct pkvm_mapping *mapping; /* only used from EL1 */ 91 92 #define HYP_MEMCACHE_ACCOUNT_STAGE2 BIT(1) 93 unsigned long flags; 94 }; 95 96 static inline void push_hyp_memcache(struct kvm_hyp_memcache *mc, 97 phys_addr_t *p, 98 phys_addr_t (*to_pa)(void *virt)) 99 { 100 *p = mc->head; 101 mc->head = to_pa(p); 102 mc->nr_pages++; 103 } 104 105 static inline void *pop_hyp_memcache(struct kvm_hyp_memcache *mc, 106 void *(*to_va)(phys_addr_t phys)) 107 { 108 phys_addr_t *p = to_va(mc->head & PAGE_MASK); 109 110 if (!mc->nr_pages) 111 return NULL; 112 113 mc->head = *p; 114 mc->nr_pages--; 115 116 return p; 117 } 118 119 static inline int __topup_hyp_memcache(struct kvm_hyp_memcache *mc, 120 unsigned long min_pages, 121 void *(*alloc_fn)(void *arg), 122 phys_addr_t (*to_pa)(void *virt), 123 void *arg) 124 { 125 while (mc->nr_pages < min_pages) { 126 phys_addr_t *p = alloc_fn(arg); 127 128 if (!p) 129 return -ENOMEM; 130 push_hyp_memcache(mc, p, to_pa); 131 } 132 133 return 0; 134 } 135 136 static inline void __free_hyp_memcache(struct kvm_hyp_memcache *mc, 137 void (*free_fn)(void *virt, void *arg), 138 void *(*to_va)(phys_addr_t phys), 139 void *arg) 140 { 141 while (mc->nr_pages) 142 free_fn(pop_hyp_memcache(mc, to_va), arg); 143 } 144 145 void free_hyp_memcache(struct kvm_hyp_memcache *mc); 146 int topup_hyp_memcache(struct kvm_hyp_memcache *mc, unsigned long min_pages); 147 148 struct kvm_vmid { 149 atomic64_t id; 150 }; 151 152 struct kvm_s2_mmu { 153 struct kvm_vmid vmid; 154 155 /* 156 * stage2 entry level table 157 * 158 * Two kvm_s2_mmu structures in the same VM can point to the same 159 * pgd here. This happens when running a guest using a 160 * translation regime that isn't affected by its own stage-2 161 * translation, such as a non-VHE hypervisor running at vEL2, or 162 * for vEL1/EL0 with vHCR_EL2.VM == 0. In that case, we use the 163 * canonical stage-2 page tables. 164 */ 165 phys_addr_t pgd_phys; 166 struct kvm_pgtable *pgt; 167 168 /* 169 * VTCR value used on the host. For a non-NV guest (or a NV 170 * guest that runs in a context where its own S2 doesn't 171 * apply), its T0SZ value reflects that of the IPA size. 172 * 173 * For a shadow S2 MMU, T0SZ reflects the PARange exposed to 174 * the guest. 175 */ 176 u64 vtcr; 177 178 /* The last vcpu id that ran on each physical CPU */ 179 int __percpu *last_vcpu_ran; 180 181 #define KVM_ARM_EAGER_SPLIT_CHUNK_SIZE_DEFAULT 0 182 /* 183 * Memory cache used to split 184 * KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE worth of huge pages. It 185 * is used to allocate stage2 page tables while splitting huge 186 * pages. The choice of KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE 187 * influences both the capacity of the split page cache, and 188 * how often KVM reschedules. Be wary of raising CHUNK_SIZE 189 * too high. 190 * 191 * Protected by kvm->slots_lock. 192 */ 193 struct kvm_mmu_memory_cache split_page_cache; 194 uint64_t split_page_chunk_size; 195 196 struct kvm_arch *arch; 197 198 /* 199 * For a shadow stage-2 MMU, the virtual vttbr used by the 200 * host to parse the guest S2. 201 * This either contains: 202 * - the virtual VTTBR programmed by the guest hypervisor with 203 * CnP cleared 204 * - The value 1 (VMID=0, BADDR=0, CnP=1) if invalid 205 * 206 * We also cache the full VTCR which gets used for TLB invalidation, 207 * taking the ARM ARM's "Any of the bits in VTCR_EL2 are permitted 208 * to be cached in a TLB" to the letter. 209 */ 210 u64 tlb_vttbr; 211 u64 tlb_vtcr; 212 213 /* 214 * true when this represents a nested context where virtual 215 * HCR_EL2.VM == 1 216 */ 217 bool nested_stage2_enabled; 218 219 /* 220 * true when this MMU needs to be unmapped before being used for a new 221 * purpose. 222 */ 223 bool pending_unmap; 224 225 /* 226 * 0: Nobody is currently using this, check vttbr for validity 227 * >0: Somebody is actively using this. 228 */ 229 atomic_t refcnt; 230 }; 231 232 struct kvm_arch_memory_slot { 233 }; 234 235 /** 236 * struct kvm_smccc_features: Descriptor of the hypercall services exposed to the guests 237 * 238 * @std_bmap: Bitmap of standard secure service calls 239 * @std_hyp_bmap: Bitmap of standard hypervisor service calls 240 * @vendor_hyp_bmap: Bitmap of vendor specific hypervisor service calls 241 */ 242 struct kvm_smccc_features { 243 unsigned long std_bmap; 244 unsigned long std_hyp_bmap; 245 unsigned long vendor_hyp_bmap; /* Function numbers 0-63 */ 246 unsigned long vendor_hyp_bmap_2; /* Function numbers 64-127 */ 247 }; 248 249 typedef unsigned int pkvm_handle_t; 250 251 struct kvm_protected_vm { 252 pkvm_handle_t handle; 253 struct kvm_hyp_memcache teardown_mc; 254 struct kvm_hyp_memcache stage2_teardown_mc; 255 bool is_protected; 256 bool is_created; 257 }; 258 259 struct kvm_mpidr_data { 260 u64 mpidr_mask; 261 DECLARE_FLEX_ARRAY(u16, cmpidr_to_idx); 262 }; 263 264 static inline u16 kvm_mpidr_index(struct kvm_mpidr_data *data, u64 mpidr) 265 { 266 unsigned long index = 0, mask = data->mpidr_mask; 267 unsigned long aff = mpidr & MPIDR_HWID_BITMASK; 268 269 bitmap_gather(&index, &aff, &mask, fls(mask)); 270 271 return index; 272 } 273 274 struct kvm_sysreg_masks; 275 276 enum fgt_group_id { 277 __NO_FGT_GROUP__, 278 HFGRTR_GROUP, 279 HFGWTR_GROUP = HFGRTR_GROUP, 280 HDFGRTR_GROUP, 281 HDFGWTR_GROUP = HDFGRTR_GROUP, 282 HFGITR_GROUP, 283 HAFGRTR_GROUP, 284 HFGRTR2_GROUP, 285 HFGWTR2_GROUP = HFGRTR2_GROUP, 286 HDFGRTR2_GROUP, 287 HDFGWTR2_GROUP = HDFGRTR2_GROUP, 288 HFGITR2_GROUP, 289 290 /* Must be last */ 291 __NR_FGT_GROUP_IDS__ 292 }; 293 294 struct kvm_arch { 295 struct kvm_s2_mmu mmu; 296 297 /* 298 * Fine-Grained UNDEF, mimicking the FGT layout defined by the 299 * architecture. We track them globally, as we present the 300 * same feature-set to all vcpus. 301 * 302 * Index 0 is currently spare. 303 */ 304 u64 fgu[__NR_FGT_GROUP_IDS__]; 305 306 /* 307 * Stage 2 paging state for VMs with nested S2 using a virtual 308 * VMID. 309 */ 310 struct kvm_s2_mmu *nested_mmus; 311 size_t nested_mmus_size; 312 int nested_mmus_next; 313 314 /* Interrupt controller */ 315 struct vgic_dist vgic; 316 317 /* Timers */ 318 struct arch_timer_vm_data timer_data; 319 320 /* Mandated version of PSCI */ 321 u32 psci_version; 322 323 /* Protects VM-scoped configuration data */ 324 struct mutex config_lock; 325 326 /* 327 * If we encounter a data abort without valid instruction syndrome 328 * information, report this to user space. User space can (and 329 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is 330 * supported. 331 */ 332 #define KVM_ARCH_FLAG_RETURN_NISV_IO_ABORT_TO_USER 0 333 /* Memory Tagging Extension enabled for the guest */ 334 #define KVM_ARCH_FLAG_MTE_ENABLED 1 335 /* At least one vCPU has ran in the VM */ 336 #define KVM_ARCH_FLAG_HAS_RAN_ONCE 2 337 /* The vCPU feature set for the VM is configured */ 338 #define KVM_ARCH_FLAG_VCPU_FEATURES_CONFIGURED 3 339 /* PSCI SYSTEM_SUSPEND enabled for the guest */ 340 #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED 4 341 /* VM counter offset */ 342 #define KVM_ARCH_FLAG_VM_COUNTER_OFFSET 5 343 /* Timer PPIs made immutable */ 344 #define KVM_ARCH_FLAG_TIMER_PPIS_IMMUTABLE 6 345 /* Initial ID reg values loaded */ 346 #define KVM_ARCH_FLAG_ID_REGS_INITIALIZED 7 347 /* Fine-Grained UNDEF initialised */ 348 #define KVM_ARCH_FLAG_FGU_INITIALIZED 8 349 /* SVE exposed to guest */ 350 #define KVM_ARCH_FLAG_GUEST_HAS_SVE 9 351 /* MIDR_EL1, REVIDR_EL1, and AIDR_EL1 are writable from userspace */ 352 #define KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS 10 353 unsigned long flags; 354 355 /* VM-wide vCPU feature set */ 356 DECLARE_BITMAP(vcpu_features, KVM_VCPU_MAX_FEATURES); 357 358 /* MPIDR to vcpu index mapping, optional */ 359 struct kvm_mpidr_data *mpidr_data; 360 361 /* 362 * VM-wide PMU filter, implemented as a bitmap and big enough for 363 * up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+). 364 */ 365 unsigned long *pmu_filter; 366 struct arm_pmu *arm_pmu; 367 368 cpumask_var_t supported_cpus; 369 370 /* Maximum number of counters for the guest */ 371 u8 nr_pmu_counters; 372 373 /* Iterator for idreg debugfs */ 374 u8 idreg_debugfs_iter; 375 376 /* Hypercall features firmware registers' descriptor */ 377 struct kvm_smccc_features smccc_feat; 378 struct maple_tree smccc_filter; 379 380 /* 381 * Emulated CPU ID registers per VM 382 * (Op0, Op1, CRn, CRm, Op2) of the ID registers to be saved in it 383 * is (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8. 384 * 385 * These emulated idregs are VM-wide, but accessed from the context of a vCPU. 386 * Atomic access to multiple idregs are guarded by kvm_arch.config_lock. 387 */ 388 #define IDREG_IDX(id) (((sys_reg_CRm(id) - 1) << 3) | sys_reg_Op2(id)) 389 #define KVM_ARM_ID_REG_NUM (IDREG_IDX(sys_reg(3, 0, 0, 7, 7)) + 1) 390 u64 id_regs[KVM_ARM_ID_REG_NUM]; 391 392 u64 midr_el1; 393 u64 revidr_el1; 394 u64 aidr_el1; 395 u64 ctr_el0; 396 397 /* Masks for VNCR-backed and general EL2 sysregs */ 398 struct kvm_sysreg_masks *sysreg_masks; 399 400 /* Count the number of VNCR_EL2 currently mapped */ 401 atomic_t vncr_map_count; 402 403 /* 404 * For an untrusted host VM, 'pkvm.handle' is used to lookup 405 * the associated pKVM instance in the hypervisor. 406 */ 407 struct kvm_protected_vm pkvm; 408 }; 409 410 struct kvm_vcpu_fault_info { 411 u64 esr_el2; /* Hyp Syndrom Register */ 412 u64 far_el2; /* Hyp Fault Address Register */ 413 u64 hpfar_el2; /* Hyp IPA Fault Address Register */ 414 u64 disr_el1; /* Deferred [SError] Status Register */ 415 }; 416 417 /* 418 * VNCR() just places the VNCR_capable registers in the enum after 419 * __VNCR_START__, and the value (after correction) to be an 8-byte offset 420 * from the VNCR base. As we don't require the enum to be otherwise ordered, 421 * we need the terrible hack below to ensure that we correctly size the 422 * sys_regs array, no matter what. 423 * 424 * The __MAX__ macro has been lifted from Sean Eron Anderson's wonderful 425 * treasure trove of bit hacks: 426 * https://graphics.stanford.edu/~seander/bithacks.html#IntegerMinOrMax 427 */ 428 #define __MAX__(x,y) ((x) ^ (((x) ^ (y)) & -((x) < (y)))) 429 #define VNCR(r) \ 430 __before_##r, \ 431 r = __VNCR_START__ + ((VNCR_ ## r) / 8), \ 432 __after_##r = __MAX__(__before_##r - 1, r) 433 434 #define MARKER(m) \ 435 m, __after_##m = m - 1 436 437 enum vcpu_sysreg { 438 __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ 439 MPIDR_EL1, /* MultiProcessor Affinity Register */ 440 CLIDR_EL1, /* Cache Level ID Register */ 441 CSSELR_EL1, /* Cache Size Selection Register */ 442 TPIDR_EL0, /* Thread ID, User R/W */ 443 TPIDRRO_EL0, /* Thread ID, User R/O */ 444 TPIDR_EL1, /* Thread ID, Privileged */ 445 CNTKCTL_EL1, /* Timer Control Register (EL1) */ 446 PAR_EL1, /* Physical Address Register */ 447 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ 448 OSLSR_EL1, /* OS Lock Status Register */ 449 DISR_EL1, /* Deferred Interrupt Status Register */ 450 451 /* Performance Monitors Registers */ 452 PMCR_EL0, /* Control Register */ 453 PMSELR_EL0, /* Event Counter Selection Register */ 454 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */ 455 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30, 456 PMCCNTR_EL0, /* Cycle Counter Register */ 457 PMEVTYPER0_EL0, /* Event Type Register (0-30) */ 458 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30, 459 PMCCFILTR_EL0, /* Cycle Count Filter Register */ 460 PMCNTENSET_EL0, /* Count Enable Set Register */ 461 PMINTENSET_EL1, /* Interrupt Enable Set Register */ 462 PMOVSSET_EL0, /* Overflow Flag Status Set Register */ 463 PMUSERENR_EL0, /* User Enable Register */ 464 465 /* Pointer Authentication Registers in a strict increasing order. */ 466 APIAKEYLO_EL1, 467 APIAKEYHI_EL1, 468 APIBKEYLO_EL1, 469 APIBKEYHI_EL1, 470 APDAKEYLO_EL1, 471 APDAKEYHI_EL1, 472 APDBKEYLO_EL1, 473 APDBKEYHI_EL1, 474 APGAKEYLO_EL1, 475 APGAKEYHI_EL1, 476 477 /* Memory Tagging Extension registers */ 478 RGSR_EL1, /* Random Allocation Tag Seed Register */ 479 GCR_EL1, /* Tag Control Register */ 480 TFSRE0_EL1, /* Tag Fault Status Register (EL0) */ 481 482 POR_EL0, /* Permission Overlay Register 0 (EL0) */ 483 484 /* FP/SIMD/SVE */ 485 SVCR, 486 FPMR, 487 488 /* 32bit specific registers. */ 489 DACR32_EL2, /* Domain Access Control Register */ 490 IFSR32_EL2, /* Instruction Fault Status Register */ 491 FPEXC32_EL2, /* Floating-Point Exception Control Register */ 492 DBGVCR32_EL2, /* Debug Vector Catch Register */ 493 494 /* EL2 registers */ 495 SCTLR_EL2, /* System Control Register (EL2) */ 496 ACTLR_EL2, /* Auxiliary Control Register (EL2) */ 497 CPTR_EL2, /* Architectural Feature Trap Register (EL2) */ 498 HACR_EL2, /* Hypervisor Auxiliary Control Register */ 499 ZCR_EL2, /* SVE Control Register (EL2) */ 500 TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */ 501 TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */ 502 TCR_EL2, /* Translation Control Register (EL2) */ 503 PIRE0_EL2, /* Permission Indirection Register 0 (EL2) */ 504 PIR_EL2, /* Permission Indirection Register 1 (EL2) */ 505 POR_EL2, /* Permission Overlay Register 2 (EL2) */ 506 SPSR_EL2, /* EL2 saved program status register */ 507 ELR_EL2, /* EL2 exception link register */ 508 AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */ 509 AFSR1_EL2, /* Auxiliary Fault Status Register 1 (EL2) */ 510 ESR_EL2, /* Exception Syndrome Register (EL2) */ 511 FAR_EL2, /* Fault Address Register (EL2) */ 512 HPFAR_EL2, /* Hypervisor IPA Fault Address Register */ 513 MAIR_EL2, /* Memory Attribute Indirection Register (EL2) */ 514 AMAIR_EL2, /* Auxiliary Memory Attribute Indirection Register (EL2) */ 515 VBAR_EL2, /* Vector Base Address Register (EL2) */ 516 RVBAR_EL2, /* Reset Vector Base Address Register */ 517 CONTEXTIDR_EL2, /* Context ID Register (EL2) */ 518 SP_EL2, /* EL2 Stack Pointer */ 519 CNTHP_CTL_EL2, 520 CNTHP_CVAL_EL2, 521 CNTHV_CTL_EL2, 522 CNTHV_CVAL_EL2, 523 524 /* Anything from this can be RES0/RES1 sanitised */ 525 MARKER(__SANITISED_REG_START__), 526 TCR2_EL2, /* Extended Translation Control Register (EL2) */ 527 SCTLR2_EL2, /* System Control Register 2 (EL2) */ 528 MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */ 529 CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */ 530 531 /* Any VNCR-capable reg goes after this point */ 532 MARKER(__VNCR_START__), 533 534 VNCR(SCTLR_EL1),/* System Control Register */ 535 VNCR(ACTLR_EL1),/* Auxiliary Control Register */ 536 VNCR(CPACR_EL1),/* Coprocessor Access Control */ 537 VNCR(ZCR_EL1), /* SVE Control */ 538 VNCR(TTBR0_EL1),/* Translation Table Base Register 0 */ 539 VNCR(TTBR1_EL1),/* Translation Table Base Register 1 */ 540 VNCR(TCR_EL1), /* Translation Control Register */ 541 VNCR(TCR2_EL1), /* Extended Translation Control Register */ 542 VNCR(SCTLR2_EL1), /* System Control Register 2 */ 543 VNCR(ESR_EL1), /* Exception Syndrome Register */ 544 VNCR(AFSR0_EL1),/* Auxiliary Fault Status Register 0 */ 545 VNCR(AFSR1_EL1),/* Auxiliary Fault Status Register 1 */ 546 VNCR(FAR_EL1), /* Fault Address Register */ 547 VNCR(MAIR_EL1), /* Memory Attribute Indirection Register */ 548 VNCR(VBAR_EL1), /* Vector Base Address Register */ 549 VNCR(CONTEXTIDR_EL1), /* Context ID Register */ 550 VNCR(AMAIR_EL1),/* Aux Memory Attribute Indirection Register */ 551 VNCR(MDSCR_EL1),/* Monitor Debug System Control Register */ 552 VNCR(ELR_EL1), 553 VNCR(SP_EL1), 554 VNCR(SPSR_EL1), 555 VNCR(TFSR_EL1), /* Tag Fault Status Register (EL1) */ 556 VNCR(VPIDR_EL2),/* Virtualization Processor ID Register */ 557 VNCR(VMPIDR_EL2),/* Virtualization Multiprocessor ID Register */ 558 VNCR(HCR_EL2), /* Hypervisor Configuration Register */ 559 VNCR(HSTR_EL2), /* Hypervisor System Trap Register */ 560 VNCR(VTTBR_EL2),/* Virtualization Translation Table Base Register */ 561 VNCR(VTCR_EL2), /* Virtualization Translation Control Register */ 562 VNCR(TPIDR_EL2),/* EL2 Software Thread ID Register */ 563 VNCR(HCRX_EL2), /* Extended Hypervisor Configuration Register */ 564 565 /* Permission Indirection Extension registers */ 566 VNCR(PIR_EL1), /* Permission Indirection Register 1 (EL1) */ 567 VNCR(PIRE0_EL1), /* Permission Indirection Register 0 (EL1) */ 568 569 VNCR(POR_EL1), /* Permission Overlay Register 1 (EL1) */ 570 571 /* FEAT_RAS registers */ 572 VNCR(VDISR_EL2), 573 VNCR(VSESR_EL2), 574 575 VNCR(HFGRTR_EL2), 576 VNCR(HFGWTR_EL2), 577 VNCR(HFGITR_EL2), 578 VNCR(HDFGRTR_EL2), 579 VNCR(HDFGWTR_EL2), 580 VNCR(HAFGRTR_EL2), 581 VNCR(HFGRTR2_EL2), 582 VNCR(HFGWTR2_EL2), 583 VNCR(HFGITR2_EL2), 584 VNCR(HDFGRTR2_EL2), 585 VNCR(HDFGWTR2_EL2), 586 587 VNCR(VNCR_EL2), 588 589 VNCR(CNTVOFF_EL2), 590 VNCR(CNTV_CVAL_EL0), 591 VNCR(CNTV_CTL_EL0), 592 VNCR(CNTP_CVAL_EL0), 593 VNCR(CNTP_CTL_EL0), 594 595 VNCR(ICH_LR0_EL2), 596 VNCR(ICH_LR1_EL2), 597 VNCR(ICH_LR2_EL2), 598 VNCR(ICH_LR3_EL2), 599 VNCR(ICH_LR4_EL2), 600 VNCR(ICH_LR5_EL2), 601 VNCR(ICH_LR6_EL2), 602 VNCR(ICH_LR7_EL2), 603 VNCR(ICH_LR8_EL2), 604 VNCR(ICH_LR9_EL2), 605 VNCR(ICH_LR10_EL2), 606 VNCR(ICH_LR11_EL2), 607 VNCR(ICH_LR12_EL2), 608 VNCR(ICH_LR13_EL2), 609 VNCR(ICH_LR14_EL2), 610 VNCR(ICH_LR15_EL2), 611 612 VNCR(ICH_AP0R0_EL2), 613 VNCR(ICH_AP0R1_EL2), 614 VNCR(ICH_AP0R2_EL2), 615 VNCR(ICH_AP0R3_EL2), 616 VNCR(ICH_AP1R0_EL2), 617 VNCR(ICH_AP1R1_EL2), 618 VNCR(ICH_AP1R2_EL2), 619 VNCR(ICH_AP1R3_EL2), 620 VNCR(ICH_HCR_EL2), 621 VNCR(ICH_VMCR_EL2), 622 623 NR_SYS_REGS /* Nothing after this line! */ 624 }; 625 626 struct kvm_sysreg_masks { 627 struct { 628 u64 res0; 629 u64 res1; 630 } mask[NR_SYS_REGS - __SANITISED_REG_START__]; 631 }; 632 633 struct fgt_masks { 634 const char *str; 635 u64 mask; 636 u64 nmask; 637 u64 res0; 638 }; 639 640 extern struct fgt_masks hfgrtr_masks; 641 extern struct fgt_masks hfgwtr_masks; 642 extern struct fgt_masks hfgitr_masks; 643 extern struct fgt_masks hdfgrtr_masks; 644 extern struct fgt_masks hdfgwtr_masks; 645 extern struct fgt_masks hafgrtr_masks; 646 extern struct fgt_masks hfgrtr2_masks; 647 extern struct fgt_masks hfgwtr2_masks; 648 extern struct fgt_masks hfgitr2_masks; 649 extern struct fgt_masks hdfgrtr2_masks; 650 extern struct fgt_masks hdfgwtr2_masks; 651 652 extern struct fgt_masks kvm_nvhe_sym(hfgrtr_masks); 653 extern struct fgt_masks kvm_nvhe_sym(hfgwtr_masks); 654 extern struct fgt_masks kvm_nvhe_sym(hfgitr_masks); 655 extern struct fgt_masks kvm_nvhe_sym(hdfgrtr_masks); 656 extern struct fgt_masks kvm_nvhe_sym(hdfgwtr_masks); 657 extern struct fgt_masks kvm_nvhe_sym(hafgrtr_masks); 658 extern struct fgt_masks kvm_nvhe_sym(hfgrtr2_masks); 659 extern struct fgt_masks kvm_nvhe_sym(hfgwtr2_masks); 660 extern struct fgt_masks kvm_nvhe_sym(hfgitr2_masks); 661 extern struct fgt_masks kvm_nvhe_sym(hdfgrtr2_masks); 662 extern struct fgt_masks kvm_nvhe_sym(hdfgwtr2_masks); 663 664 struct kvm_cpu_context { 665 struct user_pt_regs regs; /* sp = sp_el0 */ 666 667 u64 spsr_abt; 668 u64 spsr_und; 669 u64 spsr_irq; 670 u64 spsr_fiq; 671 672 struct user_fpsimd_state fp_regs; 673 674 u64 sys_regs[NR_SYS_REGS]; 675 676 struct kvm_vcpu *__hyp_running_vcpu; 677 678 /* This pointer has to be 4kB aligned. */ 679 u64 *vncr_array; 680 }; 681 682 struct cpu_sve_state { 683 __u64 zcr_el1; 684 685 /* 686 * Ordering is important since __sve_save_state/__sve_restore_state 687 * relies on it. 688 */ 689 __u32 fpsr; 690 __u32 fpcr; 691 692 /* Must be SVE_VQ_BYTES (128 bit) aligned. */ 693 __u8 sve_regs[]; 694 }; 695 696 /* 697 * This structure is instantiated on a per-CPU basis, and contains 698 * data that is: 699 * 700 * - tied to a single physical CPU, and 701 * - either have a lifetime that does not extend past vcpu_put() 702 * - or is an invariant for the lifetime of the system 703 * 704 * Use host_data_ptr(field) as a way to access a pointer to such a 705 * field. 706 */ 707 struct kvm_host_data { 708 #define KVM_HOST_DATA_FLAG_HAS_SPE 0 709 #define KVM_HOST_DATA_FLAG_HAS_TRBE 1 710 #define KVM_HOST_DATA_FLAG_TRBE_ENABLED 4 711 #define KVM_HOST_DATA_FLAG_EL1_TRACING_CONFIGURED 5 712 #define KVM_HOST_DATA_FLAG_VCPU_IN_HYP_CONTEXT 6 713 #define KVM_HOST_DATA_FLAG_L1_VNCR_MAPPED 7 714 #define KVM_HOST_DATA_FLAG_HAS_BRBE 8 715 unsigned long flags; 716 717 struct kvm_cpu_context host_ctxt; 718 719 /* 720 * Hyp VA. 721 * sve_state is only used in pKVM and if system_supports_sve(). 722 */ 723 struct cpu_sve_state *sve_state; 724 725 /* Used by pKVM only. */ 726 u64 fpmr; 727 728 /* Ownership of the FP regs */ 729 enum { 730 FP_STATE_FREE, 731 FP_STATE_HOST_OWNED, 732 FP_STATE_GUEST_OWNED, 733 } fp_owner; 734 735 /* 736 * host_debug_state contains the host registers which are 737 * saved and restored during world switches. 738 */ 739 struct { 740 /* {Break,watch}point registers */ 741 struct kvm_guest_debug_arch regs; 742 /* Statistical profiling extension */ 743 u64 pmscr_el1; 744 /* Self-hosted trace */ 745 u64 trfcr_el1; 746 /* Values of trap registers for the host before guest entry. */ 747 u64 mdcr_el2; 748 u64 brbcr_el1; 749 } host_debug_state; 750 751 /* Guest trace filter value */ 752 u64 trfcr_while_in_guest; 753 754 /* Number of programmable event counters (PMCR_EL0.N) for this CPU */ 755 unsigned int nr_event_counters; 756 757 /* Number of debug breakpoints/watchpoints for this CPU (minus 1) */ 758 unsigned int debug_brps; 759 unsigned int debug_wrps; 760 }; 761 762 struct kvm_host_psci_config { 763 /* PSCI version used by host. */ 764 u32 version; 765 u32 smccc_version; 766 767 /* Function IDs used by host if version is v0.1. */ 768 struct psci_0_1_function_ids function_ids_0_1; 769 770 bool psci_0_1_cpu_suspend_implemented; 771 bool psci_0_1_cpu_on_implemented; 772 bool psci_0_1_cpu_off_implemented; 773 bool psci_0_1_migrate_implemented; 774 }; 775 776 extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config); 777 #define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config) 778 779 extern s64 kvm_nvhe_sym(hyp_physvirt_offset); 780 #define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset) 781 782 extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS]; 783 #define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map) 784 785 struct vcpu_reset_state { 786 unsigned long pc; 787 unsigned long r0; 788 bool be; 789 bool reset; 790 }; 791 792 struct vncr_tlb; 793 794 struct kvm_vcpu_arch { 795 struct kvm_cpu_context ctxt; 796 797 /* 798 * Guest floating point state 799 * 800 * The architecture has two main floating point extensions, 801 * the original FPSIMD and SVE. These have overlapping 802 * register views, with the FPSIMD V registers occupying the 803 * low 128 bits of the SVE Z registers. When the core 804 * floating point code saves the register state of a task it 805 * records which view it saved in fp_type. 806 */ 807 void *sve_state; 808 enum fp_type fp_type; 809 unsigned int sve_max_vl; 810 811 /* Stage 2 paging state used by the hardware on next switch */ 812 struct kvm_s2_mmu *hw_mmu; 813 814 /* Values of trap registers for the guest. */ 815 u64 hcr_el2; 816 u64 hcrx_el2; 817 u64 mdcr_el2; 818 819 struct { 820 u64 r; 821 u64 w; 822 } fgt[__NR_FGT_GROUP_IDS__]; 823 824 /* Exception Information */ 825 struct kvm_vcpu_fault_info fault; 826 827 /* Configuration flags, set once and for all before the vcpu can run */ 828 u8 cflags; 829 830 /* Input flags to the hypervisor code, potentially cleared after use */ 831 u8 iflags; 832 833 /* State flags for kernel bookkeeping, unused by the hypervisor code */ 834 u16 sflags; 835 836 /* 837 * Don't run the guest (internal implementation need). 838 * 839 * Contrary to the flags above, this is set/cleared outside of 840 * a vcpu context, and thus cannot be mixed with the flags 841 * themselves (or the flag accesses need to be made atomic). 842 */ 843 bool pause; 844 845 /* 846 * We maintain more than a single set of debug registers to support 847 * debugging the guest from the host and to maintain separate host and 848 * guest state during world switches. vcpu_debug_state are the debug 849 * registers of the vcpu as the guest sees them. 850 * 851 * external_debug_state contains the debug values we want to debug the 852 * guest. This is set via the KVM_SET_GUEST_DEBUG ioctl. 853 */ 854 struct kvm_guest_debug_arch vcpu_debug_state; 855 struct kvm_guest_debug_arch external_debug_state; 856 u64 external_mdscr_el1; 857 858 enum { 859 VCPU_DEBUG_FREE, 860 VCPU_DEBUG_HOST_OWNED, 861 VCPU_DEBUG_GUEST_OWNED, 862 } debug_owner; 863 864 /* VGIC state */ 865 struct vgic_cpu vgic_cpu; 866 struct arch_timer_cpu timer_cpu; 867 struct kvm_pmu pmu; 868 869 /* vcpu power state */ 870 struct kvm_mp_state mp_state; 871 spinlock_t mp_state_lock; 872 873 /* Cache some mmu pages needed inside spinlock regions */ 874 struct kvm_mmu_memory_cache mmu_page_cache; 875 876 /* Pages to top-up the pKVM/EL2 guest pool */ 877 struct kvm_hyp_memcache pkvm_memcache; 878 879 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */ 880 u64 vsesr_el2; 881 882 /* Additional reset state */ 883 struct vcpu_reset_state reset_state; 884 885 /* Guest PV state */ 886 struct { 887 u64 last_steal; 888 gpa_t base; 889 } steal; 890 891 /* Per-vcpu CCSIDR override or NULL */ 892 u32 *ccsidr; 893 894 /* Per-vcpu TLB for VNCR_EL2 -- NULL when !NV */ 895 struct vncr_tlb *vncr_tlb; 896 }; 897 898 /* 899 * Each 'flag' is composed of a comma-separated triplet: 900 * 901 * - the flag-set it belongs to in the vcpu->arch structure 902 * - the value for that flag 903 * - the mask for that flag 904 * 905 * __vcpu_single_flag() builds such a triplet for a single-bit flag. 906 * unpack_vcpu_flag() extract the flag value from the triplet for 907 * direct use outside of the flag accessors. 908 */ 909 #define __vcpu_single_flag(_set, _f) _set, (_f), (_f) 910 911 #define __unpack_flag(_set, _f, _m) _f 912 #define unpack_vcpu_flag(...) __unpack_flag(__VA_ARGS__) 913 914 #define __build_check_flag(v, flagset, f, m) \ 915 do { \ 916 typeof(v->arch.flagset) *_fset; \ 917 \ 918 /* Check that the flags fit in the mask */ \ 919 BUILD_BUG_ON(HWEIGHT(m) != HWEIGHT((f) | (m))); \ 920 /* Check that the flags fit in the type */ \ 921 BUILD_BUG_ON((sizeof(*_fset) * 8) <= __fls(m)); \ 922 } while (0) 923 924 #define __vcpu_get_flag(v, flagset, f, m) \ 925 ({ \ 926 __build_check_flag(v, flagset, f, m); \ 927 \ 928 READ_ONCE(v->arch.flagset) & (m); \ 929 }) 930 931 /* 932 * Note that the set/clear accessors must be preempt-safe in order to 933 * avoid nesting them with load/put which also manipulate flags... 934 */ 935 #ifdef __KVM_NVHE_HYPERVISOR__ 936 /* the nVHE hypervisor is always non-preemptible */ 937 #define __vcpu_flags_preempt_disable() 938 #define __vcpu_flags_preempt_enable() 939 #else 940 #define __vcpu_flags_preempt_disable() preempt_disable() 941 #define __vcpu_flags_preempt_enable() preempt_enable() 942 #endif 943 944 #define __vcpu_set_flag(v, flagset, f, m) \ 945 do { \ 946 typeof(v->arch.flagset) *fset; \ 947 \ 948 __build_check_flag(v, flagset, f, m); \ 949 \ 950 fset = &v->arch.flagset; \ 951 __vcpu_flags_preempt_disable(); \ 952 if (HWEIGHT(m) > 1) \ 953 *fset &= ~(m); \ 954 *fset |= (f); \ 955 __vcpu_flags_preempt_enable(); \ 956 } while (0) 957 958 #define __vcpu_clear_flag(v, flagset, f, m) \ 959 do { \ 960 typeof(v->arch.flagset) *fset; \ 961 \ 962 __build_check_flag(v, flagset, f, m); \ 963 \ 964 fset = &v->arch.flagset; \ 965 __vcpu_flags_preempt_disable(); \ 966 *fset &= ~(m); \ 967 __vcpu_flags_preempt_enable(); \ 968 } while (0) 969 970 #define __vcpu_test_and_clear_flag(v, flagset, f, m) \ 971 ({ \ 972 typeof(v->arch.flagset) set; \ 973 \ 974 set = __vcpu_get_flag(v, flagset, f, m); \ 975 __vcpu_clear_flag(v, flagset, f, m); \ 976 \ 977 set; \ 978 }) 979 980 #define vcpu_get_flag(v, ...) __vcpu_get_flag((v), __VA_ARGS__) 981 #define vcpu_set_flag(v, ...) __vcpu_set_flag((v), __VA_ARGS__) 982 #define vcpu_clear_flag(v, ...) __vcpu_clear_flag((v), __VA_ARGS__) 983 #define vcpu_test_and_clear_flag(v, ...) \ 984 __vcpu_test_and_clear_flag((v), __VA_ARGS__) 985 986 /* KVM_ARM_VCPU_INIT completed */ 987 #define VCPU_INITIALIZED __vcpu_single_flag(cflags, BIT(0)) 988 /* SVE config completed */ 989 #define VCPU_SVE_FINALIZED __vcpu_single_flag(cflags, BIT(1)) 990 /* pKVM VCPU setup completed */ 991 #define VCPU_PKVM_FINALIZED __vcpu_single_flag(cflags, BIT(2)) 992 993 /* Exception pending */ 994 #define PENDING_EXCEPTION __vcpu_single_flag(iflags, BIT(0)) 995 /* 996 * PC increment. Overlaps with EXCEPT_MASK on purpose so that it can't 997 * be set together with an exception... 998 */ 999 #define INCREMENT_PC __vcpu_single_flag(iflags, BIT(1)) 1000 /* Target EL/MODE (not a single flag, but let's abuse the macro) */ 1001 #define EXCEPT_MASK __vcpu_single_flag(iflags, GENMASK(3, 1)) 1002 1003 /* Helpers to encode exceptions with minimum fuss */ 1004 #define __EXCEPT_MASK_VAL unpack_vcpu_flag(EXCEPT_MASK) 1005 #define __EXCEPT_SHIFT __builtin_ctzl(__EXCEPT_MASK_VAL) 1006 #define __vcpu_except_flags(_f) iflags, (_f << __EXCEPT_SHIFT), __EXCEPT_MASK_VAL 1007 1008 /* 1009 * When PENDING_EXCEPTION is set, EXCEPT_MASK can take the following 1010 * values: 1011 * 1012 * For AArch32 EL1: 1013 */ 1014 #define EXCEPT_AA32_UND __vcpu_except_flags(0) 1015 #define EXCEPT_AA32_IABT __vcpu_except_flags(1) 1016 #define EXCEPT_AA32_DABT __vcpu_except_flags(2) 1017 /* For AArch64: */ 1018 #define EXCEPT_AA64_EL1_SYNC __vcpu_except_flags(0) 1019 #define EXCEPT_AA64_EL1_IRQ __vcpu_except_flags(1) 1020 #define EXCEPT_AA64_EL1_FIQ __vcpu_except_flags(2) 1021 #define EXCEPT_AA64_EL1_SERR __vcpu_except_flags(3) 1022 /* For AArch64 with NV: */ 1023 #define EXCEPT_AA64_EL2_SYNC __vcpu_except_flags(4) 1024 #define EXCEPT_AA64_EL2_IRQ __vcpu_except_flags(5) 1025 #define EXCEPT_AA64_EL2_FIQ __vcpu_except_flags(6) 1026 #define EXCEPT_AA64_EL2_SERR __vcpu_except_flags(7) 1027 1028 /* Physical CPU not in supported_cpus */ 1029 #define ON_UNSUPPORTED_CPU __vcpu_single_flag(sflags, BIT(0)) 1030 /* WFIT instruction trapped */ 1031 #define IN_WFIT __vcpu_single_flag(sflags, BIT(1)) 1032 /* vcpu system registers loaded on physical CPU */ 1033 #define SYSREGS_ON_CPU __vcpu_single_flag(sflags, BIT(2)) 1034 /* Software step state is Active-pending for external debug */ 1035 #define HOST_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(3)) 1036 /* Software step state is Active pending for guest debug */ 1037 #define GUEST_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(4)) 1038 /* PMUSERENR for the guest EL0 is on physical CPU */ 1039 #define PMUSERENR_ON_CPU __vcpu_single_flag(sflags, BIT(5)) 1040 /* WFI instruction trapped */ 1041 #define IN_WFI __vcpu_single_flag(sflags, BIT(6)) 1042 /* KVM is currently emulating a nested ERET */ 1043 #define IN_NESTED_ERET __vcpu_single_flag(sflags, BIT(7)) 1044 /* SError pending for nested guest */ 1045 #define NESTED_SERROR_PENDING __vcpu_single_flag(sflags, BIT(8)) 1046 1047 1048 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */ 1049 #define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) + \ 1050 sve_ffr_offset((vcpu)->arch.sve_max_vl)) 1051 1052 #define vcpu_sve_max_vq(vcpu) sve_vq_from_vl((vcpu)->arch.sve_max_vl) 1053 1054 #define vcpu_sve_zcr_elx(vcpu) \ 1055 (unlikely(is_hyp_ctxt(vcpu)) ? ZCR_EL2 : ZCR_EL1) 1056 1057 #define sve_state_size_from_vl(sve_max_vl) ({ \ 1058 size_t __size_ret; \ 1059 unsigned int __vq; \ 1060 \ 1061 if (WARN_ON(!sve_vl_valid(sve_max_vl))) { \ 1062 __size_ret = 0; \ 1063 } else { \ 1064 __vq = sve_vq_from_vl(sve_max_vl); \ 1065 __size_ret = SVE_SIG_REGS_SIZE(__vq); \ 1066 } \ 1067 \ 1068 __size_ret; \ 1069 }) 1070 1071 #define vcpu_sve_state_size(vcpu) sve_state_size_from_vl((vcpu)->arch.sve_max_vl) 1072 1073 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \ 1074 KVM_GUESTDBG_USE_SW_BP | \ 1075 KVM_GUESTDBG_USE_HW | \ 1076 KVM_GUESTDBG_SINGLESTEP) 1077 1078 #define kvm_has_sve(kvm) (system_supports_sve() && \ 1079 test_bit(KVM_ARCH_FLAG_GUEST_HAS_SVE, &(kvm)->arch.flags)) 1080 1081 #ifdef __KVM_NVHE_HYPERVISOR__ 1082 #define vcpu_has_sve(vcpu) kvm_has_sve(kern_hyp_va((vcpu)->kvm)) 1083 #else 1084 #define vcpu_has_sve(vcpu) kvm_has_sve((vcpu)->kvm) 1085 #endif 1086 1087 #ifdef CONFIG_ARM64_PTR_AUTH 1088 #define vcpu_has_ptrauth(vcpu) \ 1089 ((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) || \ 1090 cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) && \ 1091 (vcpu_has_feature(vcpu, KVM_ARM_VCPU_PTRAUTH_ADDRESS) || \ 1092 vcpu_has_feature(vcpu, KVM_ARM_VCPU_PTRAUTH_GENERIC))) 1093 #else 1094 #define vcpu_has_ptrauth(vcpu) false 1095 #endif 1096 1097 #define vcpu_on_unsupported_cpu(vcpu) \ 1098 vcpu_get_flag(vcpu, ON_UNSUPPORTED_CPU) 1099 1100 #define vcpu_set_on_unsupported_cpu(vcpu) \ 1101 vcpu_set_flag(vcpu, ON_UNSUPPORTED_CPU) 1102 1103 #define vcpu_clear_on_unsupported_cpu(vcpu) \ 1104 vcpu_clear_flag(vcpu, ON_UNSUPPORTED_CPU) 1105 1106 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.regs) 1107 1108 /* 1109 * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the 1110 * memory backed version of a register, and not the one most recently 1111 * accessed by a running VCPU. For example, for userspace access or 1112 * for system registers that are never context switched, but only 1113 * emulated. 1114 * 1115 * Don't bother with VNCR-based accesses in the nVHE code, it has no 1116 * business dealing with NV. 1117 */ 1118 static inline u64 *___ctxt_sys_reg(const struct kvm_cpu_context *ctxt, int r) 1119 { 1120 #if !defined (__KVM_NVHE_HYPERVISOR__) 1121 if (unlikely(cpus_have_final_cap(ARM64_HAS_NESTED_VIRT) && 1122 r >= __VNCR_START__ && ctxt->vncr_array)) 1123 return &ctxt->vncr_array[r - __VNCR_START__]; 1124 #endif 1125 return (u64 *)&ctxt->sys_regs[r]; 1126 } 1127 1128 #define __ctxt_sys_reg(c,r) \ 1129 ({ \ 1130 BUILD_BUG_ON(__builtin_constant_p(r) && \ 1131 (r) >= NR_SYS_REGS); \ 1132 ___ctxt_sys_reg(c, r); \ 1133 }) 1134 1135 #define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r)) 1136 1137 u64 kvm_vcpu_apply_reg_masks(const struct kvm_vcpu *, enum vcpu_sysreg, u64); 1138 1139 #define __vcpu_assign_sys_reg(v, r, val) \ 1140 do { \ 1141 const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \ 1142 u64 __v = (val); \ 1143 if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \ 1144 __v = kvm_vcpu_apply_reg_masks((v), (r), __v); \ 1145 \ 1146 ctxt_sys_reg(ctxt, (r)) = __v; \ 1147 } while (0) 1148 1149 #define __vcpu_rmw_sys_reg(v, r, op, val) \ 1150 do { \ 1151 const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \ 1152 u64 __v = ctxt_sys_reg(ctxt, (r)); \ 1153 __v op (val); \ 1154 if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \ 1155 __v = kvm_vcpu_apply_reg_masks((v), (r), __v); \ 1156 \ 1157 ctxt_sys_reg(ctxt, (r)) = __v; \ 1158 } while (0) 1159 1160 #define __vcpu_sys_reg(v,r) \ 1161 ({ \ 1162 const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \ 1163 u64 __v = ctxt_sys_reg(ctxt, (r)); \ 1164 if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \ 1165 __v = kvm_vcpu_apply_reg_masks((v), (r), __v); \ 1166 __v; \ 1167 }) 1168 1169 u64 vcpu_read_sys_reg(const struct kvm_vcpu *, enum vcpu_sysreg); 1170 void vcpu_write_sys_reg(struct kvm_vcpu *, u64, enum vcpu_sysreg); 1171 1172 struct kvm_vm_stat { 1173 struct kvm_vm_stat_generic generic; 1174 }; 1175 1176 struct kvm_vcpu_stat { 1177 struct kvm_vcpu_stat_generic generic; 1178 u64 hvc_exit_stat; 1179 u64 wfe_exit_stat; 1180 u64 wfi_exit_stat; 1181 u64 mmio_exit_user; 1182 u64 mmio_exit_kernel; 1183 u64 signal_exits; 1184 u64 exits; 1185 }; 1186 1187 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); 1188 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); 1189 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 1190 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 1191 1192 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu); 1193 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices); 1194 1195 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu, 1196 struct kvm_vcpu_events *events); 1197 1198 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu, 1199 struct kvm_vcpu_events *events); 1200 1201 void kvm_arm_halt_guest(struct kvm *kvm); 1202 void kvm_arm_resume_guest(struct kvm *kvm); 1203 1204 #define vcpu_has_run_once(vcpu) (!!READ_ONCE((vcpu)->pid)) 1205 1206 #ifndef __KVM_NVHE_HYPERVISOR__ 1207 #define kvm_call_hyp_nvhe(f, ...) \ 1208 ({ \ 1209 struct arm_smccc_res res; \ 1210 \ 1211 arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f), \ 1212 ##__VA_ARGS__, &res); \ 1213 WARN_ON(res.a0 != SMCCC_RET_SUCCESS); \ 1214 \ 1215 res.a1; \ 1216 }) 1217 1218 /* 1219 * The isb() below is there to guarantee the same behaviour on VHE as on !VHE, 1220 * where the eret to EL1 acts as a context synchronization event. 1221 */ 1222 #define kvm_call_hyp(f, ...) \ 1223 do { \ 1224 if (has_vhe()) { \ 1225 f(__VA_ARGS__); \ 1226 isb(); \ 1227 } else { \ 1228 kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 1229 } \ 1230 } while(0) 1231 1232 #define kvm_call_hyp_ret(f, ...) \ 1233 ({ \ 1234 typeof(f(__VA_ARGS__)) ret; \ 1235 \ 1236 if (has_vhe()) { \ 1237 ret = f(__VA_ARGS__); \ 1238 } else { \ 1239 ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 1240 } \ 1241 \ 1242 ret; \ 1243 }) 1244 #else /* __KVM_NVHE_HYPERVISOR__ */ 1245 #define kvm_call_hyp(f, ...) f(__VA_ARGS__) 1246 #define kvm_call_hyp_ret(f, ...) f(__VA_ARGS__) 1247 #define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__) 1248 #endif /* __KVM_NVHE_HYPERVISOR__ */ 1249 1250 int handle_exit(struct kvm_vcpu *vcpu, int exception_index); 1251 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index); 1252 1253 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu); 1254 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu); 1255 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu); 1256 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu); 1257 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu); 1258 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu); 1259 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu); 1260 1261 void kvm_sys_regs_create_debugfs(struct kvm *kvm); 1262 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu); 1263 1264 int __init kvm_sys_reg_table_init(void); 1265 struct sys_reg_desc; 1266 int __init populate_sysreg_config(const struct sys_reg_desc *sr, 1267 unsigned int idx); 1268 int __init populate_nv_trap_config(void); 1269 1270 void kvm_calculate_traps(struct kvm_vcpu *vcpu); 1271 1272 /* MMIO helpers */ 1273 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data); 1274 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len); 1275 1276 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu); 1277 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa); 1278 1279 /* 1280 * Returns true if a Performance Monitoring Interrupt (PMI), a.k.a. perf event, 1281 * arrived in guest context. For arm64, any event that arrives while a vCPU is 1282 * loaded is considered to be "in guest". 1283 */ 1284 static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu) 1285 { 1286 return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu; 1287 } 1288 1289 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu); 1290 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu); 1291 void kvm_update_stolen_time(struct kvm_vcpu *vcpu); 1292 1293 bool kvm_arm_pvtime_supported(void); 1294 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu, 1295 struct kvm_device_attr *attr); 1296 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu, 1297 struct kvm_device_attr *attr); 1298 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu, 1299 struct kvm_device_attr *attr); 1300 1301 extern unsigned int __ro_after_init kvm_arm_vmid_bits; 1302 int __init kvm_arm_vmid_alloc_init(void); 1303 void __init kvm_arm_vmid_alloc_free(void); 1304 void kvm_arm_vmid_update(struct kvm_vmid *kvm_vmid); 1305 void kvm_arm_vmid_clear_active(void); 1306 1307 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch) 1308 { 1309 vcpu_arch->steal.base = INVALID_GPA; 1310 } 1311 1312 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch) 1313 { 1314 return (vcpu_arch->steal.base != INVALID_GPA); 1315 } 1316 1317 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); 1318 1319 DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data); 1320 1321 /* 1322 * How we access per-CPU host data depends on the where we access it from, 1323 * and the mode we're in: 1324 * 1325 * - VHE and nVHE hypervisor bits use their locally defined instance 1326 * 1327 * - the rest of the kernel use either the VHE or nVHE one, depending on 1328 * the mode we're running in. 1329 * 1330 * Unless we're in protected mode, fully deprivileged, and the nVHE 1331 * per-CPU stuff is exclusively accessible to the protected EL2 code. 1332 * In this case, the EL1 code uses the *VHE* data as its private state 1333 * (which makes sense in a way as there shouldn't be any shared state 1334 * between the host and the hypervisor). 1335 * 1336 * Yes, this is all totally trivial. Shoot me now. 1337 */ 1338 #if defined(__KVM_NVHE_HYPERVISOR__) || defined(__KVM_VHE_HYPERVISOR__) 1339 #define host_data_ptr(f) (&this_cpu_ptr(&kvm_host_data)->f) 1340 #else 1341 #define host_data_ptr(f) \ 1342 (static_branch_unlikely(&kvm_protected_mode_initialized) ? \ 1343 &this_cpu_ptr(&kvm_host_data)->f : \ 1344 &this_cpu_ptr_hyp_sym(kvm_host_data)->f) 1345 #endif 1346 1347 #define host_data_test_flag(flag) \ 1348 (test_bit(KVM_HOST_DATA_FLAG_##flag, host_data_ptr(flags))) 1349 #define host_data_set_flag(flag) \ 1350 set_bit(KVM_HOST_DATA_FLAG_##flag, host_data_ptr(flags)) 1351 #define host_data_clear_flag(flag) \ 1352 clear_bit(KVM_HOST_DATA_FLAG_##flag, host_data_ptr(flags)) 1353 1354 /* Check whether the FP regs are owned by the guest */ 1355 static inline bool guest_owns_fp_regs(void) 1356 { 1357 return *host_data_ptr(fp_owner) == FP_STATE_GUEST_OWNED; 1358 } 1359 1360 /* Check whether the FP regs are owned by the host */ 1361 static inline bool host_owns_fp_regs(void) 1362 { 1363 return *host_data_ptr(fp_owner) == FP_STATE_HOST_OWNED; 1364 } 1365 1366 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt) 1367 { 1368 /* The host's MPIDR is immutable, so let's set it up at boot time */ 1369 ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr(); 1370 } 1371 1372 static inline bool kvm_system_needs_idmapped_vectors(void) 1373 { 1374 return cpus_have_final_cap(ARM64_SPECTRE_V3A); 1375 } 1376 1377 void kvm_init_host_debug_data(void); 1378 void kvm_debug_init_vhe(void); 1379 void kvm_vcpu_load_debug(struct kvm_vcpu *vcpu); 1380 void kvm_vcpu_put_debug(struct kvm_vcpu *vcpu); 1381 void kvm_debug_set_guest_ownership(struct kvm_vcpu *vcpu); 1382 void kvm_debug_handle_oslar(struct kvm_vcpu *vcpu, u64 val); 1383 1384 #define kvm_vcpu_os_lock_enabled(vcpu) \ 1385 (!!(__vcpu_sys_reg(vcpu, OSLSR_EL1) & OSLSR_EL1_OSLK)) 1386 1387 #define kvm_debug_regs_in_use(vcpu) \ 1388 ((vcpu)->arch.debug_owner != VCPU_DEBUG_FREE) 1389 #define kvm_host_owns_debug_regs(vcpu) \ 1390 ((vcpu)->arch.debug_owner == VCPU_DEBUG_HOST_OWNED) 1391 #define kvm_guest_owns_debug_regs(vcpu) \ 1392 ((vcpu)->arch.debug_owner == VCPU_DEBUG_GUEST_OWNED) 1393 1394 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, 1395 struct kvm_device_attr *attr); 1396 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, 1397 struct kvm_device_attr *attr); 1398 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, 1399 struct kvm_device_attr *attr); 1400 1401 int kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm, 1402 struct kvm_arm_copy_mte_tags *copy_tags); 1403 int kvm_vm_ioctl_set_counter_offset(struct kvm *kvm, 1404 struct kvm_arm_counter_offset *offset); 1405 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, 1406 struct reg_mask_range *range); 1407 1408 /* Guest/host FPSIMD coordination helpers */ 1409 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu); 1410 void kvm_arch_vcpu_ctxflush_fp(struct kvm_vcpu *vcpu); 1411 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu); 1412 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu); 1413 1414 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr) 1415 { 1416 return (!has_vhe() && attr->exclude_host); 1417 } 1418 1419 #ifdef CONFIG_KVM 1420 void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr); 1421 void kvm_clr_pmu_events(u64 clr); 1422 bool kvm_set_pmuserenr(u64 val); 1423 void kvm_enable_trbe(void); 1424 void kvm_disable_trbe(void); 1425 void kvm_tracing_set_el1_configuration(u64 trfcr_while_in_guest); 1426 #else 1427 static inline void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr) {} 1428 static inline void kvm_clr_pmu_events(u64 clr) {} 1429 static inline bool kvm_set_pmuserenr(u64 val) 1430 { 1431 return false; 1432 } 1433 static inline void kvm_enable_trbe(void) {} 1434 static inline void kvm_disable_trbe(void) {} 1435 static inline void kvm_tracing_set_el1_configuration(u64 trfcr_while_in_guest) {} 1436 #endif 1437 1438 void kvm_vcpu_load_vhe(struct kvm_vcpu *vcpu); 1439 void kvm_vcpu_put_vhe(struct kvm_vcpu *vcpu); 1440 1441 int __init kvm_set_ipa_limit(void); 1442 u32 kvm_get_pa_bits(struct kvm *kvm); 1443 1444 #define __KVM_HAVE_ARCH_VM_ALLOC 1445 struct kvm *kvm_arch_alloc_vm(void); 1446 1447 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS 1448 1449 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS_RANGE 1450 1451 #define kvm_vm_is_protected(kvm) (is_protected_kvm_enabled() && (kvm)->arch.pkvm.is_protected) 1452 1453 #define vcpu_is_protected(vcpu) kvm_vm_is_protected((vcpu)->kvm) 1454 1455 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature); 1456 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu); 1457 1458 #define kvm_arm_vcpu_sve_finalized(vcpu) vcpu_get_flag(vcpu, VCPU_SVE_FINALIZED) 1459 1460 #define kvm_has_mte(kvm) \ 1461 (system_supports_mte() && \ 1462 test_bit(KVM_ARCH_FLAG_MTE_ENABLED, &(kvm)->arch.flags)) 1463 1464 #define kvm_supports_32bit_el0() \ 1465 (system_supports_32bit_el0() && \ 1466 !static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1467 1468 #define kvm_vm_has_ran_once(kvm) \ 1469 (test_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &(kvm)->arch.flags)) 1470 1471 static inline bool __vcpu_has_feature(const struct kvm_arch *ka, int feature) 1472 { 1473 return test_bit(feature, ka->vcpu_features); 1474 } 1475 1476 #define kvm_vcpu_has_feature(k, f) __vcpu_has_feature(&(k)->arch, (f)) 1477 #define vcpu_has_feature(v, f) __vcpu_has_feature(&(v)->kvm->arch, (f)) 1478 1479 #define kvm_vcpu_initialized(v) vcpu_get_flag(vcpu, VCPU_INITIALIZED) 1480 1481 int kvm_trng_call(struct kvm_vcpu *vcpu); 1482 #ifdef CONFIG_KVM 1483 extern phys_addr_t hyp_mem_base; 1484 extern phys_addr_t hyp_mem_size; 1485 void __init kvm_hyp_reserve(void); 1486 #else 1487 static inline void kvm_hyp_reserve(void) { } 1488 #endif 1489 1490 void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu); 1491 bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu); 1492 1493 static inline u64 *__vm_id_reg(struct kvm_arch *ka, u32 reg) 1494 { 1495 switch (reg) { 1496 case sys_reg(3, 0, 0, 1, 0) ... sys_reg(3, 0, 0, 7, 7): 1497 return &ka->id_regs[IDREG_IDX(reg)]; 1498 case SYS_CTR_EL0: 1499 return &ka->ctr_el0; 1500 case SYS_MIDR_EL1: 1501 return &ka->midr_el1; 1502 case SYS_REVIDR_EL1: 1503 return &ka->revidr_el1; 1504 case SYS_AIDR_EL1: 1505 return &ka->aidr_el1; 1506 default: 1507 WARN_ON_ONCE(1); 1508 return NULL; 1509 } 1510 } 1511 1512 #define kvm_read_vm_id_reg(kvm, reg) \ 1513 ({ u64 __val = *__vm_id_reg(&(kvm)->arch, reg); __val; }) 1514 1515 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val); 1516 1517 #define __expand_field_sign_unsigned(id, fld, val) \ 1518 ((u64)SYS_FIELD_VALUE(id, fld, val)) 1519 1520 #define __expand_field_sign_signed(id, fld, val) \ 1521 ({ \ 1522 u64 __val = SYS_FIELD_VALUE(id, fld, val); \ 1523 sign_extend64(__val, id##_##fld##_WIDTH - 1); \ 1524 }) 1525 1526 #define get_idreg_field_unsigned(kvm, id, fld) \ 1527 ({ \ 1528 u64 __val = kvm_read_vm_id_reg((kvm), SYS_##id); \ 1529 FIELD_GET(id##_##fld##_MASK, __val); \ 1530 }) 1531 1532 #define get_idreg_field_signed(kvm, id, fld) \ 1533 ({ \ 1534 u64 __val = get_idreg_field_unsigned(kvm, id, fld); \ 1535 sign_extend64(__val, id##_##fld##_WIDTH - 1); \ 1536 }) 1537 1538 #define get_idreg_field_enum(kvm, id, fld) \ 1539 get_idreg_field_unsigned(kvm, id, fld) 1540 1541 #define kvm_cmp_feat_signed(kvm, id, fld, op, limit) \ 1542 (get_idreg_field_signed((kvm), id, fld) op __expand_field_sign_signed(id, fld, limit)) 1543 1544 #define kvm_cmp_feat_unsigned(kvm, id, fld, op, limit) \ 1545 (get_idreg_field_unsigned((kvm), id, fld) op __expand_field_sign_unsigned(id, fld, limit)) 1546 1547 #define kvm_cmp_feat(kvm, id, fld, op, limit) \ 1548 (id##_##fld##_SIGNED ? \ 1549 kvm_cmp_feat_signed(kvm, id, fld, op, limit) : \ 1550 kvm_cmp_feat_unsigned(kvm, id, fld, op, limit)) 1551 1552 #define __kvm_has_feat(kvm, id, fld, limit) \ 1553 kvm_cmp_feat(kvm, id, fld, >=, limit) 1554 1555 #define kvm_has_feat(kvm, ...) __kvm_has_feat(kvm, __VA_ARGS__) 1556 1557 #define __kvm_has_feat_enum(kvm, id, fld, val) \ 1558 kvm_cmp_feat_unsigned(kvm, id, fld, ==, val) 1559 1560 #define kvm_has_feat_enum(kvm, ...) __kvm_has_feat_enum(kvm, __VA_ARGS__) 1561 1562 #define kvm_has_feat_range(kvm, id, fld, min, max) \ 1563 (kvm_cmp_feat(kvm, id, fld, >=, min) && \ 1564 kvm_cmp_feat(kvm, id, fld, <=, max)) 1565 1566 /* Check for a given level of PAuth support */ 1567 #define kvm_has_pauth(k, l) \ 1568 ({ \ 1569 bool pa, pi, pa3; \ 1570 \ 1571 pa = kvm_has_feat((k), ID_AA64ISAR1_EL1, APA, l); \ 1572 pa &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPA, IMP); \ 1573 pi = kvm_has_feat((k), ID_AA64ISAR1_EL1, API, l); \ 1574 pi &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPI, IMP); \ 1575 pa3 = kvm_has_feat((k), ID_AA64ISAR2_EL1, APA3, l); \ 1576 pa3 &= kvm_has_feat((k), ID_AA64ISAR2_EL1, GPA3, IMP); \ 1577 \ 1578 (pa + pi + pa3) == 1; \ 1579 }) 1580 1581 #define kvm_has_fpmr(k) \ 1582 (system_supports_fpmr() && \ 1583 kvm_has_feat((k), ID_AA64PFR2_EL1, FPMR, IMP)) 1584 1585 #define kvm_has_tcr2(k) \ 1586 (kvm_has_feat((k), ID_AA64MMFR3_EL1, TCRX, IMP)) 1587 1588 #define kvm_has_s1pie(k) \ 1589 (kvm_has_feat((k), ID_AA64MMFR3_EL1, S1PIE, IMP)) 1590 1591 #define kvm_has_s1poe(k) \ 1592 (kvm_has_feat((k), ID_AA64MMFR3_EL1, S1POE, IMP)) 1593 1594 #define kvm_has_ras(k) \ 1595 (kvm_has_feat((k), ID_AA64PFR0_EL1, RAS, IMP)) 1596 1597 #define kvm_has_sctlr2(k) \ 1598 (kvm_has_feat((k), ID_AA64MMFR3_EL1, SCTLRX, IMP)) 1599 1600 static inline bool kvm_arch_has_irq_bypass(void) 1601 { 1602 return true; 1603 } 1604 1605 void compute_fgu(struct kvm *kvm, enum fgt_group_id fgt); 1606 void get_reg_fixed_bits(struct kvm *kvm, enum vcpu_sysreg reg, u64 *res0, u64 *res1); 1607 void check_feature_map(void); 1608 void kvm_vcpu_load_fgt(struct kvm_vcpu *vcpu); 1609 1610 static __always_inline enum fgt_group_id __fgt_reg_to_group_id(enum vcpu_sysreg reg) 1611 { 1612 switch (reg) { 1613 case HFGRTR_EL2: 1614 case HFGWTR_EL2: 1615 return HFGRTR_GROUP; 1616 case HFGITR_EL2: 1617 return HFGITR_GROUP; 1618 case HDFGRTR_EL2: 1619 case HDFGWTR_EL2: 1620 return HDFGRTR_GROUP; 1621 case HAFGRTR_EL2: 1622 return HAFGRTR_GROUP; 1623 case HFGRTR2_EL2: 1624 case HFGWTR2_EL2: 1625 return HFGRTR2_GROUP; 1626 case HFGITR2_EL2: 1627 return HFGITR2_GROUP; 1628 case HDFGRTR2_EL2: 1629 case HDFGWTR2_EL2: 1630 return HDFGRTR2_GROUP; 1631 default: 1632 BUILD_BUG_ON(1); 1633 } 1634 } 1635 1636 #define vcpu_fgt(vcpu, reg) \ 1637 ({ \ 1638 enum fgt_group_id id = __fgt_reg_to_group_id(reg); \ 1639 u64 *p; \ 1640 switch (reg) { \ 1641 case HFGWTR_EL2: \ 1642 case HDFGWTR_EL2: \ 1643 case HFGWTR2_EL2: \ 1644 case HDFGWTR2_EL2: \ 1645 p = &(vcpu)->arch.fgt[id].w; \ 1646 break; \ 1647 default: \ 1648 p = &(vcpu)->arch.fgt[id].r; \ 1649 break; \ 1650 } \ 1651 \ 1652 p; \ 1653 }) 1654 1655 #endif /* __ARM64_KVM_HOST_H__ */ 1656