1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/asm/kvm_host.h: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 */ 10 11 #ifndef __ARM64_KVM_HOST_H__ 12 #define __ARM64_KVM_HOST_H__ 13 14 #include <linux/arm-smccc.h> 15 #include <linux/bitmap.h> 16 #include <linux/types.h> 17 #include <linux/jump_label.h> 18 #include <linux/kvm_types.h> 19 #include <linux/maple_tree.h> 20 #include <linux/percpu.h> 21 #include <linux/psci.h> 22 #include <asm/arch_gicv3.h> 23 #include <asm/barrier.h> 24 #include <asm/cpufeature.h> 25 #include <asm/cputype.h> 26 #include <asm/daifflags.h> 27 #include <asm/fpsimd.h> 28 #include <asm/kvm.h> 29 #include <asm/kvm_asm.h> 30 #include <asm/vncr_mapping.h> 31 32 #define __KVM_HAVE_ARCH_INTC_INITIALIZED 33 34 #define KVM_HALT_POLL_NS_DEFAULT 500000 35 36 #include <kvm/arm_vgic.h> 37 #include <kvm/arm_arch_timer.h> 38 #include <kvm/arm_pmu.h> 39 40 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS 41 42 #define KVM_VCPU_MAX_FEATURES 10 43 #define KVM_VCPU_VALID_FEATURES (BIT(KVM_VCPU_MAX_FEATURES) - 1) 44 45 #define KVM_REQ_SLEEP \ 46 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 47 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1) 48 #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2) 49 #define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(3) 50 #define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4) 51 #define KVM_REQ_RELOAD_PMU KVM_ARCH_REQ(5) 52 #define KVM_REQ_SUSPEND KVM_ARCH_REQ(6) 53 #define KVM_REQ_RESYNC_PMU_EL0 KVM_ARCH_REQ(7) 54 #define KVM_REQ_NESTED_S2_UNMAP KVM_ARCH_REQ(8) 55 #define KVM_REQ_GUEST_HYP_IRQ_PENDING KVM_ARCH_REQ(9) 56 #define KVM_REQ_MAP_L1_VNCR_EL2 KVM_ARCH_REQ(10) 57 #define KVM_REQ_VGIC_PROCESS_UPDATE KVM_ARCH_REQ(11) 58 59 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \ 60 KVM_DIRTY_LOG_INITIALLY_SET) 61 62 #define KVM_HAVE_MMU_RWLOCK 63 64 /* 65 * Mode of operation configurable with kvm-arm.mode early param. 66 * See Documentation/admin-guide/kernel-parameters.txt for more information. 67 */ 68 enum kvm_mode { 69 KVM_MODE_DEFAULT, 70 KVM_MODE_PROTECTED, 71 KVM_MODE_NV, 72 KVM_MODE_NONE, 73 }; 74 #ifdef CONFIG_KVM 75 enum kvm_mode kvm_get_mode(void); 76 void kvm_force_disabled(void); 77 #else 78 static inline enum kvm_mode kvm_get_mode(void) { return KVM_MODE_NONE; }; 79 static inline void kvm_force_disabled(void) { }; 80 #endif 81 82 extern unsigned int __ro_after_init kvm_sve_max_vl; 83 extern unsigned int __ro_after_init kvm_host_sve_max_vl; 84 int __init kvm_arm_init_sve(void); 85 86 u32 __attribute_const__ kvm_target_cpu(void); 87 void kvm_reset_vcpu(struct kvm_vcpu *vcpu); 88 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu); 89 90 struct kvm_hyp_memcache { 91 phys_addr_t head; 92 unsigned long nr_pages; 93 struct pkvm_mapping *mapping; /* only used from EL1 */ 94 95 #define HYP_MEMCACHE_ACCOUNT_STAGE2 BIT(1) 96 unsigned long flags; 97 }; 98 99 static inline void push_hyp_memcache(struct kvm_hyp_memcache *mc, 100 phys_addr_t *p, 101 phys_addr_t (*to_pa)(void *virt)) 102 { 103 *p = mc->head; 104 mc->head = to_pa(p); 105 mc->nr_pages++; 106 } 107 108 static inline void *pop_hyp_memcache(struct kvm_hyp_memcache *mc, 109 void *(*to_va)(phys_addr_t phys)) 110 { 111 phys_addr_t *p = to_va(mc->head & PAGE_MASK); 112 113 if (!mc->nr_pages) 114 return NULL; 115 116 mc->head = *p; 117 mc->nr_pages--; 118 119 return p; 120 } 121 122 static inline int __topup_hyp_memcache(struct kvm_hyp_memcache *mc, 123 unsigned long min_pages, 124 void *(*alloc_fn)(void *arg), 125 phys_addr_t (*to_pa)(void *virt), 126 void *arg) 127 { 128 while (mc->nr_pages < min_pages) { 129 phys_addr_t *p = alloc_fn(arg); 130 131 if (!p) 132 return -ENOMEM; 133 push_hyp_memcache(mc, p, to_pa); 134 } 135 136 return 0; 137 } 138 139 static inline void __free_hyp_memcache(struct kvm_hyp_memcache *mc, 140 void (*free_fn)(void *virt, void *arg), 141 void *(*to_va)(phys_addr_t phys), 142 void *arg) 143 { 144 while (mc->nr_pages) 145 free_fn(pop_hyp_memcache(mc, to_va), arg); 146 } 147 148 void free_hyp_memcache(struct kvm_hyp_memcache *mc); 149 int topup_hyp_memcache(struct kvm_hyp_memcache *mc, unsigned long min_pages); 150 151 struct kvm_vmid { 152 atomic64_t id; 153 }; 154 155 struct kvm_s2_mmu { 156 struct kvm_vmid vmid; 157 158 /* 159 * stage2 entry level table 160 * 161 * Two kvm_s2_mmu structures in the same VM can point to the same 162 * pgd here. This happens when running a guest using a 163 * translation regime that isn't affected by its own stage-2 164 * translation, such as a non-VHE hypervisor running at vEL2, or 165 * for vEL1/EL0 with vHCR_EL2.VM == 0. In that case, we use the 166 * canonical stage-2 page tables. 167 */ 168 phys_addr_t pgd_phys; 169 struct kvm_pgtable *pgt; 170 171 /* 172 * VTCR value used on the host. For a non-NV guest (or a NV 173 * guest that runs in a context where its own S2 doesn't 174 * apply), its T0SZ value reflects that of the IPA size. 175 * 176 * For a shadow S2 MMU, T0SZ reflects the PARange exposed to 177 * the guest. 178 */ 179 u64 vtcr; 180 181 /* The last vcpu id that ran on each physical CPU */ 182 int __percpu *last_vcpu_ran; 183 184 #define KVM_ARM_EAGER_SPLIT_CHUNK_SIZE_DEFAULT 0 185 /* 186 * Memory cache used to split 187 * KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE worth of huge pages. It 188 * is used to allocate stage2 page tables while splitting huge 189 * pages. The choice of KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE 190 * influences both the capacity of the split page cache, and 191 * how often KVM reschedules. Be wary of raising CHUNK_SIZE 192 * too high. 193 * 194 * Protected by kvm->slots_lock. 195 */ 196 struct kvm_mmu_memory_cache split_page_cache; 197 uint64_t split_page_chunk_size; 198 199 struct kvm_arch *arch; 200 201 /* 202 * For a shadow stage-2 MMU, the virtual vttbr used by the 203 * host to parse the guest S2. 204 * This either contains: 205 * - the virtual VTTBR programmed by the guest hypervisor with 206 * CnP cleared 207 * - The value 1 (VMID=0, BADDR=0, CnP=1) if invalid 208 * 209 * We also cache the full VTCR which gets used for TLB invalidation, 210 * taking the ARM ARM's "Any of the bits in VTCR_EL2 are permitted 211 * to be cached in a TLB" to the letter. 212 */ 213 u64 tlb_vttbr; 214 u64 tlb_vtcr; 215 216 /* 217 * true when this represents a nested context where virtual 218 * HCR_EL2.VM == 1 219 */ 220 bool nested_stage2_enabled; 221 222 #ifdef CONFIG_PTDUMP_STAGE2_DEBUGFS 223 struct dentry *shadow_pt_debugfs_dentry; 224 #endif 225 226 /* 227 * true when this MMU needs to be unmapped before being used for a new 228 * purpose. 229 */ 230 bool pending_unmap; 231 232 /* 233 * 0: Nobody is currently using this, check vttbr for validity 234 * >0: Somebody is actively using this. 235 */ 236 atomic_t refcnt; 237 }; 238 239 struct kvm_arch_memory_slot { 240 }; 241 242 /** 243 * struct kvm_smccc_features: Descriptor of the hypercall services exposed to the guests 244 * 245 * @std_bmap: Bitmap of standard secure service calls 246 * @std_hyp_bmap: Bitmap of standard hypervisor service calls 247 * @vendor_hyp_bmap: Bitmap of vendor specific hypervisor service calls 248 */ 249 struct kvm_smccc_features { 250 unsigned long std_bmap; 251 unsigned long std_hyp_bmap; 252 unsigned long vendor_hyp_bmap; /* Function numbers 0-63 */ 253 unsigned long vendor_hyp_bmap_2; /* Function numbers 64-127 */ 254 }; 255 256 typedef u16 pkvm_handle_t; 257 258 struct kvm_protected_vm { 259 pkvm_handle_t handle; 260 struct kvm_hyp_memcache teardown_mc; 261 struct kvm_hyp_memcache stage2_teardown_mc; 262 bool is_protected; 263 bool is_created; 264 265 /* 266 * True when the guest is being torn down. When in this state, the 267 * guest's vCPUs can't be loaded anymore, but its pages can be 268 * reclaimed by the host. 269 */ 270 bool is_dying; 271 }; 272 273 struct kvm_mpidr_data { 274 u64 mpidr_mask; 275 DECLARE_FLEX_ARRAY(u16, cmpidr_to_idx); 276 }; 277 278 static inline u16 kvm_mpidr_index(struct kvm_mpidr_data *data, u64 mpidr) 279 { 280 unsigned long index = 0, mask = data->mpidr_mask; 281 unsigned long aff = mpidr & MPIDR_HWID_BITMASK; 282 283 bitmap_gather(&index, &aff, &mask, fls(mask)); 284 285 return index; 286 } 287 288 struct kvm_sysreg_masks; 289 290 enum fgt_group_id { 291 __NO_FGT_GROUP__, 292 HFGRTR_GROUP, 293 HFGWTR_GROUP = HFGRTR_GROUP, 294 HDFGRTR_GROUP, 295 HDFGWTR_GROUP = HDFGRTR_GROUP, 296 HFGITR_GROUP, 297 HAFGRTR_GROUP, 298 HFGRTR2_GROUP, 299 HFGWTR2_GROUP = HFGRTR2_GROUP, 300 HDFGRTR2_GROUP, 301 HDFGWTR2_GROUP = HDFGRTR2_GROUP, 302 HFGITR2_GROUP, 303 ICH_HFGRTR_GROUP, 304 ICH_HFGWTR_GROUP = ICH_HFGRTR_GROUP, 305 ICH_HFGITR_GROUP, 306 307 /* Must be last */ 308 __NR_FGT_GROUP_IDS__ 309 }; 310 311 struct kvm_arch { 312 struct kvm_s2_mmu mmu; 313 314 /* 315 * Fine-Grained UNDEF, mimicking the FGT layout defined by the 316 * architecture. We track them globally, as we present the 317 * same feature-set to all vcpus. 318 * 319 * Index 0 is currently spare. 320 */ 321 u64 fgu[__NR_FGT_GROUP_IDS__]; 322 323 /* 324 * Stage 2 paging state for VMs with nested S2 using a virtual 325 * VMID. 326 */ 327 struct kvm_s2_mmu **nested_mmus; 328 size_t nested_mmus_size; 329 int nested_mmus_next; 330 331 /* Interrupt controller */ 332 struct vgic_dist vgic; 333 334 /* Timers */ 335 struct arch_timer_vm_data timer_data; 336 337 /* Mandated version of PSCI */ 338 u32 psci_version; 339 340 /* Protects VM-scoped configuration data */ 341 struct mutex config_lock; 342 343 /* 344 * If we encounter a data abort without valid instruction syndrome 345 * information, report this to user space. User space can (and 346 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is 347 * supported. 348 */ 349 #define KVM_ARCH_FLAG_RETURN_NISV_IO_ABORT_TO_USER 0 350 /* Memory Tagging Extension enabled for the guest */ 351 #define KVM_ARCH_FLAG_MTE_ENABLED 1 352 /* At least one vCPU has ran in the VM */ 353 #define KVM_ARCH_FLAG_HAS_RAN_ONCE 2 354 /* The vCPU feature set for the VM is configured */ 355 #define KVM_ARCH_FLAG_VCPU_FEATURES_CONFIGURED 3 356 /* PSCI SYSTEM_SUSPEND enabled for the guest */ 357 #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED 4 358 /* VM counter offset */ 359 #define KVM_ARCH_FLAG_VM_COUNTER_OFFSET 5 360 /* Timer PPIs made immutable */ 361 #define KVM_ARCH_FLAG_TIMER_PPIS_IMMUTABLE 6 362 /* Initial ID reg values loaded */ 363 #define KVM_ARCH_FLAG_ID_REGS_INITIALIZED 7 364 /* Fine-Grained UNDEF initialised */ 365 #define KVM_ARCH_FLAG_FGU_INITIALIZED 8 366 /* SVE exposed to guest */ 367 #define KVM_ARCH_FLAG_GUEST_HAS_SVE 9 368 /* MIDR_EL1, REVIDR_EL1, and AIDR_EL1 are writable from userspace */ 369 #define KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS 10 370 /* Unhandled SEAs are taken to userspace */ 371 #define KVM_ARCH_FLAG_EXIT_SEA 11 372 unsigned long flags; 373 374 /* VM-wide vCPU feature set */ 375 DECLARE_BITMAP(vcpu_features, KVM_VCPU_MAX_FEATURES); 376 377 /* MPIDR to vcpu index mapping, optional */ 378 struct kvm_mpidr_data *mpidr_data; 379 380 /* 381 * VM-wide PMU filter, implemented as a bitmap and big enough for 382 * up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+). 383 */ 384 unsigned long *pmu_filter; 385 struct arm_pmu *arm_pmu; 386 387 cpumask_var_t supported_cpus; 388 389 /* Maximum number of counters for the guest */ 390 u8 nr_pmu_counters; 391 392 /* PMMIR_EL1.SLOTS value exposed to the guest. */ 393 u8 pmmir_slots; 394 395 /* Hypercall features firmware registers' descriptor */ 396 struct kvm_smccc_features smccc_feat; 397 struct maple_tree smccc_filter; 398 399 /* 400 * Emulated CPU ID registers per VM 401 * (Op0, Op1, CRn, CRm, Op2) of the ID registers to be saved in it 402 * is (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8. 403 * 404 * These emulated idregs are VM-wide, but accessed from the context of a vCPU. 405 * Atomic access to multiple idregs are guarded by kvm_arch.config_lock. 406 */ 407 #define IDREG_IDX(id) (((sys_reg_CRm(id) - 1) << 3) | sys_reg_Op2(id)) 408 #define KVM_ARM_ID_REG_NUM (IDREG_IDX(sys_reg(3, 0, 0, 7, 7)) + 1) 409 u64 id_regs[KVM_ARM_ID_REG_NUM]; 410 411 u64 midr_el1; 412 u64 revidr_el1; 413 u64 aidr_el1; 414 u64 ctr_el0; 415 416 /* Masks for VNCR-backed and general EL2 sysregs */ 417 struct kvm_sysreg_masks *sysreg_masks; 418 419 /* Count the number of VNCR_EL2 TLBs */ 420 atomic_t vncr_tlb_count; 421 422 /* 423 * For an untrusted host VM, 'pkvm.handle' is used to lookup 424 * the associated pKVM instance in the hypervisor. 425 */ 426 struct kvm_protected_vm pkvm; 427 428 #ifdef CONFIG_PTDUMP_STAGE2_DEBUGFS 429 /* Nested virtualization info */ 430 struct dentry *debugfs_nv_dentry; 431 #endif 432 }; 433 434 struct kvm_vcpu_fault_info { 435 u64 esr_el2; /* Hyp Syndrom Register */ 436 u64 far_el2; /* Hyp Fault Address Register */ 437 u64 hpfar_el2; /* Hyp IPA Fault Address Register */ 438 u64 disr_el1; /* Deferred [SError] Status Register */ 439 }; 440 441 /* 442 * VNCR() just places the VNCR_capable registers in the enum after 443 * __VNCR_START__, and the value (after correction) to be an 8-byte offset 444 * from the VNCR base. As we don't require the enum to be otherwise ordered, 445 * we need the terrible hack below to ensure that we correctly size the 446 * sys_regs array, no matter what. 447 * 448 * The __MAX__ macro has been lifted from Sean Eron Anderson's wonderful 449 * treasure trove of bit hacks: 450 * https://graphics.stanford.edu/~seander/bithacks.html#IntegerMinOrMax 451 */ 452 #define __MAX__(x,y) ((x) ^ (((x) ^ (y)) & -((x) < (y)))) 453 #define VNCR(r) \ 454 __before_##r, \ 455 r = __VNCR_START__ + ((VNCR_ ## r) / 8), \ 456 __after_##r = __MAX__(__before_##r - 1, r) 457 458 enum vcpu_sysreg { 459 __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ 460 MPIDR_EL1, /* MultiProcessor Affinity Register */ 461 CLIDR_EL1, /* Cache Level ID Register */ 462 CSSELR_EL1, /* Cache Size Selection Register */ 463 TPIDR_EL0, /* Thread ID, User R/W */ 464 TPIDRRO_EL0, /* Thread ID, User R/O */ 465 TPIDR_EL1, /* Thread ID, Privileged */ 466 CNTKCTL_EL1, /* Timer Control Register (EL1) */ 467 PAR_EL1, /* Physical Address Register */ 468 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ 469 OSLSR_EL1, /* OS Lock Status Register */ 470 DISR_EL1, /* Deferred Interrupt Status Register */ 471 472 /* Performance Monitors Registers */ 473 PMCR_EL0, /* Control Register */ 474 PMSELR_EL0, /* Event Counter Selection Register */ 475 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */ 476 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30, 477 PMCCNTR_EL0, /* Cycle Counter Register */ 478 PMEVTYPER0_EL0, /* Event Type Register (0-30) */ 479 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30, 480 PMCCFILTR_EL0, /* Cycle Count Filter Register */ 481 PMCNTENSET_EL0, /* Count Enable Set Register */ 482 PMINTENSET_EL1, /* Interrupt Enable Set Register */ 483 PMOVSSET_EL0, /* Overflow Flag Status Set Register */ 484 PMUSERENR_EL0, /* User Enable Register */ 485 486 /* Pointer Authentication Registers in a strict increasing order. */ 487 APIAKEYLO_EL1, 488 APIAKEYHI_EL1, 489 APIBKEYLO_EL1, 490 APIBKEYHI_EL1, 491 APDAKEYLO_EL1, 492 APDAKEYHI_EL1, 493 APDBKEYLO_EL1, 494 APDBKEYHI_EL1, 495 APGAKEYLO_EL1, 496 APGAKEYHI_EL1, 497 498 /* Memory Tagging Extension registers */ 499 RGSR_EL1, /* Random Allocation Tag Seed Register */ 500 GCR_EL1, /* Tag Control Register */ 501 TFSRE0_EL1, /* Tag Fault Status Register (EL0) */ 502 503 POR_EL0, /* Permission Overlay Register 0 (EL0) */ 504 505 /* FP/SIMD/SVE */ 506 SVCR, 507 FPMR, 508 509 /* 32bit specific registers. */ 510 DACR32_EL2, /* Domain Access Control Register */ 511 IFSR32_EL2, /* Instruction Fault Status Register */ 512 FPEXC32_EL2, /* Floating-Point Exception Control Register */ 513 DBGVCR32_EL2, /* Debug Vector Catch Register */ 514 515 /* EL2 registers */ 516 ACTLR_EL2, /* Auxiliary Control Register (EL2) */ 517 CPTR_EL2, /* Architectural Feature Trap Register (EL2) */ 518 HACR_EL2, /* Hypervisor Auxiliary Control Register */ 519 TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */ 520 TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */ 521 TCR_EL2, /* Translation Control Register (EL2) */ 522 PIRE0_EL2, /* Permission Indirection Register 0 (EL2) */ 523 PIR_EL2, /* Permission Indirection Register 1 (EL2) */ 524 POR_EL2, /* Permission Overlay Register 2 (EL2) */ 525 SPSR_EL2, /* EL2 saved program status register */ 526 ELR_EL2, /* EL2 exception link register */ 527 AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */ 528 AFSR1_EL2, /* Auxiliary Fault Status Register 1 (EL2) */ 529 ESR_EL2, /* Exception Syndrome Register (EL2) */ 530 FAR_EL2, /* Fault Address Register (EL2) */ 531 HPFAR_EL2, /* Hypervisor IPA Fault Address Register */ 532 MAIR_EL2, /* Memory Attribute Indirection Register (EL2) */ 533 AMAIR_EL2, /* Auxiliary Memory Attribute Indirection Register (EL2) */ 534 VBAR_EL2, /* Vector Base Address Register (EL2) */ 535 RVBAR_EL2, /* Reset Vector Base Address Register */ 536 CONTEXTIDR_EL2, /* Context ID Register (EL2) */ 537 SP_EL2, /* EL2 Stack Pointer */ 538 CNTHP_CTL_EL2, 539 CNTHP_CVAL_EL2, 540 CNTHV_CTL_EL2, 541 CNTHV_CVAL_EL2, 542 543 /* Anything from this can be RES0/RES1 sanitised */ 544 MARKER(__SANITISED_REG_START__), 545 SCTLR_EL2, /* System Control Register (EL2) */ 546 TCR2_EL2, /* Extended Translation Control Register (EL2) */ 547 SCTLR2_EL2, /* System Control Register 2 (EL2) */ 548 MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */ 549 CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */ 550 ZCR_EL2, /* SVE Control Register (EL2) */ 551 HCR_EL2, /* Hypervisor Control Register */ 552 553 /* Any VNCR-capable reg goes after this point */ 554 MARKER(__VNCR_START__), 555 556 VNCR(SCTLR_EL1),/* System Control Register */ 557 VNCR(ACTLR_EL1),/* Auxiliary Control Register */ 558 VNCR(CPACR_EL1),/* Coprocessor Access Control */ 559 VNCR(ZCR_EL1), /* SVE Control */ 560 VNCR(TTBR0_EL1),/* Translation Table Base Register 0 */ 561 VNCR(TTBR1_EL1),/* Translation Table Base Register 1 */ 562 VNCR(TCR_EL1), /* Translation Control Register */ 563 VNCR(TCR2_EL1), /* Extended Translation Control Register */ 564 VNCR(SCTLR2_EL1), /* System Control Register 2 */ 565 VNCR(ESR_EL1), /* Exception Syndrome Register */ 566 VNCR(AFSR0_EL1),/* Auxiliary Fault Status Register 0 */ 567 VNCR(AFSR1_EL1),/* Auxiliary Fault Status Register 1 */ 568 VNCR(FAR_EL1), /* Fault Address Register */ 569 VNCR(MAIR_EL1), /* Memory Attribute Indirection Register */ 570 VNCR(VBAR_EL1), /* Vector Base Address Register */ 571 VNCR(CONTEXTIDR_EL1), /* Context ID Register */ 572 VNCR(AMAIR_EL1),/* Aux Memory Attribute Indirection Register */ 573 VNCR(MDSCR_EL1),/* Monitor Debug System Control Register */ 574 VNCR(ELR_EL1), 575 VNCR(SP_EL1), 576 VNCR(SPSR_EL1), 577 VNCR(TFSR_EL1), /* Tag Fault Status Register (EL1) */ 578 VNCR(VPIDR_EL2),/* Virtualization Processor ID Register */ 579 VNCR(VMPIDR_EL2),/* Virtualization Multiprocessor ID Register */ 580 VNCR(NVHCR_EL2),/* NV Hypervisor Configuration Register */ 581 VNCR(HSTR_EL2), /* Hypervisor System Trap Register */ 582 VNCR(VTTBR_EL2),/* Virtualization Translation Table Base Register */ 583 VNCR(VTCR_EL2), /* Virtualization Translation Control Register */ 584 VNCR(TPIDR_EL2),/* EL2 Software Thread ID Register */ 585 VNCR(HCRX_EL2), /* Extended Hypervisor Configuration Register */ 586 587 /* Permission Indirection Extension registers */ 588 VNCR(PIR_EL1), /* Permission Indirection Register 1 (EL1) */ 589 VNCR(PIRE0_EL1), /* Permission Indirection Register 0 (EL1) */ 590 591 VNCR(POR_EL1), /* Permission Overlay Register 1 (EL1) */ 592 593 /* FEAT_RAS registers */ 594 VNCR(VDISR_EL2), 595 VNCR(VSESR_EL2), 596 597 VNCR(HFGRTR_EL2), 598 VNCR(HFGWTR_EL2), 599 VNCR(HFGITR_EL2), 600 VNCR(HDFGRTR_EL2), 601 VNCR(HDFGWTR_EL2), 602 VNCR(HAFGRTR_EL2), 603 VNCR(HFGRTR2_EL2), 604 VNCR(HFGWTR2_EL2), 605 VNCR(HFGITR2_EL2), 606 VNCR(HDFGRTR2_EL2), 607 VNCR(HDFGWTR2_EL2), 608 609 VNCR(VNCR_EL2), 610 611 VNCR(CNTVOFF_EL2), 612 VNCR(CNTV_CVAL_EL0), 613 VNCR(CNTV_CTL_EL0), 614 VNCR(CNTP_CVAL_EL0), 615 VNCR(CNTP_CTL_EL0), 616 617 VNCR(ICH_LR0_EL2), 618 VNCR(ICH_LR1_EL2), 619 VNCR(ICH_LR2_EL2), 620 VNCR(ICH_LR3_EL2), 621 VNCR(ICH_LR4_EL2), 622 VNCR(ICH_LR5_EL2), 623 VNCR(ICH_LR6_EL2), 624 VNCR(ICH_LR7_EL2), 625 VNCR(ICH_LR8_EL2), 626 VNCR(ICH_LR9_EL2), 627 VNCR(ICH_LR10_EL2), 628 VNCR(ICH_LR11_EL2), 629 VNCR(ICH_LR12_EL2), 630 VNCR(ICH_LR13_EL2), 631 VNCR(ICH_LR14_EL2), 632 VNCR(ICH_LR15_EL2), 633 634 VNCR(ICH_AP0R0_EL2), 635 VNCR(ICH_AP0R1_EL2), 636 VNCR(ICH_AP0R2_EL2), 637 VNCR(ICH_AP0R3_EL2), 638 VNCR(ICH_AP1R0_EL2), 639 VNCR(ICH_AP1R1_EL2), 640 VNCR(ICH_AP1R2_EL2), 641 VNCR(ICH_AP1R3_EL2), 642 VNCR(ICH_HCR_EL2), 643 VNCR(ICH_VMCR_EL2), 644 645 VNCR(ICH_HFGRTR_EL2), 646 VNCR(ICH_HFGWTR_EL2), 647 VNCR(ICH_HFGITR_EL2), 648 649 NR_SYS_REGS /* Nothing after this line! */ 650 }; 651 652 struct resx { 653 u64 res0; 654 u64 res1; 655 }; 656 657 struct kvm_sysreg_masks { 658 struct resx mask[NR_SYS_REGS - __SANITISED_REG_START__]; 659 }; 660 661 static inline struct resx __kvm_get_sysreg_resx(struct kvm_arch *arch, 662 enum vcpu_sysreg sr) 663 { 664 struct kvm_sysreg_masks *masks; 665 666 masks = arch->sysreg_masks; 667 if (likely(masks && 668 sr >= __SANITISED_REG_START__ && sr < NR_SYS_REGS)) 669 return masks->mask[sr - __SANITISED_REG_START__]; 670 671 return (struct resx){}; 672 } 673 674 #define kvm_get_sysreg_resx(k, sr) __kvm_get_sysreg_resx(&(k)->arch, (sr)) 675 676 static inline void __kvm_set_sysreg_resx(struct kvm_arch *arch, 677 enum vcpu_sysreg sr, struct resx resx) 678 { 679 arch->sysreg_masks->mask[sr - __SANITISED_REG_START__] = resx; 680 } 681 682 #define kvm_set_sysreg_resx(k, sr, resx) \ 683 __kvm_set_sysreg_resx(&(k)->arch, (sr), (resx)) 684 685 struct fgt_masks { 686 const char *str; 687 u64 mask; 688 u64 nmask; 689 u64 res0; 690 u64 res1; 691 }; 692 693 extern struct fgt_masks hfgrtr_masks; 694 extern struct fgt_masks hfgwtr_masks; 695 extern struct fgt_masks hfgitr_masks; 696 extern struct fgt_masks hdfgrtr_masks; 697 extern struct fgt_masks hdfgwtr_masks; 698 extern struct fgt_masks hafgrtr_masks; 699 extern struct fgt_masks hfgrtr2_masks; 700 extern struct fgt_masks hfgwtr2_masks; 701 extern struct fgt_masks hfgitr2_masks; 702 extern struct fgt_masks hdfgrtr2_masks; 703 extern struct fgt_masks hdfgwtr2_masks; 704 extern struct fgt_masks ich_hfgrtr_masks; 705 extern struct fgt_masks ich_hfgwtr_masks; 706 extern struct fgt_masks ich_hfgitr_masks; 707 708 extern struct fgt_masks kvm_nvhe_sym(hfgrtr_masks); 709 extern struct fgt_masks kvm_nvhe_sym(hfgwtr_masks); 710 extern struct fgt_masks kvm_nvhe_sym(hfgitr_masks); 711 extern struct fgt_masks kvm_nvhe_sym(hdfgrtr_masks); 712 extern struct fgt_masks kvm_nvhe_sym(hdfgwtr_masks); 713 extern struct fgt_masks kvm_nvhe_sym(hafgrtr_masks); 714 extern struct fgt_masks kvm_nvhe_sym(hfgrtr2_masks); 715 extern struct fgt_masks kvm_nvhe_sym(hfgwtr2_masks); 716 extern struct fgt_masks kvm_nvhe_sym(hfgitr2_masks); 717 extern struct fgt_masks kvm_nvhe_sym(hdfgrtr2_masks); 718 extern struct fgt_masks kvm_nvhe_sym(hdfgwtr2_masks); 719 extern struct fgt_masks kvm_nvhe_sym(ich_hfgrtr_masks); 720 extern struct fgt_masks kvm_nvhe_sym(ich_hfgwtr_masks); 721 extern struct fgt_masks kvm_nvhe_sym(ich_hfgitr_masks); 722 723 struct kvm_cpu_context { 724 struct user_pt_regs regs; /* sp = sp_el0 */ 725 726 u64 spsr_abt; 727 u64 spsr_und; 728 u64 spsr_irq; 729 u64 spsr_fiq; 730 731 struct user_fpsimd_state fp_regs; 732 733 u64 sys_regs[NR_SYS_REGS]; 734 735 struct kvm_vcpu *__hyp_running_vcpu; 736 737 /* This pointer has to be 4kB aligned. */ 738 u64 *vncr_array; 739 }; 740 741 /* 742 * This structure is instantiated on a per-CPU basis, and contains 743 * data that is: 744 * 745 * - tied to a single physical CPU, and 746 * - either have a lifetime that does not extend past vcpu_put() 747 * - or is an invariant for the lifetime of the system 748 * 749 * Use host_data_ptr(field) as a way to access a pointer to such a 750 * field. 751 */ 752 struct kvm_host_data { 753 #define KVM_HOST_DATA_FLAG_HAS_SPE 0 754 #define KVM_HOST_DATA_FLAG_HAS_TRBE 1 755 #define KVM_HOST_DATA_FLAG_TRBE_ENABLED 2 756 #define KVM_HOST_DATA_FLAG_EL1_TRACING_CONFIGURED 3 757 #define KVM_HOST_DATA_FLAG_VCPU_IN_HYP_CONTEXT 4 758 #define KVM_HOST_DATA_FLAG_L1_VNCR_MAPPED 5 759 #define KVM_HOST_DATA_FLAG_HAS_BRBE 6 760 unsigned long flags; 761 762 struct kvm_cpu_context host_ctxt; 763 764 /* 765 * Hyp VA. 766 * sve_regs is only used in pKVM and if system_supports_sve(). 767 */ 768 struct arm64_sve_state *sve_regs; 769 770 /* Ownership of the FP regs */ 771 enum { 772 FP_STATE_FREE, 773 FP_STATE_HOST_OWNED, 774 FP_STATE_GUEST_OWNED, 775 } fp_owner; 776 777 /* 778 * host_debug_state contains the host registers which are 779 * saved and restored during world switches. 780 */ 781 struct { 782 /* {Break,watch}point registers */ 783 struct kvm_guest_debug_arch regs; 784 /* Statistical profiling extension */ 785 u64 pmscr_el1; 786 u64 pmblimitr_el1; 787 /* Self-hosted trace */ 788 u64 trfcr_el1; 789 u64 trblimitr_el1; 790 /* Values of trap registers for the host before guest entry. */ 791 u64 mdcr_el2; 792 u64 brbcr_el1; 793 } host_debug_state; 794 795 /* Guest trace filter value */ 796 u64 trfcr_while_in_guest; 797 798 /* Number of programmable event counters (PMCR_EL0.N) for this CPU */ 799 unsigned int nr_event_counters; 800 801 /* Number of debug breakpoints/watchpoints for this CPU (minus 1) */ 802 unsigned int debug_brps; 803 unsigned int debug_wrps; 804 805 /* Last vgic_irq part of the AP list recorded in an LR */ 806 struct vgic_irq *last_lr_irq; 807 808 /* PPI state tracking for GICv5-based guests */ 809 struct { 810 DECLARE_BITMAP(pendr, VGIC_V5_NR_PRIVATE_IRQS); 811 812 /* The saved state of the regs when leaving the guest */ 813 DECLARE_BITMAP(activer_exit, VGIC_V5_NR_PRIVATE_IRQS); 814 } vgic_v5_ppi_state; 815 }; 816 817 struct kvm_host_psci_config { 818 /* PSCI version used by host. */ 819 u32 version; 820 u32 smccc_version; 821 822 /* Function IDs used by host if version is v0.1. */ 823 struct psci_0_1_function_ids function_ids_0_1; 824 825 bool psci_0_1_cpu_suspend_implemented; 826 bool psci_0_1_cpu_on_implemented; 827 bool psci_0_1_cpu_off_implemented; 828 bool psci_0_1_migrate_implemented; 829 }; 830 831 extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config); 832 #define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config) 833 834 extern s64 kvm_nvhe_sym(hyp_physvirt_offset); 835 #define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset) 836 837 extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS]; 838 #define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map) 839 840 struct vcpu_reset_state { 841 unsigned long pc; 842 unsigned long r0; 843 bool be; 844 bool reset; 845 }; 846 847 struct vncr_tlb; 848 849 struct kvm_vcpu_arch { 850 struct kvm_cpu_context ctxt; 851 852 /* 853 * Guest floating point state 854 * 855 * The architecture has two main floating point extensions, 856 * the original FPSIMD and SVE. These have overlapping 857 * register views, with the FPSIMD V registers occupying the 858 * low 128 bits of the SVE Z registers. When the core 859 * floating point code saves the register state of a task it 860 * records which view it saved in fp_type. 861 */ 862 struct arm64_sve_state *sve_state; 863 enum fp_type fp_type; 864 unsigned int sve_max_vl; 865 866 /* Stage 2 paging state used by the hardware on next switch */ 867 struct kvm_s2_mmu *hw_mmu; 868 869 /* Values of trap registers for the guest. */ 870 u64 hcr_el2; 871 u64 hcrx_el2; 872 u64 mdcr_el2; 873 874 struct { 875 u64 r; 876 u64 w; 877 } fgt[__NR_FGT_GROUP_IDS__]; 878 879 /* Exception Information */ 880 struct kvm_vcpu_fault_info fault; 881 882 /* Configuration flags, set once and for all before the vcpu can run */ 883 u8 cflags; 884 885 /* Input flags to the hypervisor code, potentially cleared after use */ 886 u8 iflags; 887 888 /* State flags for kernel bookkeeping, unused by the hypervisor code */ 889 u16 sflags; 890 891 /* 892 * Don't run the guest (internal implementation need). 893 * 894 * Contrary to the flags above, this is set/cleared outside of 895 * a vcpu context, and thus cannot be mixed with the flags 896 * themselves (or the flag accesses need to be made atomic). 897 */ 898 bool pause; 899 900 /* 901 * We maintain more than a single set of debug registers to support 902 * debugging the guest from the host and to maintain separate host and 903 * guest state during world switches. vcpu_debug_state are the debug 904 * registers of the vcpu as the guest sees them. 905 * 906 * external_debug_state contains the debug values we want to debug the 907 * guest. This is set via the KVM_SET_GUEST_DEBUG ioctl. 908 */ 909 struct kvm_guest_debug_arch vcpu_debug_state; 910 struct kvm_guest_debug_arch external_debug_state; 911 u64 external_mdscr_el1; 912 913 enum { 914 VCPU_DEBUG_FREE, 915 VCPU_DEBUG_HOST_OWNED, 916 VCPU_DEBUG_GUEST_OWNED, 917 } debug_owner; 918 919 /* VGIC state */ 920 struct vgic_cpu vgic_cpu; 921 struct arch_timer_cpu timer_cpu; 922 struct kvm_pmu pmu; 923 924 /* vcpu power state */ 925 struct kvm_mp_state mp_state; 926 spinlock_t mp_state_lock; 927 928 /* Cache some mmu pages needed inside spinlock regions */ 929 struct kvm_mmu_memory_cache mmu_page_cache; 930 931 /* Pages to top-up the pKVM/EL2 guest pool */ 932 struct kvm_hyp_memcache pkvm_memcache; 933 934 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */ 935 u64 vsesr_el2; 936 937 /* Additional reset state */ 938 struct vcpu_reset_state reset_state; 939 940 /* Guest PV state */ 941 struct { 942 u64 last_steal; 943 gpa_t base; 944 } steal; 945 946 /* Per-vcpu CCSIDR override or NULL */ 947 u32 *ccsidr; 948 949 /* Per-vcpu TLB for VNCR_EL2 -- NULL when !NV */ 950 struct vncr_tlb *vncr_tlb; 951 952 /* Hyp-readable copy of kvm_vcpu::pid */ 953 pid_t pid; 954 }; 955 956 /* 957 * Each 'flag' is composed of a comma-separated triplet: 958 * 959 * - the flag-set it belongs to in the vcpu->arch structure 960 * - the value for that flag 961 * - the mask for that flag 962 * 963 * __vcpu_single_flag() builds such a triplet for a single-bit flag. 964 * unpack_vcpu_flag() extract the flag value from the triplet for 965 * direct use outside of the flag accessors. 966 */ 967 #define __vcpu_single_flag(_set, _f) _set, (_f), (_f) 968 969 #define __unpack_flag(_set, _f, _m) _f 970 #define unpack_vcpu_flag(...) __unpack_flag(__VA_ARGS__) 971 972 #define __build_check_flag(v, flagset, f, m) \ 973 do { \ 974 typeof(v->arch.flagset) *_fset; \ 975 \ 976 /* Check that the flags fit in the mask */ \ 977 BUILD_BUG_ON(HWEIGHT(m) != HWEIGHT((f) | (m))); \ 978 /* Check that the flags fit in the type */ \ 979 BUILD_BUG_ON((sizeof(*_fset) * 8) <= __fls(m)); \ 980 } while (0) 981 982 #define __vcpu_get_flag(v, flagset, f, m) \ 983 ({ \ 984 __build_check_flag(v, flagset, f, m); \ 985 \ 986 READ_ONCE(v->arch.flagset) & (m); \ 987 }) 988 989 /* 990 * Note that the set/clear accessors must be preempt-safe in order to 991 * avoid nesting them with load/put which also manipulate flags... 992 */ 993 #ifdef __KVM_NVHE_HYPERVISOR__ 994 /* the nVHE hypervisor is always non-preemptible */ 995 #define __vcpu_flags_preempt_disable() 996 #define __vcpu_flags_preempt_enable() 997 #else 998 #define __vcpu_flags_preempt_disable() preempt_disable() 999 #define __vcpu_flags_preempt_enable() preempt_enable() 1000 #endif 1001 1002 #define __vcpu_set_flag(v, flagset, f, m) \ 1003 do { \ 1004 typeof(v->arch.flagset) *fset; \ 1005 \ 1006 __build_check_flag(v, flagset, f, m); \ 1007 \ 1008 fset = &v->arch.flagset; \ 1009 __vcpu_flags_preempt_disable(); \ 1010 if (HWEIGHT(m) > 1) \ 1011 *fset &= ~(m); \ 1012 *fset |= (f); \ 1013 __vcpu_flags_preempt_enable(); \ 1014 } while (0) 1015 1016 #define __vcpu_clear_flag(v, flagset, f, m) \ 1017 do { \ 1018 typeof(v->arch.flagset) *fset; \ 1019 \ 1020 __build_check_flag(v, flagset, f, m); \ 1021 \ 1022 fset = &v->arch.flagset; \ 1023 __vcpu_flags_preempt_disable(); \ 1024 *fset &= ~(m); \ 1025 __vcpu_flags_preempt_enable(); \ 1026 } while (0) 1027 1028 #define __vcpu_test_and_clear_flag(v, flagset, f, m) \ 1029 ({ \ 1030 typeof(v->arch.flagset) set; \ 1031 \ 1032 set = __vcpu_get_flag(v, flagset, f, m); \ 1033 __vcpu_clear_flag(v, flagset, f, m); \ 1034 \ 1035 set; \ 1036 }) 1037 1038 #define vcpu_get_flag(v, ...) __vcpu_get_flag((v), __VA_ARGS__) 1039 #define vcpu_set_flag(v, ...) __vcpu_set_flag((v), __VA_ARGS__) 1040 #define vcpu_clear_flag(v, ...) __vcpu_clear_flag((v), __VA_ARGS__) 1041 #define vcpu_test_and_clear_flag(v, ...) \ 1042 __vcpu_test_and_clear_flag((v), __VA_ARGS__) 1043 1044 /* KVM_ARM_VCPU_INIT completed */ 1045 #define VCPU_INITIALIZED __vcpu_single_flag(cflags, BIT(0)) 1046 /* SVE config completed */ 1047 #define VCPU_SVE_FINALIZED __vcpu_single_flag(cflags, BIT(1)) 1048 /* pKVM VCPU setup completed */ 1049 #define VCPU_PKVM_FINALIZED __vcpu_single_flag(cflags, BIT(2)) 1050 1051 /* Exception pending */ 1052 #define PENDING_EXCEPTION __vcpu_single_flag(iflags, BIT(0)) 1053 /* 1054 * PC increment. Overlaps with EXCEPT_MASK on purpose so that it can't 1055 * be set together with an exception... 1056 */ 1057 #define INCREMENT_PC __vcpu_single_flag(iflags, BIT(1)) 1058 /* Target EL/MODE (not a single flag, but let's abuse the macro) */ 1059 #define EXCEPT_MASK __vcpu_single_flag(iflags, GENMASK(3, 1)) 1060 /* Host-set: the hyp flushes the non-protected vCPU state in on entry */ 1061 #define PKVM_HOST_STATE_DIRTY __vcpu_single_flag(iflags, BIT(4)) 1062 1063 /* Helpers to encode exceptions with minimum fuss */ 1064 #define __EXCEPT_MASK_VAL unpack_vcpu_flag(EXCEPT_MASK) 1065 #define __EXCEPT_SHIFT __builtin_ctzl(__EXCEPT_MASK_VAL) 1066 #define __vcpu_except_flags(_f) iflags, (_f << __EXCEPT_SHIFT), __EXCEPT_MASK_VAL 1067 1068 /* 1069 * When PENDING_EXCEPTION is set, EXCEPT_MASK can take the following 1070 * values: 1071 * 1072 * For AArch32 EL1: 1073 */ 1074 #define EXCEPT_AA32_UND __vcpu_except_flags(0) 1075 #define EXCEPT_AA32_IABT __vcpu_except_flags(1) 1076 #define EXCEPT_AA32_DABT __vcpu_except_flags(2) 1077 /* For AArch64: */ 1078 #define EXCEPT_AA64_EL1_SYNC __vcpu_except_flags(0) 1079 #define EXCEPT_AA64_EL1_IRQ __vcpu_except_flags(1) 1080 #define EXCEPT_AA64_EL1_FIQ __vcpu_except_flags(2) 1081 #define EXCEPT_AA64_EL1_SERR __vcpu_except_flags(3) 1082 /* For AArch64 with NV: */ 1083 #define EXCEPT_AA64_EL2_SYNC __vcpu_except_flags(4) 1084 #define EXCEPT_AA64_EL2_IRQ __vcpu_except_flags(5) 1085 #define EXCEPT_AA64_EL2_FIQ __vcpu_except_flags(6) 1086 #define EXCEPT_AA64_EL2_SERR __vcpu_except_flags(7) 1087 1088 /* Physical CPU not in supported_cpus */ 1089 #define ON_UNSUPPORTED_CPU __vcpu_single_flag(sflags, BIT(0)) 1090 /* WFIT instruction trapped */ 1091 #define IN_WFIT __vcpu_single_flag(sflags, BIT(1)) 1092 /* vcpu system registers loaded on physical CPU */ 1093 #define SYSREGS_ON_CPU __vcpu_single_flag(sflags, BIT(2)) 1094 /* Software step state is Active-pending for external debug */ 1095 #define HOST_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(3)) 1096 /* Software step state is Active pending for guest debug */ 1097 #define GUEST_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(4)) 1098 /* PMUSERENR for the guest EL0 is on physical CPU */ 1099 #define PMUSERENR_ON_CPU __vcpu_single_flag(sflags, BIT(5)) 1100 /* WFI instruction trapped */ 1101 #define IN_WFI __vcpu_single_flag(sflags, BIT(6)) 1102 /* KVM is currently emulating a nested ERET */ 1103 #define IN_NESTED_ERET __vcpu_single_flag(sflags, BIT(7)) 1104 /* SError pending for nested guest */ 1105 #define NESTED_SERROR_PENDING __vcpu_single_flag(sflags, BIT(8)) 1106 /* KVM is currently emulating an L2 to L1 exception */ 1107 #define IN_NESTED_EXCEPTION __vcpu_single_flag(sflags, BIT(9)) 1108 1109 #define vcpu_sve_max_vq(vcpu) sve_vq_from_vl((vcpu)->arch.sve_max_vl) 1110 1111 #define vcpu_sve_zcr_elx(vcpu) \ 1112 (unlikely(is_hyp_ctxt(vcpu)) ? ZCR_EL2 : ZCR_EL1) 1113 1114 #define sve_state_size_from_vl(sve_max_vl) ({ \ 1115 size_t __size_ret; \ 1116 unsigned int __vq; \ 1117 \ 1118 if (WARN_ON(!sve_vl_valid(sve_max_vl))) { \ 1119 __size_ret = 0; \ 1120 } else { \ 1121 __vq = sve_vq_from_vl(sve_max_vl); \ 1122 __size_ret = SVE_SIG_REGS_SIZE(__vq); \ 1123 } \ 1124 \ 1125 __size_ret; \ 1126 }) 1127 1128 #define vcpu_sve_state_size(vcpu) sve_state_size_from_vl((vcpu)->arch.sve_max_vl) 1129 1130 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \ 1131 KVM_GUESTDBG_USE_SW_BP | \ 1132 KVM_GUESTDBG_USE_HW | \ 1133 KVM_GUESTDBG_SINGLESTEP) 1134 1135 #define kvm_has_sve(kvm) (system_supports_sve() && \ 1136 test_bit(KVM_ARCH_FLAG_GUEST_HAS_SVE, &(kvm)->arch.flags)) 1137 1138 #ifdef __KVM_NVHE_HYPERVISOR__ 1139 #define vcpu_has_sve(vcpu) kvm_has_sve(kern_hyp_va((vcpu)->kvm)) 1140 #else 1141 #define vcpu_has_sve(vcpu) kvm_has_sve((vcpu)->kvm) 1142 #endif 1143 1144 #ifdef CONFIG_ARM64_PTR_AUTH 1145 #define vcpu_has_ptrauth(vcpu) \ 1146 ((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) || \ 1147 cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) && \ 1148 (vcpu_has_feature(vcpu, KVM_ARM_VCPU_PTRAUTH_ADDRESS) || \ 1149 vcpu_has_feature(vcpu, KVM_ARM_VCPU_PTRAUTH_GENERIC))) 1150 #else 1151 #define vcpu_has_ptrauth(vcpu) false 1152 #endif 1153 1154 #define vcpu_on_unsupported_cpu(vcpu) \ 1155 vcpu_get_flag(vcpu, ON_UNSUPPORTED_CPU) 1156 1157 #define vcpu_set_on_unsupported_cpu(vcpu) \ 1158 vcpu_set_flag(vcpu, ON_UNSUPPORTED_CPU) 1159 1160 #define vcpu_clear_on_unsupported_cpu(vcpu) \ 1161 vcpu_clear_flag(vcpu, ON_UNSUPPORTED_CPU) 1162 1163 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.regs) 1164 1165 /* 1166 * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the 1167 * memory backed version of a register, and not the one most recently 1168 * accessed by a running VCPU. For example, for userspace access or 1169 * for system registers that are never context switched, but only 1170 * emulated. 1171 * 1172 * Don't bother with VNCR-based accesses in the nVHE code, it has no 1173 * business dealing with NV. 1174 */ 1175 static inline u64 *___ctxt_sys_reg(const struct kvm_cpu_context *ctxt, int r) 1176 { 1177 #if !defined (__KVM_NVHE_HYPERVISOR__) 1178 if (unlikely(cpus_have_final_cap(ARM64_HAS_NESTED_VIRT) && 1179 r >= __VNCR_START__ && ctxt->vncr_array)) 1180 return &ctxt->vncr_array[r - __VNCR_START__]; 1181 #endif 1182 return (u64 *)&ctxt->sys_regs[r]; 1183 } 1184 1185 #define __ctxt_sys_reg(c,r) \ 1186 ({ \ 1187 BUILD_BUG_ON(__builtin_constant_p(r) && \ 1188 (r) >= NR_SYS_REGS); \ 1189 ___ctxt_sys_reg(c, r); \ 1190 }) 1191 1192 #define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r)) 1193 1194 u64 kvm_vcpu_apply_reg_masks(const struct kvm_vcpu *, enum vcpu_sysreg, u64); 1195 1196 #define __vcpu_assign_sys_reg(v, r, val) \ 1197 do { \ 1198 const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \ 1199 u64 __v = (val); \ 1200 if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \ 1201 __v = kvm_vcpu_apply_reg_masks((v), (r), __v); \ 1202 \ 1203 ctxt_sys_reg(ctxt, (r)) = __v; \ 1204 } while (0) 1205 1206 #define __vcpu_rmw_sys_reg(v, r, op, val) \ 1207 do { \ 1208 const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \ 1209 u64 __v = ctxt_sys_reg(ctxt, (r)); \ 1210 __v op (val); \ 1211 if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \ 1212 __v = kvm_vcpu_apply_reg_masks((v), (r), __v); \ 1213 \ 1214 ctxt_sys_reg(ctxt, (r)) = __v; \ 1215 } while (0) 1216 1217 #define __vcpu_sys_reg(v,r) \ 1218 ({ \ 1219 const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \ 1220 u64 __v = ctxt_sys_reg(ctxt, (r)); \ 1221 if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \ 1222 __v = kvm_vcpu_apply_reg_masks((v), (r), __v); \ 1223 __v; \ 1224 }) 1225 1226 u64 vcpu_read_sys_reg(const struct kvm_vcpu *, enum vcpu_sysreg); 1227 void vcpu_write_sys_reg(struct kvm_vcpu *, u64, enum vcpu_sysreg); 1228 1229 struct kvm_vm_stat { 1230 struct kvm_vm_stat_generic generic; 1231 }; 1232 1233 struct kvm_vcpu_stat { 1234 struct kvm_vcpu_stat_generic generic; 1235 u64 hvc_exit_stat; 1236 u64 wfe_exit_stat; 1237 u64 wfi_exit_stat; 1238 u64 mmio_exit_user; 1239 u64 mmio_exit_kernel; 1240 u64 signal_exits; 1241 u64 exits; 1242 }; 1243 1244 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); 1245 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); 1246 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 1247 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 1248 1249 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu); 1250 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices); 1251 1252 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu, 1253 struct kvm_vcpu_events *events); 1254 1255 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu, 1256 struct kvm_vcpu_events *events); 1257 1258 void kvm_arm_halt_guest(struct kvm *kvm); 1259 void kvm_arm_resume_guest(struct kvm *kvm); 1260 1261 #define vcpu_has_run_once(vcpu) (!!READ_ONCE((vcpu)->pid)) 1262 1263 #ifndef __KVM_NVHE_HYPERVISOR__ 1264 #define kvm_call_hyp_nvhe(f, ...) \ 1265 ({ \ 1266 struct arm_smccc_res res; \ 1267 \ 1268 arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f), \ 1269 ##__VA_ARGS__, &res); \ 1270 if (WARN_ON(res.a0 != SMCCC_RET_SUCCESS)) \ 1271 res.a1 = -EOPNOTSUPP; \ 1272 \ 1273 res.a1; \ 1274 }) 1275 1276 /* 1277 * The isb() below is there to guarantee the same behaviour on VHE as on !VHE, 1278 * where the eret to EL1 acts as a context synchronization event. 1279 */ 1280 #define kvm_call_hyp(f, ...) \ 1281 do { \ 1282 if (has_vhe()) { \ 1283 f(__VA_ARGS__); \ 1284 isb(); \ 1285 } else { \ 1286 kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 1287 } \ 1288 } while(0) 1289 1290 #define kvm_call_hyp_ret(f, ...) \ 1291 ({ \ 1292 typeof(f(__VA_ARGS__)) ret; \ 1293 \ 1294 if (has_vhe()) { \ 1295 ret = f(__VA_ARGS__); \ 1296 } else { \ 1297 ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 1298 } \ 1299 \ 1300 ret; \ 1301 }) 1302 #else /* __KVM_NVHE_HYPERVISOR__ */ 1303 #define kvm_call_hyp(f, ...) f(__VA_ARGS__) 1304 #define kvm_call_hyp_ret(f, ...) f(__VA_ARGS__) 1305 #define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__) 1306 #endif /* __KVM_NVHE_HYPERVISOR__ */ 1307 1308 int handle_exit(struct kvm_vcpu *vcpu, int exception_index); 1309 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index); 1310 1311 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu); 1312 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu); 1313 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu); 1314 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu); 1315 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu); 1316 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu); 1317 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu); 1318 1319 void kvm_sys_regs_create_debugfs(struct kvm *kvm); 1320 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu); 1321 1322 int __init kvm_sys_reg_table_init(void); 1323 struct sys_reg_desc; 1324 int __init populate_sysreg_config(const struct sys_reg_desc *sr, 1325 unsigned int idx); 1326 int __init populate_nv_trap_config(void); 1327 1328 void kvm_calculate_traps(struct kvm_vcpu *vcpu); 1329 1330 /* MMIO helpers */ 1331 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data); 1332 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len); 1333 1334 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu); 1335 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa); 1336 1337 /* 1338 * Returns true if a Performance Monitoring Interrupt (PMI), a.k.a. perf event, 1339 * arrived in guest context. For arm64, any event that arrives while a vCPU is 1340 * loaded is considered to be "in guest". 1341 */ 1342 static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu) 1343 { 1344 return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu; 1345 } 1346 1347 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu); 1348 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu); 1349 void kvm_update_stolen_time(struct kvm_vcpu *vcpu); 1350 1351 bool kvm_arm_pvtime_supported(void); 1352 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu, 1353 struct kvm_device_attr *attr); 1354 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu, 1355 struct kvm_device_attr *attr); 1356 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu, 1357 struct kvm_device_attr *attr); 1358 1359 extern unsigned int __ro_after_init kvm_arm_vmid_bits; 1360 int __init kvm_arm_vmid_alloc_init(void); 1361 void __init kvm_arm_vmid_alloc_free(void); 1362 void kvm_arm_vmid_update(struct kvm_vmid *kvm_vmid); 1363 void kvm_arm_vmid_clear_active(void); 1364 1365 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch) 1366 { 1367 vcpu_arch->steal.base = INVALID_GPA; 1368 } 1369 1370 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch) 1371 { 1372 return (vcpu_arch->steal.base != INVALID_GPA); 1373 } 1374 1375 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); 1376 1377 DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data); 1378 1379 /* 1380 * How we access per-CPU host data depends on the where we access it from, 1381 * and the mode we're in: 1382 * 1383 * - VHE and nVHE hypervisor bits use their locally defined instance 1384 * 1385 * - the rest of the kernel use either the VHE or nVHE one, depending on 1386 * the mode we're running in. 1387 * 1388 * Unless we're in protected mode, fully deprivileged, and the nVHE 1389 * per-CPU stuff is exclusively accessible to the protected EL2 code. 1390 * In this case, the EL1 code uses the *VHE* data as its private state 1391 * (which makes sense in a way as there shouldn't be any shared state 1392 * between the host and the hypervisor). 1393 * 1394 * Yes, this is all totally trivial. Shoot me now. 1395 */ 1396 #if defined(__KVM_NVHE_HYPERVISOR__) || defined(__KVM_VHE_HYPERVISOR__) 1397 #define host_data_ptr(f) (&this_cpu_ptr(&kvm_host_data)->f) 1398 #else 1399 #define host_data_ptr(f) \ 1400 (static_branch_unlikely(&kvm_protected_mode_initialized) ? \ 1401 &this_cpu_ptr(&kvm_host_data)->f : \ 1402 &this_cpu_ptr_hyp_sym(kvm_host_data)->f) 1403 #endif 1404 1405 #define host_data_test_flag(flag) \ 1406 (test_bit(KVM_HOST_DATA_FLAG_##flag, host_data_ptr(flags))) 1407 #define host_data_set_flag(flag) \ 1408 set_bit(KVM_HOST_DATA_FLAG_##flag, host_data_ptr(flags)) 1409 #define host_data_clear_flag(flag) \ 1410 clear_bit(KVM_HOST_DATA_FLAG_##flag, host_data_ptr(flags)) 1411 1412 /* Check whether the FP regs are owned by the guest */ 1413 static inline bool guest_owns_fp_regs(void) 1414 { 1415 return *host_data_ptr(fp_owner) == FP_STATE_GUEST_OWNED; 1416 } 1417 1418 /* Check whether the FP regs are owned by the host */ 1419 static inline bool host_owns_fp_regs(void) 1420 { 1421 return *host_data_ptr(fp_owner) == FP_STATE_HOST_OWNED; 1422 } 1423 1424 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt) 1425 { 1426 /* The host's MPIDR is immutable, so let's set it up at boot time */ 1427 ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr(); 1428 } 1429 1430 static inline bool kvm_system_needs_idmapped_vectors(void) 1431 { 1432 return cpus_have_final_cap(ARM64_SPECTRE_V3A); 1433 } 1434 1435 void kvm_init_host_debug_data(void); 1436 void kvm_debug_init_vhe(void); 1437 void kvm_vcpu_load_debug(struct kvm_vcpu *vcpu); 1438 void kvm_vcpu_put_debug(struct kvm_vcpu *vcpu); 1439 void kvm_debug_set_guest_ownership(struct kvm_vcpu *vcpu); 1440 void kvm_debug_handle_oslar(struct kvm_vcpu *vcpu, u64 val); 1441 1442 #define kvm_vcpu_os_lock_enabled(vcpu) \ 1443 (!!(__vcpu_sys_reg(vcpu, OSLSR_EL1) & OSLSR_EL1_OSLK)) 1444 1445 #define kvm_debug_regs_in_use(vcpu) \ 1446 ((vcpu)->arch.debug_owner != VCPU_DEBUG_FREE) 1447 #define kvm_host_owns_debug_regs(vcpu) \ 1448 ((vcpu)->arch.debug_owner == VCPU_DEBUG_HOST_OWNED) 1449 #define kvm_guest_owns_debug_regs(vcpu) \ 1450 ((vcpu)->arch.debug_owner == VCPU_DEBUG_GUEST_OWNED) 1451 1452 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, 1453 struct kvm_device_attr *attr); 1454 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, 1455 struct kvm_device_attr *attr); 1456 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, 1457 struct kvm_device_attr *attr); 1458 1459 int kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm, 1460 struct kvm_arm_copy_mte_tags *copy_tags); 1461 int kvm_vm_ioctl_set_counter_offset(struct kvm *kvm, 1462 struct kvm_arm_counter_offset *offset); 1463 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, 1464 struct reg_mask_range *range); 1465 1466 /* Guest/host FPSIMD coordination helpers */ 1467 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu); 1468 void kvm_arch_vcpu_ctxflush_fp(struct kvm_vcpu *vcpu); 1469 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu); 1470 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu); 1471 1472 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr) 1473 { 1474 return (!has_vhe() && attr->exclude_host); 1475 } 1476 1477 #ifdef CONFIG_KVM 1478 void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr); 1479 void kvm_clr_pmu_events(u64 clr); 1480 bool kvm_set_pmuserenr(u64 val); 1481 void kvm_enable_trbe(void); 1482 void kvm_disable_trbe(void); 1483 void kvm_tracing_set_el1_configuration(u64 trfcr_while_in_guest); 1484 #else 1485 static inline void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr) {} 1486 static inline void kvm_clr_pmu_events(u64 clr) {} 1487 static inline bool kvm_set_pmuserenr(u64 val) 1488 { 1489 return false; 1490 } 1491 static inline void kvm_enable_trbe(void) {} 1492 static inline void kvm_disable_trbe(void) {} 1493 static inline void kvm_tracing_set_el1_configuration(u64 trfcr_while_in_guest) {} 1494 #endif 1495 1496 void kvm_vcpu_load_vhe(struct kvm_vcpu *vcpu); 1497 void kvm_vcpu_put_vhe(struct kvm_vcpu *vcpu); 1498 1499 int __init kvm_set_ipa_limit(void); 1500 u32 kvm_get_pa_bits(struct kvm *kvm); 1501 1502 #define __KVM_HAVE_ARCH_VM_ALLOC 1503 struct kvm *kvm_arch_alloc_vm(void); 1504 1505 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS 1506 1507 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS_RANGE 1508 1509 #define kvm_vm_is_protected(kvm) (is_protected_kvm_enabled() && (kvm)->arch.pkvm.is_protected) 1510 1511 #define vcpu_is_protected(vcpu) kvm_vm_is_protected((vcpu)->kvm) 1512 1513 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature); 1514 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu); 1515 1516 #define kvm_arm_vcpu_sve_finalized(vcpu) vcpu_get_flag(vcpu, VCPU_SVE_FINALIZED) 1517 1518 #define kvm_has_mte(kvm) \ 1519 (system_supports_mte() && \ 1520 test_bit(KVM_ARCH_FLAG_MTE_ENABLED, &(kvm)->arch.flags)) 1521 1522 #define kvm_supports_32bit_el0() \ 1523 (system_supports_32bit_el0() && \ 1524 !static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1525 1526 #define kvm_vm_has_ran_once(kvm) \ 1527 (test_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &(kvm)->arch.flags)) 1528 1529 static inline bool __vcpu_has_feature(const struct kvm_arch *ka, int feature) 1530 { 1531 return test_bit(feature, ka->vcpu_features); 1532 } 1533 1534 #define kvm_vcpu_has_feature(k, f) __vcpu_has_feature(&(k)->arch, (f)) 1535 #define vcpu_has_feature(v, f) __vcpu_has_feature(&(v)->kvm->arch, (f)) 1536 1537 #define kvm_vcpu_initialized(v) vcpu_get_flag(v, VCPU_INITIALIZED) 1538 1539 int kvm_trng_call(struct kvm_vcpu *vcpu); 1540 #ifdef CONFIG_KVM 1541 extern phys_addr_t hyp_mem_base; 1542 extern phys_addr_t hyp_mem_size; 1543 void __init kvm_hyp_reserve(void); 1544 #else 1545 static inline void kvm_hyp_reserve(void) { } 1546 #endif 1547 1548 void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu); 1549 bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu); 1550 1551 static inline u64 *__vm_id_reg(struct kvm_arch *ka, u32 reg) 1552 { 1553 switch (reg) { 1554 case sys_reg(3, 0, 0, 1, 0) ... sys_reg(3, 0, 0, 7, 7): 1555 return &ka->id_regs[IDREG_IDX(reg)]; 1556 case SYS_CTR_EL0: 1557 return &ka->ctr_el0; 1558 case SYS_MIDR_EL1: 1559 return &ka->midr_el1; 1560 case SYS_REVIDR_EL1: 1561 return &ka->revidr_el1; 1562 case SYS_AIDR_EL1: 1563 return &ka->aidr_el1; 1564 default: 1565 WARN_ON_ONCE(1); 1566 return NULL; 1567 } 1568 } 1569 1570 #define kvm_read_vm_id_reg(kvm, reg) \ 1571 ({ u64 __val = *__vm_id_reg(&(kvm)->arch, reg); __val; }) 1572 1573 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val); 1574 1575 #define __expand_field_sign_unsigned(id, fld, val) \ 1576 ((u64)SYS_FIELD_VALUE(id, fld, val)) 1577 1578 #define __expand_field_sign_signed(id, fld, val) \ 1579 ({ \ 1580 u64 __val = SYS_FIELD_VALUE(id, fld, val); \ 1581 sign_extend64(__val, id##_##fld##_WIDTH - 1); \ 1582 }) 1583 1584 #define get_idreg_field_unsigned(kvm, id, fld) \ 1585 ({ \ 1586 u64 __val = kvm_read_vm_id_reg((kvm), SYS_##id); \ 1587 FIELD_GET(id##_##fld##_MASK, __val); \ 1588 }) 1589 1590 #define get_idreg_field_signed(kvm, id, fld) \ 1591 ({ \ 1592 u64 __val = get_idreg_field_unsigned(kvm, id, fld); \ 1593 sign_extend64(__val, id##_##fld##_WIDTH - 1); \ 1594 }) 1595 1596 #define get_idreg_field_enum(kvm, id, fld) \ 1597 get_idreg_field_unsigned(kvm, id, fld) 1598 1599 #define kvm_cmp_feat_signed(kvm, id, fld, op, limit) \ 1600 (get_idreg_field_signed((kvm), id, fld) op __expand_field_sign_signed(id, fld, limit)) 1601 1602 #define kvm_cmp_feat_unsigned(kvm, id, fld, op, limit) \ 1603 (get_idreg_field_unsigned((kvm), id, fld) op __expand_field_sign_unsigned(id, fld, limit)) 1604 1605 #define kvm_cmp_feat(kvm, id, fld, op, limit) \ 1606 (id##_##fld##_SIGNED ? \ 1607 kvm_cmp_feat_signed(kvm, id, fld, op, limit) : \ 1608 kvm_cmp_feat_unsigned(kvm, id, fld, op, limit)) 1609 1610 #define __kvm_has_feat(kvm, id, fld, limit) \ 1611 kvm_cmp_feat(kvm, id, fld, >=, limit) 1612 1613 #define kvm_has_feat(kvm, ...) __kvm_has_feat(kvm, __VA_ARGS__) 1614 1615 #define __kvm_has_feat_enum(kvm, id, fld, val) \ 1616 kvm_cmp_feat_unsigned(kvm, id, fld, ==, val) 1617 1618 #define kvm_has_feat_enum(kvm, ...) __kvm_has_feat_enum(kvm, __VA_ARGS__) 1619 1620 #define kvm_has_feat_range(kvm, id, fld, min, max) \ 1621 (kvm_cmp_feat(kvm, id, fld, >=, min) && \ 1622 kvm_cmp_feat(kvm, id, fld, <=, max)) 1623 1624 /* Check for a given level of PAuth support */ 1625 #define kvm_has_pauth(k, l) \ 1626 ({ \ 1627 bool pa, pi, pa3; \ 1628 \ 1629 pa = kvm_has_feat((k), ID_AA64ISAR1_EL1, APA, l); \ 1630 pa &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPA, IMP); \ 1631 pi = kvm_has_feat((k), ID_AA64ISAR1_EL1, API, l); \ 1632 pi &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPI, IMP); \ 1633 pa3 = kvm_has_feat((k), ID_AA64ISAR2_EL1, APA3, l); \ 1634 pa3 &= kvm_has_feat((k), ID_AA64ISAR2_EL1, GPA3, IMP); \ 1635 \ 1636 (pa + pi + pa3) == 1; \ 1637 }) 1638 1639 #define kvm_has_fpmr(k) \ 1640 (system_supports_fpmr() && \ 1641 kvm_has_feat((k), ID_AA64PFR2_EL1, FPMR, IMP)) 1642 1643 #define kvm_has_tcr2(k) \ 1644 (kvm_has_feat((k), ID_AA64MMFR3_EL1, TCRX, IMP)) 1645 1646 #define kvm_has_s1pie(k) \ 1647 (kvm_has_feat((k), ID_AA64MMFR3_EL1, S1PIE, IMP)) 1648 1649 #define kvm_has_s1poe(k) \ 1650 (system_supports_poe() && \ 1651 kvm_has_feat((k), ID_AA64MMFR3_EL1, S1POE, IMP)) 1652 1653 #define kvm_has_ras(k) \ 1654 (kvm_has_feat((k), ID_AA64PFR0_EL1, RAS, IMP)) 1655 1656 #define kvm_has_sctlr2(k) \ 1657 (kvm_has_feat((k), ID_AA64MMFR3_EL1, SCTLRX, IMP)) 1658 1659 static inline bool kvm_arch_has_irq_bypass(void) 1660 { 1661 return true; 1662 } 1663 1664 void compute_fgu(struct kvm *kvm, enum fgt_group_id fgt); 1665 struct resx get_reg_fixed_bits(struct kvm *kvm, enum vcpu_sysreg reg); 1666 void check_feature_map(void); 1667 void kvm_vcpu_load_fgt(struct kvm_vcpu *vcpu); 1668 1669 static __always_inline enum fgt_group_id __fgt_reg_to_group_id(enum vcpu_sysreg reg) 1670 { 1671 switch (reg) { 1672 case HFGRTR_EL2: 1673 case HFGWTR_EL2: 1674 return HFGRTR_GROUP; 1675 case HFGITR_EL2: 1676 return HFGITR_GROUP; 1677 case HDFGRTR_EL2: 1678 case HDFGWTR_EL2: 1679 return HDFGRTR_GROUP; 1680 case HAFGRTR_EL2: 1681 return HAFGRTR_GROUP; 1682 case HFGRTR2_EL2: 1683 case HFGWTR2_EL2: 1684 return HFGRTR2_GROUP; 1685 case HFGITR2_EL2: 1686 return HFGITR2_GROUP; 1687 case HDFGRTR2_EL2: 1688 case HDFGWTR2_EL2: 1689 return HDFGRTR2_GROUP; 1690 case ICH_HFGRTR_EL2: 1691 case ICH_HFGWTR_EL2: 1692 return ICH_HFGRTR_GROUP; 1693 case ICH_HFGITR_EL2: 1694 return ICH_HFGITR_GROUP; 1695 default: 1696 BUILD_BUG_ON(1); 1697 } 1698 } 1699 1700 #define vcpu_fgt(vcpu, reg) \ 1701 ({ \ 1702 enum fgt_group_id id = __fgt_reg_to_group_id(reg); \ 1703 u64 *p; \ 1704 switch (reg) { \ 1705 case HFGWTR_EL2: \ 1706 case HDFGWTR_EL2: \ 1707 case HFGWTR2_EL2: \ 1708 case HDFGWTR2_EL2: \ 1709 case ICH_HFGWTR_EL2: \ 1710 p = &(vcpu)->arch.fgt[id].w; \ 1711 break; \ 1712 default: \ 1713 p = &(vcpu)->arch.fgt[id].r; \ 1714 break; \ 1715 } \ 1716 \ 1717 p; \ 1718 }) 1719 1720 long kvm_get_cap_for_kvm_ioctl(unsigned int ioctl, long *ext); 1721 1722 #endif /* __ARM64_KVM_HOST_H__ */ 1723