1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/asm/kvm_host.h: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 */ 10 11 #ifndef __ARM64_KVM_HOST_H__ 12 #define __ARM64_KVM_HOST_H__ 13 14 #include <linux/arm-smccc.h> 15 #include <linux/bitmap.h> 16 #include <linux/types.h> 17 #include <linux/jump_label.h> 18 #include <linux/kvm_types.h> 19 #include <linux/maple_tree.h> 20 #include <linux/percpu.h> 21 #include <linux/psci.h> 22 #include <asm/arch_gicv3.h> 23 #include <asm/barrier.h> 24 #include <asm/cpufeature.h> 25 #include <asm/cputype.h> 26 #include <asm/daifflags.h> 27 #include <asm/fpsimd.h> 28 #include <asm/kvm.h> 29 #include <asm/kvm_asm.h> 30 #include <asm/vncr_mapping.h> 31 32 #define __KVM_HAVE_ARCH_INTC_INITIALIZED 33 34 #define KVM_HALT_POLL_NS_DEFAULT 500000 35 36 #include <kvm/arm_vgic.h> 37 #include <kvm/arm_arch_timer.h> 38 #include <kvm/arm_pmu.h> 39 40 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS 41 42 #define KVM_VCPU_MAX_FEATURES 9 43 #define KVM_VCPU_VALID_FEATURES (BIT(KVM_VCPU_MAX_FEATURES) - 1) 44 45 #define KVM_REQ_SLEEP \ 46 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 47 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1) 48 #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2) 49 #define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(3) 50 #define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4) 51 #define KVM_REQ_RELOAD_PMU KVM_ARCH_REQ(5) 52 #define KVM_REQ_SUSPEND KVM_ARCH_REQ(6) 53 #define KVM_REQ_RESYNC_PMU_EL0 KVM_ARCH_REQ(7) 54 #define KVM_REQ_NESTED_S2_UNMAP KVM_ARCH_REQ(8) 55 #define KVM_REQ_GUEST_HYP_IRQ_PENDING KVM_ARCH_REQ(9) 56 #define KVM_REQ_MAP_L1_VNCR_EL2 KVM_ARCH_REQ(10) 57 #define KVM_REQ_VGIC_PROCESS_UPDATE KVM_ARCH_REQ(11) 58 59 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \ 60 KVM_DIRTY_LOG_INITIALLY_SET) 61 62 #define KVM_HAVE_MMU_RWLOCK 63 64 /* 65 * Mode of operation configurable with kvm-arm.mode early param. 66 * See Documentation/admin-guide/kernel-parameters.txt for more information. 67 */ 68 enum kvm_mode { 69 KVM_MODE_DEFAULT, 70 KVM_MODE_PROTECTED, 71 KVM_MODE_NV, 72 KVM_MODE_NONE, 73 }; 74 #ifdef CONFIG_KVM 75 enum kvm_mode kvm_get_mode(void); 76 #else 77 static inline enum kvm_mode kvm_get_mode(void) { return KVM_MODE_NONE; }; 78 #endif 79 80 extern unsigned int __ro_after_init kvm_sve_max_vl; 81 extern unsigned int __ro_after_init kvm_host_sve_max_vl; 82 int __init kvm_arm_init_sve(void); 83 84 u32 __attribute_const__ kvm_target_cpu(void); 85 void kvm_reset_vcpu(struct kvm_vcpu *vcpu); 86 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu); 87 88 struct kvm_hyp_memcache { 89 phys_addr_t head; 90 unsigned long nr_pages; 91 struct pkvm_mapping *mapping; /* only used from EL1 */ 92 93 #define HYP_MEMCACHE_ACCOUNT_STAGE2 BIT(1) 94 unsigned long flags; 95 }; 96 97 static inline void push_hyp_memcache(struct kvm_hyp_memcache *mc, 98 phys_addr_t *p, 99 phys_addr_t (*to_pa)(void *virt)) 100 { 101 *p = mc->head; 102 mc->head = to_pa(p); 103 mc->nr_pages++; 104 } 105 106 static inline void *pop_hyp_memcache(struct kvm_hyp_memcache *mc, 107 void *(*to_va)(phys_addr_t phys)) 108 { 109 phys_addr_t *p = to_va(mc->head & PAGE_MASK); 110 111 if (!mc->nr_pages) 112 return NULL; 113 114 mc->head = *p; 115 mc->nr_pages--; 116 117 return p; 118 } 119 120 static inline int __topup_hyp_memcache(struct kvm_hyp_memcache *mc, 121 unsigned long min_pages, 122 void *(*alloc_fn)(void *arg), 123 phys_addr_t (*to_pa)(void *virt), 124 void *arg) 125 { 126 while (mc->nr_pages < min_pages) { 127 phys_addr_t *p = alloc_fn(arg); 128 129 if (!p) 130 return -ENOMEM; 131 push_hyp_memcache(mc, p, to_pa); 132 } 133 134 return 0; 135 } 136 137 static inline void __free_hyp_memcache(struct kvm_hyp_memcache *mc, 138 void (*free_fn)(void *virt, void *arg), 139 void *(*to_va)(phys_addr_t phys), 140 void *arg) 141 { 142 while (mc->nr_pages) 143 free_fn(pop_hyp_memcache(mc, to_va), arg); 144 } 145 146 void free_hyp_memcache(struct kvm_hyp_memcache *mc); 147 int topup_hyp_memcache(struct kvm_hyp_memcache *mc, unsigned long min_pages); 148 149 struct kvm_vmid { 150 atomic64_t id; 151 }; 152 153 struct kvm_s2_mmu { 154 struct kvm_vmid vmid; 155 156 /* 157 * stage2 entry level table 158 * 159 * Two kvm_s2_mmu structures in the same VM can point to the same 160 * pgd here. This happens when running a guest using a 161 * translation regime that isn't affected by its own stage-2 162 * translation, such as a non-VHE hypervisor running at vEL2, or 163 * for vEL1/EL0 with vHCR_EL2.VM == 0. In that case, we use the 164 * canonical stage-2 page tables. 165 */ 166 phys_addr_t pgd_phys; 167 struct kvm_pgtable *pgt; 168 169 /* 170 * VTCR value used on the host. For a non-NV guest (or a NV 171 * guest that runs in a context where its own S2 doesn't 172 * apply), its T0SZ value reflects that of the IPA size. 173 * 174 * For a shadow S2 MMU, T0SZ reflects the PARange exposed to 175 * the guest. 176 */ 177 u64 vtcr; 178 179 /* The last vcpu id that ran on each physical CPU */ 180 int __percpu *last_vcpu_ran; 181 182 #define KVM_ARM_EAGER_SPLIT_CHUNK_SIZE_DEFAULT 0 183 /* 184 * Memory cache used to split 185 * KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE worth of huge pages. It 186 * is used to allocate stage2 page tables while splitting huge 187 * pages. The choice of KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE 188 * influences both the capacity of the split page cache, and 189 * how often KVM reschedules. Be wary of raising CHUNK_SIZE 190 * too high. 191 * 192 * Protected by kvm->slots_lock. 193 */ 194 struct kvm_mmu_memory_cache split_page_cache; 195 uint64_t split_page_chunk_size; 196 197 struct kvm_arch *arch; 198 199 /* 200 * For a shadow stage-2 MMU, the virtual vttbr used by the 201 * host to parse the guest S2. 202 * This either contains: 203 * - the virtual VTTBR programmed by the guest hypervisor with 204 * CnP cleared 205 * - The value 1 (VMID=0, BADDR=0, CnP=1) if invalid 206 * 207 * We also cache the full VTCR which gets used for TLB invalidation, 208 * taking the ARM ARM's "Any of the bits in VTCR_EL2 are permitted 209 * to be cached in a TLB" to the letter. 210 */ 211 u64 tlb_vttbr; 212 u64 tlb_vtcr; 213 214 /* 215 * true when this represents a nested context where virtual 216 * HCR_EL2.VM == 1 217 */ 218 bool nested_stage2_enabled; 219 220 /* 221 * true when this MMU needs to be unmapped before being used for a new 222 * purpose. 223 */ 224 bool pending_unmap; 225 226 /* 227 * 0: Nobody is currently using this, check vttbr for validity 228 * >0: Somebody is actively using this. 229 */ 230 atomic_t refcnt; 231 }; 232 233 struct kvm_arch_memory_slot { 234 }; 235 236 /** 237 * struct kvm_smccc_features: Descriptor of the hypercall services exposed to the guests 238 * 239 * @std_bmap: Bitmap of standard secure service calls 240 * @std_hyp_bmap: Bitmap of standard hypervisor service calls 241 * @vendor_hyp_bmap: Bitmap of vendor specific hypervisor service calls 242 */ 243 struct kvm_smccc_features { 244 unsigned long std_bmap; 245 unsigned long std_hyp_bmap; 246 unsigned long vendor_hyp_bmap; /* Function numbers 0-63 */ 247 unsigned long vendor_hyp_bmap_2; /* Function numbers 64-127 */ 248 }; 249 250 typedef unsigned int pkvm_handle_t; 251 252 struct kvm_protected_vm { 253 pkvm_handle_t handle; 254 struct kvm_hyp_memcache teardown_mc; 255 struct kvm_hyp_memcache stage2_teardown_mc; 256 bool is_protected; 257 bool is_created; 258 }; 259 260 struct kvm_mpidr_data { 261 u64 mpidr_mask; 262 DECLARE_FLEX_ARRAY(u16, cmpidr_to_idx); 263 }; 264 265 static inline u16 kvm_mpidr_index(struct kvm_mpidr_data *data, u64 mpidr) 266 { 267 unsigned long index = 0, mask = data->mpidr_mask; 268 unsigned long aff = mpidr & MPIDR_HWID_BITMASK; 269 270 bitmap_gather(&index, &aff, &mask, fls(mask)); 271 272 return index; 273 } 274 275 struct kvm_sysreg_masks; 276 277 enum fgt_group_id { 278 __NO_FGT_GROUP__, 279 HFGRTR_GROUP, 280 HFGWTR_GROUP = HFGRTR_GROUP, 281 HDFGRTR_GROUP, 282 HDFGWTR_GROUP = HDFGRTR_GROUP, 283 HFGITR_GROUP, 284 HAFGRTR_GROUP, 285 HFGRTR2_GROUP, 286 HFGWTR2_GROUP = HFGRTR2_GROUP, 287 HDFGRTR2_GROUP, 288 HDFGWTR2_GROUP = HDFGRTR2_GROUP, 289 HFGITR2_GROUP, 290 291 /* Must be last */ 292 __NR_FGT_GROUP_IDS__ 293 }; 294 295 struct kvm_arch { 296 struct kvm_s2_mmu mmu; 297 298 /* 299 * Fine-Grained UNDEF, mimicking the FGT layout defined by the 300 * architecture. We track them globally, as we present the 301 * same feature-set to all vcpus. 302 * 303 * Index 0 is currently spare. 304 */ 305 u64 fgu[__NR_FGT_GROUP_IDS__]; 306 307 /* 308 * Stage 2 paging state for VMs with nested S2 using a virtual 309 * VMID. 310 */ 311 struct kvm_s2_mmu *nested_mmus; 312 size_t nested_mmus_size; 313 int nested_mmus_next; 314 315 /* Interrupt controller */ 316 struct vgic_dist vgic; 317 318 /* Timers */ 319 struct arch_timer_vm_data timer_data; 320 321 /* Mandated version of PSCI */ 322 u32 psci_version; 323 324 /* Protects VM-scoped configuration data */ 325 struct mutex config_lock; 326 327 /* 328 * If we encounter a data abort without valid instruction syndrome 329 * information, report this to user space. User space can (and 330 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is 331 * supported. 332 */ 333 #define KVM_ARCH_FLAG_RETURN_NISV_IO_ABORT_TO_USER 0 334 /* Memory Tagging Extension enabled for the guest */ 335 #define KVM_ARCH_FLAG_MTE_ENABLED 1 336 /* At least one vCPU has ran in the VM */ 337 #define KVM_ARCH_FLAG_HAS_RAN_ONCE 2 338 /* The vCPU feature set for the VM is configured */ 339 #define KVM_ARCH_FLAG_VCPU_FEATURES_CONFIGURED 3 340 /* PSCI SYSTEM_SUSPEND enabled for the guest */ 341 #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED 4 342 /* VM counter offset */ 343 #define KVM_ARCH_FLAG_VM_COUNTER_OFFSET 5 344 /* Timer PPIs made immutable */ 345 #define KVM_ARCH_FLAG_TIMER_PPIS_IMMUTABLE 6 346 /* Initial ID reg values loaded */ 347 #define KVM_ARCH_FLAG_ID_REGS_INITIALIZED 7 348 /* Fine-Grained UNDEF initialised */ 349 #define KVM_ARCH_FLAG_FGU_INITIALIZED 8 350 /* SVE exposed to guest */ 351 #define KVM_ARCH_FLAG_GUEST_HAS_SVE 9 352 /* MIDR_EL1, REVIDR_EL1, and AIDR_EL1 are writable from userspace */ 353 #define KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS 10 354 /* Unhandled SEAs are taken to userspace */ 355 #define KVM_ARCH_FLAG_EXIT_SEA 11 356 unsigned long flags; 357 358 /* VM-wide vCPU feature set */ 359 DECLARE_BITMAP(vcpu_features, KVM_VCPU_MAX_FEATURES); 360 361 /* MPIDR to vcpu index mapping, optional */ 362 struct kvm_mpidr_data *mpidr_data; 363 364 /* 365 * VM-wide PMU filter, implemented as a bitmap and big enough for 366 * up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+). 367 */ 368 unsigned long *pmu_filter; 369 struct arm_pmu *arm_pmu; 370 371 cpumask_var_t supported_cpus; 372 373 /* Maximum number of counters for the guest */ 374 u8 nr_pmu_counters; 375 376 /* Iterator for idreg debugfs */ 377 u8 idreg_debugfs_iter; 378 379 /* Hypercall features firmware registers' descriptor */ 380 struct kvm_smccc_features smccc_feat; 381 struct maple_tree smccc_filter; 382 383 /* 384 * Emulated CPU ID registers per VM 385 * (Op0, Op1, CRn, CRm, Op2) of the ID registers to be saved in it 386 * is (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8. 387 * 388 * These emulated idregs are VM-wide, but accessed from the context of a vCPU. 389 * Atomic access to multiple idregs are guarded by kvm_arch.config_lock. 390 */ 391 #define IDREG_IDX(id) (((sys_reg_CRm(id) - 1) << 3) | sys_reg_Op2(id)) 392 #define KVM_ARM_ID_REG_NUM (IDREG_IDX(sys_reg(3, 0, 0, 7, 7)) + 1) 393 u64 id_regs[KVM_ARM_ID_REG_NUM]; 394 395 u64 midr_el1; 396 u64 revidr_el1; 397 u64 aidr_el1; 398 u64 ctr_el0; 399 400 /* Masks for VNCR-backed and general EL2 sysregs */ 401 struct kvm_sysreg_masks *sysreg_masks; 402 403 /* Count the number of VNCR_EL2 currently mapped */ 404 atomic_t vncr_map_count; 405 406 /* 407 * For an untrusted host VM, 'pkvm.handle' is used to lookup 408 * the associated pKVM instance in the hypervisor. 409 */ 410 struct kvm_protected_vm pkvm; 411 }; 412 413 struct kvm_vcpu_fault_info { 414 u64 esr_el2; /* Hyp Syndrom Register */ 415 u64 far_el2; /* Hyp Fault Address Register */ 416 u64 hpfar_el2; /* Hyp IPA Fault Address Register */ 417 u64 disr_el1; /* Deferred [SError] Status Register */ 418 }; 419 420 /* 421 * VNCR() just places the VNCR_capable registers in the enum after 422 * __VNCR_START__, and the value (after correction) to be an 8-byte offset 423 * from the VNCR base. As we don't require the enum to be otherwise ordered, 424 * we need the terrible hack below to ensure that we correctly size the 425 * sys_regs array, no matter what. 426 * 427 * The __MAX__ macro has been lifted from Sean Eron Anderson's wonderful 428 * treasure trove of bit hacks: 429 * https://graphics.stanford.edu/~seander/bithacks.html#IntegerMinOrMax 430 */ 431 #define __MAX__(x,y) ((x) ^ (((x) ^ (y)) & -((x) < (y)))) 432 #define VNCR(r) \ 433 __before_##r, \ 434 r = __VNCR_START__ + ((VNCR_ ## r) / 8), \ 435 __after_##r = __MAX__(__before_##r - 1, r) 436 437 #define MARKER(m) \ 438 m, __after_##m = m - 1 439 440 enum vcpu_sysreg { 441 __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ 442 MPIDR_EL1, /* MultiProcessor Affinity Register */ 443 CLIDR_EL1, /* Cache Level ID Register */ 444 CSSELR_EL1, /* Cache Size Selection Register */ 445 TPIDR_EL0, /* Thread ID, User R/W */ 446 TPIDRRO_EL0, /* Thread ID, User R/O */ 447 TPIDR_EL1, /* Thread ID, Privileged */ 448 CNTKCTL_EL1, /* Timer Control Register (EL1) */ 449 PAR_EL1, /* Physical Address Register */ 450 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ 451 OSLSR_EL1, /* OS Lock Status Register */ 452 DISR_EL1, /* Deferred Interrupt Status Register */ 453 454 /* Performance Monitors Registers */ 455 PMCR_EL0, /* Control Register */ 456 PMSELR_EL0, /* Event Counter Selection Register */ 457 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */ 458 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30, 459 PMCCNTR_EL0, /* Cycle Counter Register */ 460 PMEVTYPER0_EL0, /* Event Type Register (0-30) */ 461 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30, 462 PMCCFILTR_EL0, /* Cycle Count Filter Register */ 463 PMCNTENSET_EL0, /* Count Enable Set Register */ 464 PMINTENSET_EL1, /* Interrupt Enable Set Register */ 465 PMOVSSET_EL0, /* Overflow Flag Status Set Register */ 466 PMUSERENR_EL0, /* User Enable Register */ 467 468 /* Pointer Authentication Registers in a strict increasing order. */ 469 APIAKEYLO_EL1, 470 APIAKEYHI_EL1, 471 APIBKEYLO_EL1, 472 APIBKEYHI_EL1, 473 APDAKEYLO_EL1, 474 APDAKEYHI_EL1, 475 APDBKEYLO_EL1, 476 APDBKEYHI_EL1, 477 APGAKEYLO_EL1, 478 APGAKEYHI_EL1, 479 480 /* Memory Tagging Extension registers */ 481 RGSR_EL1, /* Random Allocation Tag Seed Register */ 482 GCR_EL1, /* Tag Control Register */ 483 TFSRE0_EL1, /* Tag Fault Status Register (EL0) */ 484 485 POR_EL0, /* Permission Overlay Register 0 (EL0) */ 486 487 /* FP/SIMD/SVE */ 488 SVCR, 489 FPMR, 490 491 /* 32bit specific registers. */ 492 DACR32_EL2, /* Domain Access Control Register */ 493 IFSR32_EL2, /* Instruction Fault Status Register */ 494 FPEXC32_EL2, /* Floating-Point Exception Control Register */ 495 DBGVCR32_EL2, /* Debug Vector Catch Register */ 496 497 /* EL2 registers */ 498 SCTLR_EL2, /* System Control Register (EL2) */ 499 ACTLR_EL2, /* Auxiliary Control Register (EL2) */ 500 CPTR_EL2, /* Architectural Feature Trap Register (EL2) */ 501 HACR_EL2, /* Hypervisor Auxiliary Control Register */ 502 ZCR_EL2, /* SVE Control Register (EL2) */ 503 TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */ 504 TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */ 505 TCR_EL2, /* Translation Control Register (EL2) */ 506 PIRE0_EL2, /* Permission Indirection Register 0 (EL2) */ 507 PIR_EL2, /* Permission Indirection Register 1 (EL2) */ 508 POR_EL2, /* Permission Overlay Register 2 (EL2) */ 509 SPSR_EL2, /* EL2 saved program status register */ 510 ELR_EL2, /* EL2 exception link register */ 511 AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */ 512 AFSR1_EL2, /* Auxiliary Fault Status Register 1 (EL2) */ 513 ESR_EL2, /* Exception Syndrome Register (EL2) */ 514 FAR_EL2, /* Fault Address Register (EL2) */ 515 HPFAR_EL2, /* Hypervisor IPA Fault Address Register */ 516 MAIR_EL2, /* Memory Attribute Indirection Register (EL2) */ 517 AMAIR_EL2, /* Auxiliary Memory Attribute Indirection Register (EL2) */ 518 VBAR_EL2, /* Vector Base Address Register (EL2) */ 519 RVBAR_EL2, /* Reset Vector Base Address Register */ 520 CONTEXTIDR_EL2, /* Context ID Register (EL2) */ 521 SP_EL2, /* EL2 Stack Pointer */ 522 CNTHP_CTL_EL2, 523 CNTHP_CVAL_EL2, 524 CNTHV_CTL_EL2, 525 CNTHV_CVAL_EL2, 526 527 /* Anything from this can be RES0/RES1 sanitised */ 528 MARKER(__SANITISED_REG_START__), 529 TCR2_EL2, /* Extended Translation Control Register (EL2) */ 530 SCTLR2_EL2, /* System Control Register 2 (EL2) */ 531 MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */ 532 CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */ 533 534 /* Any VNCR-capable reg goes after this point */ 535 MARKER(__VNCR_START__), 536 537 VNCR(SCTLR_EL1),/* System Control Register */ 538 VNCR(ACTLR_EL1),/* Auxiliary Control Register */ 539 VNCR(CPACR_EL1),/* Coprocessor Access Control */ 540 VNCR(ZCR_EL1), /* SVE Control */ 541 VNCR(TTBR0_EL1),/* Translation Table Base Register 0 */ 542 VNCR(TTBR1_EL1),/* Translation Table Base Register 1 */ 543 VNCR(TCR_EL1), /* Translation Control Register */ 544 VNCR(TCR2_EL1), /* Extended Translation Control Register */ 545 VNCR(SCTLR2_EL1), /* System Control Register 2 */ 546 VNCR(ESR_EL1), /* Exception Syndrome Register */ 547 VNCR(AFSR0_EL1),/* Auxiliary Fault Status Register 0 */ 548 VNCR(AFSR1_EL1),/* Auxiliary Fault Status Register 1 */ 549 VNCR(FAR_EL1), /* Fault Address Register */ 550 VNCR(MAIR_EL1), /* Memory Attribute Indirection Register */ 551 VNCR(VBAR_EL1), /* Vector Base Address Register */ 552 VNCR(CONTEXTIDR_EL1), /* Context ID Register */ 553 VNCR(AMAIR_EL1),/* Aux Memory Attribute Indirection Register */ 554 VNCR(MDSCR_EL1),/* Monitor Debug System Control Register */ 555 VNCR(ELR_EL1), 556 VNCR(SP_EL1), 557 VNCR(SPSR_EL1), 558 VNCR(TFSR_EL1), /* Tag Fault Status Register (EL1) */ 559 VNCR(VPIDR_EL2),/* Virtualization Processor ID Register */ 560 VNCR(VMPIDR_EL2),/* Virtualization Multiprocessor ID Register */ 561 VNCR(HCR_EL2), /* Hypervisor Configuration Register */ 562 VNCR(HSTR_EL2), /* Hypervisor System Trap Register */ 563 VNCR(VTTBR_EL2),/* Virtualization Translation Table Base Register */ 564 VNCR(VTCR_EL2), /* Virtualization Translation Control Register */ 565 VNCR(TPIDR_EL2),/* EL2 Software Thread ID Register */ 566 VNCR(HCRX_EL2), /* Extended Hypervisor Configuration Register */ 567 568 /* Permission Indirection Extension registers */ 569 VNCR(PIR_EL1), /* Permission Indirection Register 1 (EL1) */ 570 VNCR(PIRE0_EL1), /* Permission Indirection Register 0 (EL1) */ 571 572 VNCR(POR_EL1), /* Permission Overlay Register 1 (EL1) */ 573 574 /* FEAT_RAS registers */ 575 VNCR(VDISR_EL2), 576 VNCR(VSESR_EL2), 577 578 VNCR(HFGRTR_EL2), 579 VNCR(HFGWTR_EL2), 580 VNCR(HFGITR_EL2), 581 VNCR(HDFGRTR_EL2), 582 VNCR(HDFGWTR_EL2), 583 VNCR(HAFGRTR_EL2), 584 VNCR(HFGRTR2_EL2), 585 VNCR(HFGWTR2_EL2), 586 VNCR(HFGITR2_EL2), 587 VNCR(HDFGRTR2_EL2), 588 VNCR(HDFGWTR2_EL2), 589 590 VNCR(VNCR_EL2), 591 592 VNCR(CNTVOFF_EL2), 593 VNCR(CNTV_CVAL_EL0), 594 VNCR(CNTV_CTL_EL0), 595 VNCR(CNTP_CVAL_EL0), 596 VNCR(CNTP_CTL_EL0), 597 598 VNCR(ICH_LR0_EL2), 599 VNCR(ICH_LR1_EL2), 600 VNCR(ICH_LR2_EL2), 601 VNCR(ICH_LR3_EL2), 602 VNCR(ICH_LR4_EL2), 603 VNCR(ICH_LR5_EL2), 604 VNCR(ICH_LR6_EL2), 605 VNCR(ICH_LR7_EL2), 606 VNCR(ICH_LR8_EL2), 607 VNCR(ICH_LR9_EL2), 608 VNCR(ICH_LR10_EL2), 609 VNCR(ICH_LR11_EL2), 610 VNCR(ICH_LR12_EL2), 611 VNCR(ICH_LR13_EL2), 612 VNCR(ICH_LR14_EL2), 613 VNCR(ICH_LR15_EL2), 614 615 VNCR(ICH_AP0R0_EL2), 616 VNCR(ICH_AP0R1_EL2), 617 VNCR(ICH_AP0R2_EL2), 618 VNCR(ICH_AP0R3_EL2), 619 VNCR(ICH_AP1R0_EL2), 620 VNCR(ICH_AP1R1_EL2), 621 VNCR(ICH_AP1R2_EL2), 622 VNCR(ICH_AP1R3_EL2), 623 VNCR(ICH_HCR_EL2), 624 VNCR(ICH_VMCR_EL2), 625 626 NR_SYS_REGS /* Nothing after this line! */ 627 }; 628 629 struct kvm_sysreg_masks { 630 struct { 631 u64 res0; 632 u64 res1; 633 } mask[NR_SYS_REGS - __SANITISED_REG_START__]; 634 }; 635 636 struct fgt_masks { 637 const char *str; 638 u64 mask; 639 u64 nmask; 640 u64 res0; 641 }; 642 643 extern struct fgt_masks hfgrtr_masks; 644 extern struct fgt_masks hfgwtr_masks; 645 extern struct fgt_masks hfgitr_masks; 646 extern struct fgt_masks hdfgrtr_masks; 647 extern struct fgt_masks hdfgwtr_masks; 648 extern struct fgt_masks hafgrtr_masks; 649 extern struct fgt_masks hfgrtr2_masks; 650 extern struct fgt_masks hfgwtr2_masks; 651 extern struct fgt_masks hfgitr2_masks; 652 extern struct fgt_masks hdfgrtr2_masks; 653 extern struct fgt_masks hdfgwtr2_masks; 654 655 extern struct fgt_masks kvm_nvhe_sym(hfgrtr_masks); 656 extern struct fgt_masks kvm_nvhe_sym(hfgwtr_masks); 657 extern struct fgt_masks kvm_nvhe_sym(hfgitr_masks); 658 extern struct fgt_masks kvm_nvhe_sym(hdfgrtr_masks); 659 extern struct fgt_masks kvm_nvhe_sym(hdfgwtr_masks); 660 extern struct fgt_masks kvm_nvhe_sym(hafgrtr_masks); 661 extern struct fgt_masks kvm_nvhe_sym(hfgrtr2_masks); 662 extern struct fgt_masks kvm_nvhe_sym(hfgwtr2_masks); 663 extern struct fgt_masks kvm_nvhe_sym(hfgitr2_masks); 664 extern struct fgt_masks kvm_nvhe_sym(hdfgrtr2_masks); 665 extern struct fgt_masks kvm_nvhe_sym(hdfgwtr2_masks); 666 667 struct kvm_cpu_context { 668 struct user_pt_regs regs; /* sp = sp_el0 */ 669 670 u64 spsr_abt; 671 u64 spsr_und; 672 u64 spsr_irq; 673 u64 spsr_fiq; 674 675 struct user_fpsimd_state fp_regs; 676 677 u64 sys_regs[NR_SYS_REGS]; 678 679 struct kvm_vcpu *__hyp_running_vcpu; 680 681 /* This pointer has to be 4kB aligned. */ 682 u64 *vncr_array; 683 }; 684 685 struct cpu_sve_state { 686 __u64 zcr_el1; 687 688 /* 689 * Ordering is important since __sve_save_state/__sve_restore_state 690 * relies on it. 691 */ 692 __u32 fpsr; 693 __u32 fpcr; 694 695 /* Must be SVE_VQ_BYTES (128 bit) aligned. */ 696 __u8 sve_regs[]; 697 }; 698 699 /* 700 * This structure is instantiated on a per-CPU basis, and contains 701 * data that is: 702 * 703 * - tied to a single physical CPU, and 704 * - either have a lifetime that does not extend past vcpu_put() 705 * - or is an invariant for the lifetime of the system 706 * 707 * Use host_data_ptr(field) as a way to access a pointer to such a 708 * field. 709 */ 710 struct kvm_host_data { 711 #define KVM_HOST_DATA_FLAG_HAS_SPE 0 712 #define KVM_HOST_DATA_FLAG_HAS_TRBE 1 713 #define KVM_HOST_DATA_FLAG_TRBE_ENABLED 4 714 #define KVM_HOST_DATA_FLAG_EL1_TRACING_CONFIGURED 5 715 #define KVM_HOST_DATA_FLAG_VCPU_IN_HYP_CONTEXT 6 716 #define KVM_HOST_DATA_FLAG_L1_VNCR_MAPPED 7 717 #define KVM_HOST_DATA_FLAG_HAS_BRBE 8 718 unsigned long flags; 719 720 struct kvm_cpu_context host_ctxt; 721 722 /* 723 * Hyp VA. 724 * sve_state is only used in pKVM and if system_supports_sve(). 725 */ 726 struct cpu_sve_state *sve_state; 727 728 /* Used by pKVM only. */ 729 u64 fpmr; 730 731 /* Ownership of the FP regs */ 732 enum { 733 FP_STATE_FREE, 734 FP_STATE_HOST_OWNED, 735 FP_STATE_GUEST_OWNED, 736 } fp_owner; 737 738 /* 739 * host_debug_state contains the host registers which are 740 * saved and restored during world switches. 741 */ 742 struct { 743 /* {Break,watch}point registers */ 744 struct kvm_guest_debug_arch regs; 745 /* Statistical profiling extension */ 746 u64 pmscr_el1; 747 /* Self-hosted trace */ 748 u64 trfcr_el1; 749 /* Values of trap registers for the host before guest entry. */ 750 u64 mdcr_el2; 751 u64 brbcr_el1; 752 } host_debug_state; 753 754 /* Guest trace filter value */ 755 u64 trfcr_while_in_guest; 756 757 /* Number of programmable event counters (PMCR_EL0.N) for this CPU */ 758 unsigned int nr_event_counters; 759 760 /* Number of debug breakpoints/watchpoints for this CPU (minus 1) */ 761 unsigned int debug_brps; 762 unsigned int debug_wrps; 763 }; 764 765 struct kvm_host_psci_config { 766 /* PSCI version used by host. */ 767 u32 version; 768 u32 smccc_version; 769 770 /* Function IDs used by host if version is v0.1. */ 771 struct psci_0_1_function_ids function_ids_0_1; 772 773 bool psci_0_1_cpu_suspend_implemented; 774 bool psci_0_1_cpu_on_implemented; 775 bool psci_0_1_cpu_off_implemented; 776 bool psci_0_1_migrate_implemented; 777 }; 778 779 extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config); 780 #define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config) 781 782 extern s64 kvm_nvhe_sym(hyp_physvirt_offset); 783 #define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset) 784 785 extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS]; 786 #define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map) 787 788 struct vcpu_reset_state { 789 unsigned long pc; 790 unsigned long r0; 791 bool be; 792 bool reset; 793 }; 794 795 struct vncr_tlb; 796 797 struct kvm_vcpu_arch { 798 struct kvm_cpu_context ctxt; 799 800 /* 801 * Guest floating point state 802 * 803 * The architecture has two main floating point extensions, 804 * the original FPSIMD and SVE. These have overlapping 805 * register views, with the FPSIMD V registers occupying the 806 * low 128 bits of the SVE Z registers. When the core 807 * floating point code saves the register state of a task it 808 * records which view it saved in fp_type. 809 */ 810 void *sve_state; 811 enum fp_type fp_type; 812 unsigned int sve_max_vl; 813 814 /* Stage 2 paging state used by the hardware on next switch */ 815 struct kvm_s2_mmu *hw_mmu; 816 817 /* Values of trap registers for the guest. */ 818 u64 hcr_el2; 819 u64 hcrx_el2; 820 u64 mdcr_el2; 821 822 struct { 823 u64 r; 824 u64 w; 825 } fgt[__NR_FGT_GROUP_IDS__]; 826 827 /* Exception Information */ 828 struct kvm_vcpu_fault_info fault; 829 830 /* Configuration flags, set once and for all before the vcpu can run */ 831 u8 cflags; 832 833 /* Input flags to the hypervisor code, potentially cleared after use */ 834 u8 iflags; 835 836 /* State flags for kernel bookkeeping, unused by the hypervisor code */ 837 u16 sflags; 838 839 /* 840 * Don't run the guest (internal implementation need). 841 * 842 * Contrary to the flags above, this is set/cleared outside of 843 * a vcpu context, and thus cannot be mixed with the flags 844 * themselves (or the flag accesses need to be made atomic). 845 */ 846 bool pause; 847 848 /* 849 * We maintain more than a single set of debug registers to support 850 * debugging the guest from the host and to maintain separate host and 851 * guest state during world switches. vcpu_debug_state are the debug 852 * registers of the vcpu as the guest sees them. 853 * 854 * external_debug_state contains the debug values we want to debug the 855 * guest. This is set via the KVM_SET_GUEST_DEBUG ioctl. 856 */ 857 struct kvm_guest_debug_arch vcpu_debug_state; 858 struct kvm_guest_debug_arch external_debug_state; 859 u64 external_mdscr_el1; 860 861 enum { 862 VCPU_DEBUG_FREE, 863 VCPU_DEBUG_HOST_OWNED, 864 VCPU_DEBUG_GUEST_OWNED, 865 } debug_owner; 866 867 /* VGIC state */ 868 struct vgic_cpu vgic_cpu; 869 struct arch_timer_cpu timer_cpu; 870 struct kvm_pmu pmu; 871 872 /* vcpu power state */ 873 struct kvm_mp_state mp_state; 874 spinlock_t mp_state_lock; 875 876 /* Cache some mmu pages needed inside spinlock regions */ 877 struct kvm_mmu_memory_cache mmu_page_cache; 878 879 /* Pages to top-up the pKVM/EL2 guest pool */ 880 struct kvm_hyp_memcache pkvm_memcache; 881 882 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */ 883 u64 vsesr_el2; 884 885 /* Additional reset state */ 886 struct vcpu_reset_state reset_state; 887 888 /* Guest PV state */ 889 struct { 890 u64 last_steal; 891 gpa_t base; 892 } steal; 893 894 /* Per-vcpu CCSIDR override or NULL */ 895 u32 *ccsidr; 896 897 /* Per-vcpu TLB for VNCR_EL2 -- NULL when !NV */ 898 struct vncr_tlb *vncr_tlb; 899 }; 900 901 /* 902 * Each 'flag' is composed of a comma-separated triplet: 903 * 904 * - the flag-set it belongs to in the vcpu->arch structure 905 * - the value for that flag 906 * - the mask for that flag 907 * 908 * __vcpu_single_flag() builds such a triplet for a single-bit flag. 909 * unpack_vcpu_flag() extract the flag value from the triplet for 910 * direct use outside of the flag accessors. 911 */ 912 #define __vcpu_single_flag(_set, _f) _set, (_f), (_f) 913 914 #define __unpack_flag(_set, _f, _m) _f 915 #define unpack_vcpu_flag(...) __unpack_flag(__VA_ARGS__) 916 917 #define __build_check_flag(v, flagset, f, m) \ 918 do { \ 919 typeof(v->arch.flagset) *_fset; \ 920 \ 921 /* Check that the flags fit in the mask */ \ 922 BUILD_BUG_ON(HWEIGHT(m) != HWEIGHT((f) | (m))); \ 923 /* Check that the flags fit in the type */ \ 924 BUILD_BUG_ON((sizeof(*_fset) * 8) <= __fls(m)); \ 925 } while (0) 926 927 #define __vcpu_get_flag(v, flagset, f, m) \ 928 ({ \ 929 __build_check_flag(v, flagset, f, m); \ 930 \ 931 READ_ONCE(v->arch.flagset) & (m); \ 932 }) 933 934 /* 935 * Note that the set/clear accessors must be preempt-safe in order to 936 * avoid nesting them with load/put which also manipulate flags... 937 */ 938 #ifdef __KVM_NVHE_HYPERVISOR__ 939 /* the nVHE hypervisor is always non-preemptible */ 940 #define __vcpu_flags_preempt_disable() 941 #define __vcpu_flags_preempt_enable() 942 #else 943 #define __vcpu_flags_preempt_disable() preempt_disable() 944 #define __vcpu_flags_preempt_enable() preempt_enable() 945 #endif 946 947 #define __vcpu_set_flag(v, flagset, f, m) \ 948 do { \ 949 typeof(v->arch.flagset) *fset; \ 950 \ 951 __build_check_flag(v, flagset, f, m); \ 952 \ 953 fset = &v->arch.flagset; \ 954 __vcpu_flags_preempt_disable(); \ 955 if (HWEIGHT(m) > 1) \ 956 *fset &= ~(m); \ 957 *fset |= (f); \ 958 __vcpu_flags_preempt_enable(); \ 959 } while (0) 960 961 #define __vcpu_clear_flag(v, flagset, f, m) \ 962 do { \ 963 typeof(v->arch.flagset) *fset; \ 964 \ 965 __build_check_flag(v, flagset, f, m); \ 966 \ 967 fset = &v->arch.flagset; \ 968 __vcpu_flags_preempt_disable(); \ 969 *fset &= ~(m); \ 970 __vcpu_flags_preempt_enable(); \ 971 } while (0) 972 973 #define __vcpu_test_and_clear_flag(v, flagset, f, m) \ 974 ({ \ 975 typeof(v->arch.flagset) set; \ 976 \ 977 set = __vcpu_get_flag(v, flagset, f, m); \ 978 __vcpu_clear_flag(v, flagset, f, m); \ 979 \ 980 set; \ 981 }) 982 983 #define vcpu_get_flag(v, ...) __vcpu_get_flag((v), __VA_ARGS__) 984 #define vcpu_set_flag(v, ...) __vcpu_set_flag((v), __VA_ARGS__) 985 #define vcpu_clear_flag(v, ...) __vcpu_clear_flag((v), __VA_ARGS__) 986 #define vcpu_test_and_clear_flag(v, ...) \ 987 __vcpu_test_and_clear_flag((v), __VA_ARGS__) 988 989 /* KVM_ARM_VCPU_INIT completed */ 990 #define VCPU_INITIALIZED __vcpu_single_flag(cflags, BIT(0)) 991 /* SVE config completed */ 992 #define VCPU_SVE_FINALIZED __vcpu_single_flag(cflags, BIT(1)) 993 /* pKVM VCPU setup completed */ 994 #define VCPU_PKVM_FINALIZED __vcpu_single_flag(cflags, BIT(2)) 995 996 /* Exception pending */ 997 #define PENDING_EXCEPTION __vcpu_single_flag(iflags, BIT(0)) 998 /* 999 * PC increment. Overlaps with EXCEPT_MASK on purpose so that it can't 1000 * be set together with an exception... 1001 */ 1002 #define INCREMENT_PC __vcpu_single_flag(iflags, BIT(1)) 1003 /* Target EL/MODE (not a single flag, but let's abuse the macro) */ 1004 #define EXCEPT_MASK __vcpu_single_flag(iflags, GENMASK(3, 1)) 1005 1006 /* Helpers to encode exceptions with minimum fuss */ 1007 #define __EXCEPT_MASK_VAL unpack_vcpu_flag(EXCEPT_MASK) 1008 #define __EXCEPT_SHIFT __builtin_ctzl(__EXCEPT_MASK_VAL) 1009 #define __vcpu_except_flags(_f) iflags, (_f << __EXCEPT_SHIFT), __EXCEPT_MASK_VAL 1010 1011 /* 1012 * When PENDING_EXCEPTION is set, EXCEPT_MASK can take the following 1013 * values: 1014 * 1015 * For AArch32 EL1: 1016 */ 1017 #define EXCEPT_AA32_UND __vcpu_except_flags(0) 1018 #define EXCEPT_AA32_IABT __vcpu_except_flags(1) 1019 #define EXCEPT_AA32_DABT __vcpu_except_flags(2) 1020 /* For AArch64: */ 1021 #define EXCEPT_AA64_EL1_SYNC __vcpu_except_flags(0) 1022 #define EXCEPT_AA64_EL1_IRQ __vcpu_except_flags(1) 1023 #define EXCEPT_AA64_EL1_FIQ __vcpu_except_flags(2) 1024 #define EXCEPT_AA64_EL1_SERR __vcpu_except_flags(3) 1025 /* For AArch64 with NV: */ 1026 #define EXCEPT_AA64_EL2_SYNC __vcpu_except_flags(4) 1027 #define EXCEPT_AA64_EL2_IRQ __vcpu_except_flags(5) 1028 #define EXCEPT_AA64_EL2_FIQ __vcpu_except_flags(6) 1029 #define EXCEPT_AA64_EL2_SERR __vcpu_except_flags(7) 1030 1031 /* Physical CPU not in supported_cpus */ 1032 #define ON_UNSUPPORTED_CPU __vcpu_single_flag(sflags, BIT(0)) 1033 /* WFIT instruction trapped */ 1034 #define IN_WFIT __vcpu_single_flag(sflags, BIT(1)) 1035 /* vcpu system registers loaded on physical CPU */ 1036 #define SYSREGS_ON_CPU __vcpu_single_flag(sflags, BIT(2)) 1037 /* Software step state is Active-pending for external debug */ 1038 #define HOST_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(3)) 1039 /* Software step state is Active pending for guest debug */ 1040 #define GUEST_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(4)) 1041 /* PMUSERENR for the guest EL0 is on physical CPU */ 1042 #define PMUSERENR_ON_CPU __vcpu_single_flag(sflags, BIT(5)) 1043 /* WFI instruction trapped */ 1044 #define IN_WFI __vcpu_single_flag(sflags, BIT(6)) 1045 /* KVM is currently emulating a nested ERET */ 1046 #define IN_NESTED_ERET __vcpu_single_flag(sflags, BIT(7)) 1047 /* SError pending for nested guest */ 1048 #define NESTED_SERROR_PENDING __vcpu_single_flag(sflags, BIT(8)) 1049 1050 1051 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */ 1052 #define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) + \ 1053 sve_ffr_offset((vcpu)->arch.sve_max_vl)) 1054 1055 #define vcpu_sve_max_vq(vcpu) sve_vq_from_vl((vcpu)->arch.sve_max_vl) 1056 1057 #define vcpu_sve_zcr_elx(vcpu) \ 1058 (unlikely(is_hyp_ctxt(vcpu)) ? ZCR_EL2 : ZCR_EL1) 1059 1060 #define sve_state_size_from_vl(sve_max_vl) ({ \ 1061 size_t __size_ret; \ 1062 unsigned int __vq; \ 1063 \ 1064 if (WARN_ON(!sve_vl_valid(sve_max_vl))) { \ 1065 __size_ret = 0; \ 1066 } else { \ 1067 __vq = sve_vq_from_vl(sve_max_vl); \ 1068 __size_ret = SVE_SIG_REGS_SIZE(__vq); \ 1069 } \ 1070 \ 1071 __size_ret; \ 1072 }) 1073 1074 #define vcpu_sve_state_size(vcpu) sve_state_size_from_vl((vcpu)->arch.sve_max_vl) 1075 1076 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \ 1077 KVM_GUESTDBG_USE_SW_BP | \ 1078 KVM_GUESTDBG_USE_HW | \ 1079 KVM_GUESTDBG_SINGLESTEP) 1080 1081 #define kvm_has_sve(kvm) (system_supports_sve() && \ 1082 test_bit(KVM_ARCH_FLAG_GUEST_HAS_SVE, &(kvm)->arch.flags)) 1083 1084 #ifdef __KVM_NVHE_HYPERVISOR__ 1085 #define vcpu_has_sve(vcpu) kvm_has_sve(kern_hyp_va((vcpu)->kvm)) 1086 #else 1087 #define vcpu_has_sve(vcpu) kvm_has_sve((vcpu)->kvm) 1088 #endif 1089 1090 #ifdef CONFIG_ARM64_PTR_AUTH 1091 #define vcpu_has_ptrauth(vcpu) \ 1092 ((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) || \ 1093 cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) && \ 1094 (vcpu_has_feature(vcpu, KVM_ARM_VCPU_PTRAUTH_ADDRESS) || \ 1095 vcpu_has_feature(vcpu, KVM_ARM_VCPU_PTRAUTH_GENERIC))) 1096 #else 1097 #define vcpu_has_ptrauth(vcpu) false 1098 #endif 1099 1100 #define vcpu_on_unsupported_cpu(vcpu) \ 1101 vcpu_get_flag(vcpu, ON_UNSUPPORTED_CPU) 1102 1103 #define vcpu_set_on_unsupported_cpu(vcpu) \ 1104 vcpu_set_flag(vcpu, ON_UNSUPPORTED_CPU) 1105 1106 #define vcpu_clear_on_unsupported_cpu(vcpu) \ 1107 vcpu_clear_flag(vcpu, ON_UNSUPPORTED_CPU) 1108 1109 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.regs) 1110 1111 /* 1112 * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the 1113 * memory backed version of a register, and not the one most recently 1114 * accessed by a running VCPU. For example, for userspace access or 1115 * for system registers that are never context switched, but only 1116 * emulated. 1117 * 1118 * Don't bother with VNCR-based accesses in the nVHE code, it has no 1119 * business dealing with NV. 1120 */ 1121 static inline u64 *___ctxt_sys_reg(const struct kvm_cpu_context *ctxt, int r) 1122 { 1123 #if !defined (__KVM_NVHE_HYPERVISOR__) 1124 if (unlikely(cpus_have_final_cap(ARM64_HAS_NESTED_VIRT) && 1125 r >= __VNCR_START__ && ctxt->vncr_array)) 1126 return &ctxt->vncr_array[r - __VNCR_START__]; 1127 #endif 1128 return (u64 *)&ctxt->sys_regs[r]; 1129 } 1130 1131 #define __ctxt_sys_reg(c,r) \ 1132 ({ \ 1133 BUILD_BUG_ON(__builtin_constant_p(r) && \ 1134 (r) >= NR_SYS_REGS); \ 1135 ___ctxt_sys_reg(c, r); \ 1136 }) 1137 1138 #define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r)) 1139 1140 u64 kvm_vcpu_apply_reg_masks(const struct kvm_vcpu *, enum vcpu_sysreg, u64); 1141 1142 #define __vcpu_assign_sys_reg(v, r, val) \ 1143 do { \ 1144 const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \ 1145 u64 __v = (val); \ 1146 if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \ 1147 __v = kvm_vcpu_apply_reg_masks((v), (r), __v); \ 1148 \ 1149 ctxt_sys_reg(ctxt, (r)) = __v; \ 1150 } while (0) 1151 1152 #define __vcpu_rmw_sys_reg(v, r, op, val) \ 1153 do { \ 1154 const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \ 1155 u64 __v = ctxt_sys_reg(ctxt, (r)); \ 1156 __v op (val); \ 1157 if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \ 1158 __v = kvm_vcpu_apply_reg_masks((v), (r), __v); \ 1159 \ 1160 ctxt_sys_reg(ctxt, (r)) = __v; \ 1161 } while (0) 1162 1163 #define __vcpu_sys_reg(v,r) \ 1164 ({ \ 1165 const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \ 1166 u64 __v = ctxt_sys_reg(ctxt, (r)); \ 1167 if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \ 1168 __v = kvm_vcpu_apply_reg_masks((v), (r), __v); \ 1169 __v; \ 1170 }) 1171 1172 u64 vcpu_read_sys_reg(const struct kvm_vcpu *, enum vcpu_sysreg); 1173 void vcpu_write_sys_reg(struct kvm_vcpu *, u64, enum vcpu_sysreg); 1174 1175 struct kvm_vm_stat { 1176 struct kvm_vm_stat_generic generic; 1177 }; 1178 1179 struct kvm_vcpu_stat { 1180 struct kvm_vcpu_stat_generic generic; 1181 u64 hvc_exit_stat; 1182 u64 wfe_exit_stat; 1183 u64 wfi_exit_stat; 1184 u64 mmio_exit_user; 1185 u64 mmio_exit_kernel; 1186 u64 signal_exits; 1187 u64 exits; 1188 }; 1189 1190 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); 1191 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); 1192 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 1193 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 1194 1195 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu); 1196 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices); 1197 1198 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu, 1199 struct kvm_vcpu_events *events); 1200 1201 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu, 1202 struct kvm_vcpu_events *events); 1203 1204 void kvm_arm_halt_guest(struct kvm *kvm); 1205 void kvm_arm_resume_guest(struct kvm *kvm); 1206 1207 #define vcpu_has_run_once(vcpu) (!!READ_ONCE((vcpu)->pid)) 1208 1209 #ifndef __KVM_NVHE_HYPERVISOR__ 1210 #define kvm_call_hyp_nvhe(f, ...) \ 1211 ({ \ 1212 struct arm_smccc_res res; \ 1213 \ 1214 arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f), \ 1215 ##__VA_ARGS__, &res); \ 1216 WARN_ON(res.a0 != SMCCC_RET_SUCCESS); \ 1217 \ 1218 res.a1; \ 1219 }) 1220 1221 /* 1222 * The isb() below is there to guarantee the same behaviour on VHE as on !VHE, 1223 * where the eret to EL1 acts as a context synchronization event. 1224 */ 1225 #define kvm_call_hyp(f, ...) \ 1226 do { \ 1227 if (has_vhe()) { \ 1228 f(__VA_ARGS__); \ 1229 isb(); \ 1230 } else { \ 1231 kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 1232 } \ 1233 } while(0) 1234 1235 #define kvm_call_hyp_ret(f, ...) \ 1236 ({ \ 1237 typeof(f(__VA_ARGS__)) ret; \ 1238 \ 1239 if (has_vhe()) { \ 1240 ret = f(__VA_ARGS__); \ 1241 } else { \ 1242 ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 1243 } \ 1244 \ 1245 ret; \ 1246 }) 1247 #else /* __KVM_NVHE_HYPERVISOR__ */ 1248 #define kvm_call_hyp(f, ...) f(__VA_ARGS__) 1249 #define kvm_call_hyp_ret(f, ...) f(__VA_ARGS__) 1250 #define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__) 1251 #endif /* __KVM_NVHE_HYPERVISOR__ */ 1252 1253 int handle_exit(struct kvm_vcpu *vcpu, int exception_index); 1254 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index); 1255 1256 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu); 1257 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu); 1258 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu); 1259 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu); 1260 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu); 1261 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu); 1262 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu); 1263 1264 void kvm_sys_regs_create_debugfs(struct kvm *kvm); 1265 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu); 1266 1267 int __init kvm_sys_reg_table_init(void); 1268 struct sys_reg_desc; 1269 int __init populate_sysreg_config(const struct sys_reg_desc *sr, 1270 unsigned int idx); 1271 int __init populate_nv_trap_config(void); 1272 1273 void kvm_calculate_traps(struct kvm_vcpu *vcpu); 1274 1275 /* MMIO helpers */ 1276 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data); 1277 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len); 1278 1279 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu); 1280 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa); 1281 1282 /* 1283 * Returns true if a Performance Monitoring Interrupt (PMI), a.k.a. perf event, 1284 * arrived in guest context. For arm64, any event that arrives while a vCPU is 1285 * loaded is considered to be "in guest". 1286 */ 1287 static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu) 1288 { 1289 return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu; 1290 } 1291 1292 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu); 1293 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu); 1294 void kvm_update_stolen_time(struct kvm_vcpu *vcpu); 1295 1296 bool kvm_arm_pvtime_supported(void); 1297 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu, 1298 struct kvm_device_attr *attr); 1299 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu, 1300 struct kvm_device_attr *attr); 1301 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu, 1302 struct kvm_device_attr *attr); 1303 1304 extern unsigned int __ro_after_init kvm_arm_vmid_bits; 1305 int __init kvm_arm_vmid_alloc_init(void); 1306 void __init kvm_arm_vmid_alloc_free(void); 1307 void kvm_arm_vmid_update(struct kvm_vmid *kvm_vmid); 1308 void kvm_arm_vmid_clear_active(void); 1309 1310 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch) 1311 { 1312 vcpu_arch->steal.base = INVALID_GPA; 1313 } 1314 1315 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch) 1316 { 1317 return (vcpu_arch->steal.base != INVALID_GPA); 1318 } 1319 1320 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); 1321 1322 DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data); 1323 1324 /* 1325 * How we access per-CPU host data depends on the where we access it from, 1326 * and the mode we're in: 1327 * 1328 * - VHE and nVHE hypervisor bits use their locally defined instance 1329 * 1330 * - the rest of the kernel use either the VHE or nVHE one, depending on 1331 * the mode we're running in. 1332 * 1333 * Unless we're in protected mode, fully deprivileged, and the nVHE 1334 * per-CPU stuff is exclusively accessible to the protected EL2 code. 1335 * In this case, the EL1 code uses the *VHE* data as its private state 1336 * (which makes sense in a way as there shouldn't be any shared state 1337 * between the host and the hypervisor). 1338 * 1339 * Yes, this is all totally trivial. Shoot me now. 1340 */ 1341 #if defined(__KVM_NVHE_HYPERVISOR__) || defined(__KVM_VHE_HYPERVISOR__) 1342 #define host_data_ptr(f) (&this_cpu_ptr(&kvm_host_data)->f) 1343 #else 1344 #define host_data_ptr(f) \ 1345 (static_branch_unlikely(&kvm_protected_mode_initialized) ? \ 1346 &this_cpu_ptr(&kvm_host_data)->f : \ 1347 &this_cpu_ptr_hyp_sym(kvm_host_data)->f) 1348 #endif 1349 1350 #define host_data_test_flag(flag) \ 1351 (test_bit(KVM_HOST_DATA_FLAG_##flag, host_data_ptr(flags))) 1352 #define host_data_set_flag(flag) \ 1353 set_bit(KVM_HOST_DATA_FLAG_##flag, host_data_ptr(flags)) 1354 #define host_data_clear_flag(flag) \ 1355 clear_bit(KVM_HOST_DATA_FLAG_##flag, host_data_ptr(flags)) 1356 1357 /* Check whether the FP regs are owned by the guest */ 1358 static inline bool guest_owns_fp_regs(void) 1359 { 1360 return *host_data_ptr(fp_owner) == FP_STATE_GUEST_OWNED; 1361 } 1362 1363 /* Check whether the FP regs are owned by the host */ 1364 static inline bool host_owns_fp_regs(void) 1365 { 1366 return *host_data_ptr(fp_owner) == FP_STATE_HOST_OWNED; 1367 } 1368 1369 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt) 1370 { 1371 /* The host's MPIDR is immutable, so let's set it up at boot time */ 1372 ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr(); 1373 } 1374 1375 static inline bool kvm_system_needs_idmapped_vectors(void) 1376 { 1377 return cpus_have_final_cap(ARM64_SPECTRE_V3A); 1378 } 1379 1380 void kvm_init_host_debug_data(void); 1381 void kvm_debug_init_vhe(void); 1382 void kvm_vcpu_load_debug(struct kvm_vcpu *vcpu); 1383 void kvm_vcpu_put_debug(struct kvm_vcpu *vcpu); 1384 void kvm_debug_set_guest_ownership(struct kvm_vcpu *vcpu); 1385 void kvm_debug_handle_oslar(struct kvm_vcpu *vcpu, u64 val); 1386 1387 #define kvm_vcpu_os_lock_enabled(vcpu) \ 1388 (!!(__vcpu_sys_reg(vcpu, OSLSR_EL1) & OSLSR_EL1_OSLK)) 1389 1390 #define kvm_debug_regs_in_use(vcpu) \ 1391 ((vcpu)->arch.debug_owner != VCPU_DEBUG_FREE) 1392 #define kvm_host_owns_debug_regs(vcpu) \ 1393 ((vcpu)->arch.debug_owner == VCPU_DEBUG_HOST_OWNED) 1394 #define kvm_guest_owns_debug_regs(vcpu) \ 1395 ((vcpu)->arch.debug_owner == VCPU_DEBUG_GUEST_OWNED) 1396 1397 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, 1398 struct kvm_device_attr *attr); 1399 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, 1400 struct kvm_device_attr *attr); 1401 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, 1402 struct kvm_device_attr *attr); 1403 1404 int kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm, 1405 struct kvm_arm_copy_mte_tags *copy_tags); 1406 int kvm_vm_ioctl_set_counter_offset(struct kvm *kvm, 1407 struct kvm_arm_counter_offset *offset); 1408 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, 1409 struct reg_mask_range *range); 1410 1411 /* Guest/host FPSIMD coordination helpers */ 1412 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu); 1413 void kvm_arch_vcpu_ctxflush_fp(struct kvm_vcpu *vcpu); 1414 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu); 1415 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu); 1416 1417 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr) 1418 { 1419 return (!has_vhe() && attr->exclude_host); 1420 } 1421 1422 #ifdef CONFIG_KVM 1423 void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr); 1424 void kvm_clr_pmu_events(u64 clr); 1425 bool kvm_set_pmuserenr(u64 val); 1426 void kvm_enable_trbe(void); 1427 void kvm_disable_trbe(void); 1428 void kvm_tracing_set_el1_configuration(u64 trfcr_while_in_guest); 1429 #else 1430 static inline void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr) {} 1431 static inline void kvm_clr_pmu_events(u64 clr) {} 1432 static inline bool kvm_set_pmuserenr(u64 val) 1433 { 1434 return false; 1435 } 1436 static inline void kvm_enable_trbe(void) {} 1437 static inline void kvm_disable_trbe(void) {} 1438 static inline void kvm_tracing_set_el1_configuration(u64 trfcr_while_in_guest) {} 1439 #endif 1440 1441 void kvm_vcpu_load_vhe(struct kvm_vcpu *vcpu); 1442 void kvm_vcpu_put_vhe(struct kvm_vcpu *vcpu); 1443 1444 int __init kvm_set_ipa_limit(void); 1445 u32 kvm_get_pa_bits(struct kvm *kvm); 1446 1447 #define __KVM_HAVE_ARCH_VM_ALLOC 1448 struct kvm *kvm_arch_alloc_vm(void); 1449 1450 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS 1451 1452 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS_RANGE 1453 1454 #define kvm_vm_is_protected(kvm) (is_protected_kvm_enabled() && (kvm)->arch.pkvm.is_protected) 1455 1456 #define vcpu_is_protected(vcpu) kvm_vm_is_protected((vcpu)->kvm) 1457 1458 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature); 1459 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu); 1460 1461 #define kvm_arm_vcpu_sve_finalized(vcpu) vcpu_get_flag(vcpu, VCPU_SVE_FINALIZED) 1462 1463 #define kvm_has_mte(kvm) \ 1464 (system_supports_mte() && \ 1465 test_bit(KVM_ARCH_FLAG_MTE_ENABLED, &(kvm)->arch.flags)) 1466 1467 #define kvm_supports_32bit_el0() \ 1468 (system_supports_32bit_el0() && \ 1469 !static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1470 1471 #define kvm_vm_has_ran_once(kvm) \ 1472 (test_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &(kvm)->arch.flags)) 1473 1474 static inline bool __vcpu_has_feature(const struct kvm_arch *ka, int feature) 1475 { 1476 return test_bit(feature, ka->vcpu_features); 1477 } 1478 1479 #define kvm_vcpu_has_feature(k, f) __vcpu_has_feature(&(k)->arch, (f)) 1480 #define vcpu_has_feature(v, f) __vcpu_has_feature(&(v)->kvm->arch, (f)) 1481 1482 #define kvm_vcpu_initialized(v) vcpu_get_flag(vcpu, VCPU_INITIALIZED) 1483 1484 int kvm_trng_call(struct kvm_vcpu *vcpu); 1485 #ifdef CONFIG_KVM 1486 extern phys_addr_t hyp_mem_base; 1487 extern phys_addr_t hyp_mem_size; 1488 void __init kvm_hyp_reserve(void); 1489 #else 1490 static inline void kvm_hyp_reserve(void) { } 1491 #endif 1492 1493 void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu); 1494 bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu); 1495 1496 static inline u64 *__vm_id_reg(struct kvm_arch *ka, u32 reg) 1497 { 1498 switch (reg) { 1499 case sys_reg(3, 0, 0, 1, 0) ... sys_reg(3, 0, 0, 7, 7): 1500 return &ka->id_regs[IDREG_IDX(reg)]; 1501 case SYS_CTR_EL0: 1502 return &ka->ctr_el0; 1503 case SYS_MIDR_EL1: 1504 return &ka->midr_el1; 1505 case SYS_REVIDR_EL1: 1506 return &ka->revidr_el1; 1507 case SYS_AIDR_EL1: 1508 return &ka->aidr_el1; 1509 default: 1510 WARN_ON_ONCE(1); 1511 return NULL; 1512 } 1513 } 1514 1515 #define kvm_read_vm_id_reg(kvm, reg) \ 1516 ({ u64 __val = *__vm_id_reg(&(kvm)->arch, reg); __val; }) 1517 1518 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val); 1519 1520 #define __expand_field_sign_unsigned(id, fld, val) \ 1521 ((u64)SYS_FIELD_VALUE(id, fld, val)) 1522 1523 #define __expand_field_sign_signed(id, fld, val) \ 1524 ({ \ 1525 u64 __val = SYS_FIELD_VALUE(id, fld, val); \ 1526 sign_extend64(__val, id##_##fld##_WIDTH - 1); \ 1527 }) 1528 1529 #define get_idreg_field_unsigned(kvm, id, fld) \ 1530 ({ \ 1531 u64 __val = kvm_read_vm_id_reg((kvm), SYS_##id); \ 1532 FIELD_GET(id##_##fld##_MASK, __val); \ 1533 }) 1534 1535 #define get_idreg_field_signed(kvm, id, fld) \ 1536 ({ \ 1537 u64 __val = get_idreg_field_unsigned(kvm, id, fld); \ 1538 sign_extend64(__val, id##_##fld##_WIDTH - 1); \ 1539 }) 1540 1541 #define get_idreg_field_enum(kvm, id, fld) \ 1542 get_idreg_field_unsigned(kvm, id, fld) 1543 1544 #define kvm_cmp_feat_signed(kvm, id, fld, op, limit) \ 1545 (get_idreg_field_signed((kvm), id, fld) op __expand_field_sign_signed(id, fld, limit)) 1546 1547 #define kvm_cmp_feat_unsigned(kvm, id, fld, op, limit) \ 1548 (get_idreg_field_unsigned((kvm), id, fld) op __expand_field_sign_unsigned(id, fld, limit)) 1549 1550 #define kvm_cmp_feat(kvm, id, fld, op, limit) \ 1551 (id##_##fld##_SIGNED ? \ 1552 kvm_cmp_feat_signed(kvm, id, fld, op, limit) : \ 1553 kvm_cmp_feat_unsigned(kvm, id, fld, op, limit)) 1554 1555 #define __kvm_has_feat(kvm, id, fld, limit) \ 1556 kvm_cmp_feat(kvm, id, fld, >=, limit) 1557 1558 #define kvm_has_feat(kvm, ...) __kvm_has_feat(kvm, __VA_ARGS__) 1559 1560 #define __kvm_has_feat_enum(kvm, id, fld, val) \ 1561 kvm_cmp_feat_unsigned(kvm, id, fld, ==, val) 1562 1563 #define kvm_has_feat_enum(kvm, ...) __kvm_has_feat_enum(kvm, __VA_ARGS__) 1564 1565 #define kvm_has_feat_range(kvm, id, fld, min, max) \ 1566 (kvm_cmp_feat(kvm, id, fld, >=, min) && \ 1567 kvm_cmp_feat(kvm, id, fld, <=, max)) 1568 1569 /* Check for a given level of PAuth support */ 1570 #define kvm_has_pauth(k, l) \ 1571 ({ \ 1572 bool pa, pi, pa3; \ 1573 \ 1574 pa = kvm_has_feat((k), ID_AA64ISAR1_EL1, APA, l); \ 1575 pa &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPA, IMP); \ 1576 pi = kvm_has_feat((k), ID_AA64ISAR1_EL1, API, l); \ 1577 pi &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPI, IMP); \ 1578 pa3 = kvm_has_feat((k), ID_AA64ISAR2_EL1, APA3, l); \ 1579 pa3 &= kvm_has_feat((k), ID_AA64ISAR2_EL1, GPA3, IMP); \ 1580 \ 1581 (pa + pi + pa3) == 1; \ 1582 }) 1583 1584 #define kvm_has_fpmr(k) \ 1585 (system_supports_fpmr() && \ 1586 kvm_has_feat((k), ID_AA64PFR2_EL1, FPMR, IMP)) 1587 1588 #define kvm_has_tcr2(k) \ 1589 (kvm_has_feat((k), ID_AA64MMFR3_EL1, TCRX, IMP)) 1590 1591 #define kvm_has_s1pie(k) \ 1592 (kvm_has_feat((k), ID_AA64MMFR3_EL1, S1PIE, IMP)) 1593 1594 #define kvm_has_s1poe(k) \ 1595 (kvm_has_feat((k), ID_AA64MMFR3_EL1, S1POE, IMP)) 1596 1597 #define kvm_has_ras(k) \ 1598 (kvm_has_feat((k), ID_AA64PFR0_EL1, RAS, IMP)) 1599 1600 #define kvm_has_sctlr2(k) \ 1601 (kvm_has_feat((k), ID_AA64MMFR3_EL1, SCTLRX, IMP)) 1602 1603 static inline bool kvm_arch_has_irq_bypass(void) 1604 { 1605 return true; 1606 } 1607 1608 void compute_fgu(struct kvm *kvm, enum fgt_group_id fgt); 1609 void get_reg_fixed_bits(struct kvm *kvm, enum vcpu_sysreg reg, u64 *res0, u64 *res1); 1610 void check_feature_map(void); 1611 void kvm_vcpu_load_fgt(struct kvm_vcpu *vcpu); 1612 1613 static __always_inline enum fgt_group_id __fgt_reg_to_group_id(enum vcpu_sysreg reg) 1614 { 1615 switch (reg) { 1616 case HFGRTR_EL2: 1617 case HFGWTR_EL2: 1618 return HFGRTR_GROUP; 1619 case HFGITR_EL2: 1620 return HFGITR_GROUP; 1621 case HDFGRTR_EL2: 1622 case HDFGWTR_EL2: 1623 return HDFGRTR_GROUP; 1624 case HAFGRTR_EL2: 1625 return HAFGRTR_GROUP; 1626 case HFGRTR2_EL2: 1627 case HFGWTR2_EL2: 1628 return HFGRTR2_GROUP; 1629 case HFGITR2_EL2: 1630 return HFGITR2_GROUP; 1631 case HDFGRTR2_EL2: 1632 case HDFGWTR2_EL2: 1633 return HDFGRTR2_GROUP; 1634 default: 1635 BUILD_BUG_ON(1); 1636 } 1637 } 1638 1639 #define vcpu_fgt(vcpu, reg) \ 1640 ({ \ 1641 enum fgt_group_id id = __fgt_reg_to_group_id(reg); \ 1642 u64 *p; \ 1643 switch (reg) { \ 1644 case HFGWTR_EL2: \ 1645 case HDFGWTR_EL2: \ 1646 case HFGWTR2_EL2: \ 1647 case HDFGWTR2_EL2: \ 1648 p = &(vcpu)->arch.fgt[id].w; \ 1649 break; \ 1650 default: \ 1651 p = &(vcpu)->arch.fgt[id].r; \ 1652 break; \ 1653 } \ 1654 \ 1655 p; \ 1656 }) 1657 1658 #endif /* __ARM64_KVM_HOST_H__ */ 1659