1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/asm/kvm_host.h: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 */ 10 11 #ifndef __ARM64_KVM_HOST_H__ 12 #define __ARM64_KVM_HOST_H__ 13 14 #include <linux/arm-smccc.h> 15 #include <linux/bitmap.h> 16 #include <linux/types.h> 17 #include <linux/jump_label.h> 18 #include <linux/kvm_types.h> 19 #include <linux/maple_tree.h> 20 #include <linux/percpu.h> 21 #include <linux/psci.h> 22 #include <asm/arch_gicv3.h> 23 #include <asm/barrier.h> 24 #include <asm/cpufeature.h> 25 #include <asm/cputype.h> 26 #include <asm/daifflags.h> 27 #include <asm/fpsimd.h> 28 #include <asm/kvm.h> 29 #include <asm/kvm_asm.h> 30 #include <asm/vncr_mapping.h> 31 32 #define __KVM_HAVE_ARCH_INTC_INITIALIZED 33 34 #define KVM_HALT_POLL_NS_DEFAULT 500000 35 36 #include <kvm/arm_vgic.h> 37 #include <kvm/arm_arch_timer.h> 38 #include <kvm/arm_pmu.h> 39 40 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS 41 42 #define KVM_VCPU_MAX_FEATURES 7 43 #define KVM_VCPU_VALID_FEATURES (BIT(KVM_VCPU_MAX_FEATURES) - 1) 44 45 #define KVM_REQ_SLEEP \ 46 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 47 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1) 48 #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2) 49 #define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(3) 50 #define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4) 51 #define KVM_REQ_RELOAD_PMU KVM_ARCH_REQ(5) 52 #define KVM_REQ_SUSPEND KVM_ARCH_REQ(6) 53 #define KVM_REQ_RESYNC_PMU_EL0 KVM_ARCH_REQ(7) 54 #define KVM_REQ_NESTED_S2_UNMAP KVM_ARCH_REQ(8) 55 56 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \ 57 KVM_DIRTY_LOG_INITIALLY_SET) 58 59 #define KVM_HAVE_MMU_RWLOCK 60 61 /* 62 * Mode of operation configurable with kvm-arm.mode early param. 63 * See Documentation/admin-guide/kernel-parameters.txt for more information. 64 */ 65 enum kvm_mode { 66 KVM_MODE_DEFAULT, 67 KVM_MODE_PROTECTED, 68 KVM_MODE_NV, 69 KVM_MODE_NONE, 70 }; 71 #ifdef CONFIG_KVM 72 enum kvm_mode kvm_get_mode(void); 73 #else 74 static inline enum kvm_mode kvm_get_mode(void) { return KVM_MODE_NONE; }; 75 #endif 76 77 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use); 78 79 extern unsigned int __ro_after_init kvm_sve_max_vl; 80 extern unsigned int __ro_after_init kvm_host_sve_max_vl; 81 int __init kvm_arm_init_sve(void); 82 83 u32 __attribute_const__ kvm_target_cpu(void); 84 void kvm_reset_vcpu(struct kvm_vcpu *vcpu); 85 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu); 86 87 struct kvm_hyp_memcache { 88 phys_addr_t head; 89 unsigned long nr_pages; 90 }; 91 92 static inline void push_hyp_memcache(struct kvm_hyp_memcache *mc, 93 phys_addr_t *p, 94 phys_addr_t (*to_pa)(void *virt)) 95 { 96 *p = mc->head; 97 mc->head = to_pa(p); 98 mc->nr_pages++; 99 } 100 101 static inline void *pop_hyp_memcache(struct kvm_hyp_memcache *mc, 102 void *(*to_va)(phys_addr_t phys)) 103 { 104 phys_addr_t *p = to_va(mc->head); 105 106 if (!mc->nr_pages) 107 return NULL; 108 109 mc->head = *p; 110 mc->nr_pages--; 111 112 return p; 113 } 114 115 static inline int __topup_hyp_memcache(struct kvm_hyp_memcache *mc, 116 unsigned long min_pages, 117 void *(*alloc_fn)(void *arg), 118 phys_addr_t (*to_pa)(void *virt), 119 void *arg) 120 { 121 while (mc->nr_pages < min_pages) { 122 phys_addr_t *p = alloc_fn(arg); 123 124 if (!p) 125 return -ENOMEM; 126 push_hyp_memcache(mc, p, to_pa); 127 } 128 129 return 0; 130 } 131 132 static inline void __free_hyp_memcache(struct kvm_hyp_memcache *mc, 133 void (*free_fn)(void *virt, void *arg), 134 void *(*to_va)(phys_addr_t phys), 135 void *arg) 136 { 137 while (mc->nr_pages) 138 free_fn(pop_hyp_memcache(mc, to_va), arg); 139 } 140 141 void free_hyp_memcache(struct kvm_hyp_memcache *mc); 142 int topup_hyp_memcache(struct kvm_hyp_memcache *mc, unsigned long min_pages); 143 144 struct kvm_vmid { 145 atomic64_t id; 146 }; 147 148 struct kvm_s2_mmu { 149 struct kvm_vmid vmid; 150 151 /* 152 * stage2 entry level table 153 * 154 * Two kvm_s2_mmu structures in the same VM can point to the same 155 * pgd here. This happens when running a guest using a 156 * translation regime that isn't affected by its own stage-2 157 * translation, such as a non-VHE hypervisor running at vEL2, or 158 * for vEL1/EL0 with vHCR_EL2.VM == 0. In that case, we use the 159 * canonical stage-2 page tables. 160 */ 161 phys_addr_t pgd_phys; 162 struct kvm_pgtable *pgt; 163 164 /* 165 * VTCR value used on the host. For a non-NV guest (or a NV 166 * guest that runs in a context where its own S2 doesn't 167 * apply), its T0SZ value reflects that of the IPA size. 168 * 169 * For a shadow S2 MMU, T0SZ reflects the PARange exposed to 170 * the guest. 171 */ 172 u64 vtcr; 173 174 /* The last vcpu id that ran on each physical CPU */ 175 int __percpu *last_vcpu_ran; 176 177 #define KVM_ARM_EAGER_SPLIT_CHUNK_SIZE_DEFAULT 0 178 /* 179 * Memory cache used to split 180 * KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE worth of huge pages. It 181 * is used to allocate stage2 page tables while splitting huge 182 * pages. The choice of KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE 183 * influences both the capacity of the split page cache, and 184 * how often KVM reschedules. Be wary of raising CHUNK_SIZE 185 * too high. 186 * 187 * Protected by kvm->slots_lock. 188 */ 189 struct kvm_mmu_memory_cache split_page_cache; 190 uint64_t split_page_chunk_size; 191 192 struct kvm_arch *arch; 193 194 /* 195 * For a shadow stage-2 MMU, the virtual vttbr used by the 196 * host to parse the guest S2. 197 * This either contains: 198 * - the virtual VTTBR programmed by the guest hypervisor with 199 * CnP cleared 200 * - The value 1 (VMID=0, BADDR=0, CnP=1) if invalid 201 * 202 * We also cache the full VTCR which gets used for TLB invalidation, 203 * taking the ARM ARM's "Any of the bits in VTCR_EL2 are permitted 204 * to be cached in a TLB" to the letter. 205 */ 206 u64 tlb_vttbr; 207 u64 tlb_vtcr; 208 209 /* 210 * true when this represents a nested context where virtual 211 * HCR_EL2.VM == 1 212 */ 213 bool nested_stage2_enabled; 214 215 /* 216 * true when this MMU needs to be unmapped before being used for a new 217 * purpose. 218 */ 219 bool pending_unmap; 220 221 /* 222 * 0: Nobody is currently using this, check vttbr for validity 223 * >0: Somebody is actively using this. 224 */ 225 atomic_t refcnt; 226 }; 227 228 struct kvm_arch_memory_slot { 229 }; 230 231 /** 232 * struct kvm_smccc_features: Descriptor of the hypercall services exposed to the guests 233 * 234 * @std_bmap: Bitmap of standard secure service calls 235 * @std_hyp_bmap: Bitmap of standard hypervisor service calls 236 * @vendor_hyp_bmap: Bitmap of vendor specific hypervisor service calls 237 */ 238 struct kvm_smccc_features { 239 unsigned long std_bmap; 240 unsigned long std_hyp_bmap; 241 unsigned long vendor_hyp_bmap; 242 }; 243 244 typedef unsigned int pkvm_handle_t; 245 246 struct kvm_protected_vm { 247 pkvm_handle_t handle; 248 struct kvm_hyp_memcache teardown_mc; 249 bool enabled; 250 }; 251 252 struct kvm_mpidr_data { 253 u64 mpidr_mask; 254 DECLARE_FLEX_ARRAY(u16, cmpidr_to_idx); 255 }; 256 257 static inline u16 kvm_mpidr_index(struct kvm_mpidr_data *data, u64 mpidr) 258 { 259 unsigned long index = 0, mask = data->mpidr_mask; 260 unsigned long aff = mpidr & MPIDR_HWID_BITMASK; 261 262 bitmap_gather(&index, &aff, &mask, fls(mask)); 263 264 return index; 265 } 266 267 struct kvm_sysreg_masks; 268 269 enum fgt_group_id { 270 __NO_FGT_GROUP__, 271 HFGxTR_GROUP, 272 HDFGRTR_GROUP, 273 HDFGWTR_GROUP = HDFGRTR_GROUP, 274 HFGITR_GROUP, 275 HAFGRTR_GROUP, 276 277 /* Must be last */ 278 __NR_FGT_GROUP_IDS__ 279 }; 280 281 struct kvm_arch { 282 struct kvm_s2_mmu mmu; 283 284 /* 285 * Fine-Grained UNDEF, mimicking the FGT layout defined by the 286 * architecture. We track them globally, as we present the 287 * same feature-set to all vcpus. 288 * 289 * Index 0 is currently spare. 290 */ 291 u64 fgu[__NR_FGT_GROUP_IDS__]; 292 293 /* 294 * Stage 2 paging state for VMs with nested S2 using a virtual 295 * VMID. 296 */ 297 struct kvm_s2_mmu *nested_mmus; 298 size_t nested_mmus_size; 299 int nested_mmus_next; 300 301 /* Interrupt controller */ 302 struct vgic_dist vgic; 303 304 /* Timers */ 305 struct arch_timer_vm_data timer_data; 306 307 /* Mandated version of PSCI */ 308 u32 psci_version; 309 310 /* Protects VM-scoped configuration data */ 311 struct mutex config_lock; 312 313 /* 314 * If we encounter a data abort without valid instruction syndrome 315 * information, report this to user space. User space can (and 316 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is 317 * supported. 318 */ 319 #define KVM_ARCH_FLAG_RETURN_NISV_IO_ABORT_TO_USER 0 320 /* Memory Tagging Extension enabled for the guest */ 321 #define KVM_ARCH_FLAG_MTE_ENABLED 1 322 /* At least one vCPU has ran in the VM */ 323 #define KVM_ARCH_FLAG_HAS_RAN_ONCE 2 324 /* The vCPU feature set for the VM is configured */ 325 #define KVM_ARCH_FLAG_VCPU_FEATURES_CONFIGURED 3 326 /* PSCI SYSTEM_SUSPEND enabled for the guest */ 327 #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED 4 328 /* VM counter offset */ 329 #define KVM_ARCH_FLAG_VM_COUNTER_OFFSET 5 330 /* Timer PPIs made immutable */ 331 #define KVM_ARCH_FLAG_TIMER_PPIS_IMMUTABLE 6 332 /* Initial ID reg values loaded */ 333 #define KVM_ARCH_FLAG_ID_REGS_INITIALIZED 7 334 /* Fine-Grained UNDEF initialised */ 335 #define KVM_ARCH_FLAG_FGU_INITIALIZED 8 336 unsigned long flags; 337 338 /* VM-wide vCPU feature set */ 339 DECLARE_BITMAP(vcpu_features, KVM_VCPU_MAX_FEATURES); 340 341 /* MPIDR to vcpu index mapping, optional */ 342 struct kvm_mpidr_data *mpidr_data; 343 344 /* 345 * VM-wide PMU filter, implemented as a bitmap and big enough for 346 * up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+). 347 */ 348 unsigned long *pmu_filter; 349 struct arm_pmu *arm_pmu; 350 351 cpumask_var_t supported_cpus; 352 353 /* PMCR_EL0.N value for the guest */ 354 u8 pmcr_n; 355 356 /* Iterator for idreg debugfs */ 357 u8 idreg_debugfs_iter; 358 359 /* Hypercall features firmware registers' descriptor */ 360 struct kvm_smccc_features smccc_feat; 361 struct maple_tree smccc_filter; 362 363 /* 364 * Emulated CPU ID registers per VM 365 * (Op0, Op1, CRn, CRm, Op2) of the ID registers to be saved in it 366 * is (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8. 367 * 368 * These emulated idregs are VM-wide, but accessed from the context of a vCPU. 369 * Atomic access to multiple idregs are guarded by kvm_arch.config_lock. 370 */ 371 #define IDREG_IDX(id) (((sys_reg_CRm(id) - 1) << 3) | sys_reg_Op2(id)) 372 #define KVM_ARM_ID_REG_NUM (IDREG_IDX(sys_reg(3, 0, 0, 7, 7)) + 1) 373 u64 id_regs[KVM_ARM_ID_REG_NUM]; 374 375 u64 ctr_el0; 376 377 /* Masks for VNCR-backed and general EL2 sysregs */ 378 struct kvm_sysreg_masks *sysreg_masks; 379 380 /* 381 * For an untrusted host VM, 'pkvm.handle' is used to lookup 382 * the associated pKVM instance in the hypervisor. 383 */ 384 struct kvm_protected_vm pkvm; 385 }; 386 387 struct kvm_vcpu_fault_info { 388 u64 esr_el2; /* Hyp Syndrom Register */ 389 u64 far_el2; /* Hyp Fault Address Register */ 390 u64 hpfar_el2; /* Hyp IPA Fault Address Register */ 391 u64 disr_el1; /* Deferred [SError] Status Register */ 392 }; 393 394 /* 395 * VNCR() just places the VNCR_capable registers in the enum after 396 * __VNCR_START__, and the value (after correction) to be an 8-byte offset 397 * from the VNCR base. As we don't require the enum to be otherwise ordered, 398 * we need the terrible hack below to ensure that we correctly size the 399 * sys_regs array, no matter what. 400 * 401 * The __MAX__ macro has been lifted from Sean Eron Anderson's wonderful 402 * treasure trove of bit hacks: 403 * https://graphics.stanford.edu/~seander/bithacks.html#IntegerMinOrMax 404 */ 405 #define __MAX__(x,y) ((x) ^ (((x) ^ (y)) & -((x) < (y)))) 406 #define VNCR(r) \ 407 __before_##r, \ 408 r = __VNCR_START__ + ((VNCR_ ## r) / 8), \ 409 __after_##r = __MAX__(__before_##r - 1, r) 410 411 #define MARKER(m) \ 412 m, __after_##m = m - 1 413 414 enum vcpu_sysreg { 415 __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ 416 MPIDR_EL1, /* MultiProcessor Affinity Register */ 417 CLIDR_EL1, /* Cache Level ID Register */ 418 CSSELR_EL1, /* Cache Size Selection Register */ 419 TPIDR_EL0, /* Thread ID, User R/W */ 420 TPIDRRO_EL0, /* Thread ID, User R/O */ 421 TPIDR_EL1, /* Thread ID, Privileged */ 422 CNTKCTL_EL1, /* Timer Control Register (EL1) */ 423 PAR_EL1, /* Physical Address Register */ 424 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ 425 OSLSR_EL1, /* OS Lock Status Register */ 426 DISR_EL1, /* Deferred Interrupt Status Register */ 427 428 /* Performance Monitors Registers */ 429 PMCR_EL0, /* Control Register */ 430 PMSELR_EL0, /* Event Counter Selection Register */ 431 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */ 432 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30, 433 PMCCNTR_EL0, /* Cycle Counter Register */ 434 PMEVTYPER0_EL0, /* Event Type Register (0-30) */ 435 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30, 436 PMCCFILTR_EL0, /* Cycle Count Filter Register */ 437 PMCNTENSET_EL0, /* Count Enable Set Register */ 438 PMINTENSET_EL1, /* Interrupt Enable Set Register */ 439 PMOVSSET_EL0, /* Overflow Flag Status Set Register */ 440 PMUSERENR_EL0, /* User Enable Register */ 441 442 /* Pointer Authentication Registers in a strict increasing order. */ 443 APIAKEYLO_EL1, 444 APIAKEYHI_EL1, 445 APIBKEYLO_EL1, 446 APIBKEYHI_EL1, 447 APDAKEYLO_EL1, 448 APDAKEYHI_EL1, 449 APDBKEYLO_EL1, 450 APDBKEYHI_EL1, 451 APGAKEYLO_EL1, 452 APGAKEYHI_EL1, 453 454 /* Memory Tagging Extension registers */ 455 RGSR_EL1, /* Random Allocation Tag Seed Register */ 456 GCR_EL1, /* Tag Control Register */ 457 TFSRE0_EL1, /* Tag Fault Status Register (EL0) */ 458 459 POR_EL0, /* Permission Overlay Register 0 (EL0) */ 460 461 /* FP/SIMD/SVE */ 462 SVCR, 463 FPMR, 464 465 /* 32bit specific registers. */ 466 DACR32_EL2, /* Domain Access Control Register */ 467 IFSR32_EL2, /* Instruction Fault Status Register */ 468 FPEXC32_EL2, /* Floating-Point Exception Control Register */ 469 DBGVCR32_EL2, /* Debug Vector Catch Register */ 470 471 /* EL2 registers */ 472 SCTLR_EL2, /* System Control Register (EL2) */ 473 ACTLR_EL2, /* Auxiliary Control Register (EL2) */ 474 MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */ 475 CPTR_EL2, /* Architectural Feature Trap Register (EL2) */ 476 HACR_EL2, /* Hypervisor Auxiliary Control Register */ 477 ZCR_EL2, /* SVE Control Register (EL2) */ 478 TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */ 479 TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */ 480 TCR_EL2, /* Translation Control Register (EL2) */ 481 PIRE0_EL2, /* Permission Indirection Register 0 (EL2) */ 482 PIR_EL2, /* Permission Indirection Register 1 (EL2) */ 483 SPSR_EL2, /* EL2 saved program status register */ 484 ELR_EL2, /* EL2 exception link register */ 485 AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */ 486 AFSR1_EL2, /* Auxiliary Fault Status Register 1 (EL2) */ 487 ESR_EL2, /* Exception Syndrome Register (EL2) */ 488 FAR_EL2, /* Fault Address Register (EL2) */ 489 HPFAR_EL2, /* Hypervisor IPA Fault Address Register */ 490 MAIR_EL2, /* Memory Attribute Indirection Register (EL2) */ 491 AMAIR_EL2, /* Auxiliary Memory Attribute Indirection Register (EL2) */ 492 VBAR_EL2, /* Vector Base Address Register (EL2) */ 493 RVBAR_EL2, /* Reset Vector Base Address Register */ 494 CONTEXTIDR_EL2, /* Context ID Register (EL2) */ 495 CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */ 496 SP_EL2, /* EL2 Stack Pointer */ 497 CNTHP_CTL_EL2, 498 CNTHP_CVAL_EL2, 499 CNTHV_CTL_EL2, 500 CNTHV_CVAL_EL2, 501 502 /* Anything from this can be RES0/RES1 sanitised */ 503 MARKER(__SANITISED_REG_START__), 504 TCR2_EL2, /* Extended Translation Control Register (EL2) */ 505 506 /* Any VNCR-capable reg goes after this point */ 507 MARKER(__VNCR_START__), 508 509 VNCR(SCTLR_EL1),/* System Control Register */ 510 VNCR(ACTLR_EL1),/* Auxiliary Control Register */ 511 VNCR(CPACR_EL1),/* Coprocessor Access Control */ 512 VNCR(ZCR_EL1), /* SVE Control */ 513 VNCR(TTBR0_EL1),/* Translation Table Base Register 0 */ 514 VNCR(TTBR1_EL1),/* Translation Table Base Register 1 */ 515 VNCR(TCR_EL1), /* Translation Control Register */ 516 VNCR(TCR2_EL1), /* Extended Translation Control Register */ 517 VNCR(ESR_EL1), /* Exception Syndrome Register */ 518 VNCR(AFSR0_EL1),/* Auxiliary Fault Status Register 0 */ 519 VNCR(AFSR1_EL1),/* Auxiliary Fault Status Register 1 */ 520 VNCR(FAR_EL1), /* Fault Address Register */ 521 VNCR(MAIR_EL1), /* Memory Attribute Indirection Register */ 522 VNCR(VBAR_EL1), /* Vector Base Address Register */ 523 VNCR(CONTEXTIDR_EL1), /* Context ID Register */ 524 VNCR(AMAIR_EL1),/* Aux Memory Attribute Indirection Register */ 525 VNCR(MDSCR_EL1),/* Monitor Debug System Control Register */ 526 VNCR(ELR_EL1), 527 VNCR(SP_EL1), 528 VNCR(SPSR_EL1), 529 VNCR(TFSR_EL1), /* Tag Fault Status Register (EL1) */ 530 VNCR(VPIDR_EL2),/* Virtualization Processor ID Register */ 531 VNCR(VMPIDR_EL2),/* Virtualization Multiprocessor ID Register */ 532 VNCR(HCR_EL2), /* Hypervisor Configuration Register */ 533 VNCR(HSTR_EL2), /* Hypervisor System Trap Register */ 534 VNCR(VTTBR_EL2),/* Virtualization Translation Table Base Register */ 535 VNCR(VTCR_EL2), /* Virtualization Translation Control Register */ 536 VNCR(TPIDR_EL2),/* EL2 Software Thread ID Register */ 537 VNCR(HCRX_EL2), /* Extended Hypervisor Configuration Register */ 538 539 /* Permission Indirection Extension registers */ 540 VNCR(PIR_EL1), /* Permission Indirection Register 1 (EL1) */ 541 VNCR(PIRE0_EL1), /* Permission Indirection Register 0 (EL1) */ 542 543 VNCR(POR_EL1), /* Permission Overlay Register 1 (EL1) */ 544 545 VNCR(HFGRTR_EL2), 546 VNCR(HFGWTR_EL2), 547 VNCR(HFGITR_EL2), 548 VNCR(HDFGRTR_EL2), 549 VNCR(HDFGWTR_EL2), 550 VNCR(HAFGRTR_EL2), 551 552 VNCR(CNTVOFF_EL2), 553 VNCR(CNTV_CVAL_EL0), 554 VNCR(CNTV_CTL_EL0), 555 VNCR(CNTP_CVAL_EL0), 556 VNCR(CNTP_CTL_EL0), 557 558 VNCR(ICH_HCR_EL2), 559 560 NR_SYS_REGS /* Nothing after this line! */ 561 }; 562 563 struct kvm_sysreg_masks { 564 struct { 565 u64 res0; 566 u64 res1; 567 } mask[NR_SYS_REGS - __SANITISED_REG_START__]; 568 }; 569 570 struct kvm_cpu_context { 571 struct user_pt_regs regs; /* sp = sp_el0 */ 572 573 u64 spsr_abt; 574 u64 spsr_und; 575 u64 spsr_irq; 576 u64 spsr_fiq; 577 578 struct user_fpsimd_state fp_regs; 579 580 u64 sys_regs[NR_SYS_REGS]; 581 582 struct kvm_vcpu *__hyp_running_vcpu; 583 584 /* This pointer has to be 4kB aligned. */ 585 u64 *vncr_array; 586 }; 587 588 struct cpu_sve_state { 589 __u64 zcr_el1; 590 591 /* 592 * Ordering is important since __sve_save_state/__sve_restore_state 593 * relies on it. 594 */ 595 __u32 fpsr; 596 __u32 fpcr; 597 598 /* Must be SVE_VQ_BYTES (128 bit) aligned. */ 599 __u8 sve_regs[]; 600 }; 601 602 /* 603 * This structure is instantiated on a per-CPU basis, and contains 604 * data that is: 605 * 606 * - tied to a single physical CPU, and 607 * - either have a lifetime that does not extend past vcpu_put() 608 * - or is an invariant for the lifetime of the system 609 * 610 * Use host_data_ptr(field) as a way to access a pointer to such a 611 * field. 612 */ 613 struct kvm_host_data { 614 struct kvm_cpu_context host_ctxt; 615 616 /* 617 * All pointers in this union are hyp VA. 618 * sve_state is only used in pKVM and if system_supports_sve(). 619 */ 620 union { 621 struct user_fpsimd_state *fpsimd_state; 622 struct cpu_sve_state *sve_state; 623 }; 624 625 union { 626 /* HYP VA pointer to the host storage for FPMR */ 627 u64 *fpmr_ptr; 628 /* 629 * Used by pKVM only, as it needs to provide storage 630 * for the host 631 */ 632 u64 fpmr; 633 }; 634 635 /* Ownership of the FP regs */ 636 enum { 637 FP_STATE_FREE, 638 FP_STATE_HOST_OWNED, 639 FP_STATE_GUEST_OWNED, 640 } fp_owner; 641 642 /* 643 * host_debug_state contains the host registers which are 644 * saved and restored during world switches. 645 */ 646 struct { 647 /* {Break,watch}point registers */ 648 struct kvm_guest_debug_arch regs; 649 /* Statistical profiling extension */ 650 u64 pmscr_el1; 651 /* Self-hosted trace */ 652 u64 trfcr_el1; 653 /* Values of trap registers for the host before guest entry. */ 654 u64 mdcr_el2; 655 } host_debug_state; 656 }; 657 658 struct kvm_host_psci_config { 659 /* PSCI version used by host. */ 660 u32 version; 661 u32 smccc_version; 662 663 /* Function IDs used by host if version is v0.1. */ 664 struct psci_0_1_function_ids function_ids_0_1; 665 666 bool psci_0_1_cpu_suspend_implemented; 667 bool psci_0_1_cpu_on_implemented; 668 bool psci_0_1_cpu_off_implemented; 669 bool psci_0_1_migrate_implemented; 670 }; 671 672 extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config); 673 #define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config) 674 675 extern s64 kvm_nvhe_sym(hyp_physvirt_offset); 676 #define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset) 677 678 extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS]; 679 #define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map) 680 681 struct vcpu_reset_state { 682 unsigned long pc; 683 unsigned long r0; 684 bool be; 685 bool reset; 686 }; 687 688 struct kvm_vcpu_arch { 689 struct kvm_cpu_context ctxt; 690 691 /* 692 * Guest floating point state 693 * 694 * The architecture has two main floating point extensions, 695 * the original FPSIMD and SVE. These have overlapping 696 * register views, with the FPSIMD V registers occupying the 697 * low 128 bits of the SVE Z registers. When the core 698 * floating point code saves the register state of a task it 699 * records which view it saved in fp_type. 700 */ 701 void *sve_state; 702 enum fp_type fp_type; 703 unsigned int sve_max_vl; 704 705 /* Stage 2 paging state used by the hardware on next switch */ 706 struct kvm_s2_mmu *hw_mmu; 707 708 /* Values of trap registers for the guest. */ 709 u64 hcr_el2; 710 u64 hcrx_el2; 711 u64 mdcr_el2; 712 u64 cptr_el2; 713 714 /* Exception Information */ 715 struct kvm_vcpu_fault_info fault; 716 717 /* Configuration flags, set once and for all before the vcpu can run */ 718 u8 cflags; 719 720 /* Input flags to the hypervisor code, potentially cleared after use */ 721 u8 iflags; 722 723 /* State flags for kernel bookkeeping, unused by the hypervisor code */ 724 u8 sflags; 725 726 /* 727 * Don't run the guest (internal implementation need). 728 * 729 * Contrary to the flags above, this is set/cleared outside of 730 * a vcpu context, and thus cannot be mixed with the flags 731 * themselves (or the flag accesses need to be made atomic). 732 */ 733 bool pause; 734 735 /* 736 * We maintain more than a single set of debug registers to support 737 * debugging the guest from the host and to maintain separate host and 738 * guest state during world switches. vcpu_debug_state are the debug 739 * registers of the vcpu as the guest sees them. 740 * 741 * external_debug_state contains the debug values we want to debug the 742 * guest. This is set via the KVM_SET_GUEST_DEBUG ioctl. 743 * 744 * debug_ptr points to the set of debug registers that should be loaded 745 * onto the hardware when running the guest. 746 */ 747 struct kvm_guest_debug_arch *debug_ptr; 748 struct kvm_guest_debug_arch vcpu_debug_state; 749 struct kvm_guest_debug_arch external_debug_state; 750 751 /* VGIC state */ 752 struct vgic_cpu vgic_cpu; 753 struct arch_timer_cpu timer_cpu; 754 struct kvm_pmu pmu; 755 756 /* 757 * Guest registers we preserve during guest debugging. 758 * 759 * These shadow registers are updated by the kvm_handle_sys_reg 760 * trap handler if the guest accesses or updates them while we 761 * are using guest debug. 762 */ 763 struct { 764 u32 mdscr_el1; 765 bool pstate_ss; 766 } guest_debug_preserved; 767 768 /* vcpu power state */ 769 struct kvm_mp_state mp_state; 770 spinlock_t mp_state_lock; 771 772 /* Cache some mmu pages needed inside spinlock regions */ 773 struct kvm_mmu_memory_cache mmu_page_cache; 774 775 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */ 776 u64 vsesr_el2; 777 778 /* Additional reset state */ 779 struct vcpu_reset_state reset_state; 780 781 /* Guest PV state */ 782 struct { 783 u64 last_steal; 784 gpa_t base; 785 } steal; 786 787 /* Per-vcpu CCSIDR override or NULL */ 788 u32 *ccsidr; 789 }; 790 791 /* 792 * Each 'flag' is composed of a comma-separated triplet: 793 * 794 * - the flag-set it belongs to in the vcpu->arch structure 795 * - the value for that flag 796 * - the mask for that flag 797 * 798 * __vcpu_single_flag() builds such a triplet for a single-bit flag. 799 * unpack_vcpu_flag() extract the flag value from the triplet for 800 * direct use outside of the flag accessors. 801 */ 802 #define __vcpu_single_flag(_set, _f) _set, (_f), (_f) 803 804 #define __unpack_flag(_set, _f, _m) _f 805 #define unpack_vcpu_flag(...) __unpack_flag(__VA_ARGS__) 806 807 #define __build_check_flag(v, flagset, f, m) \ 808 do { \ 809 typeof(v->arch.flagset) *_fset; \ 810 \ 811 /* Check that the flags fit in the mask */ \ 812 BUILD_BUG_ON(HWEIGHT(m) != HWEIGHT((f) | (m))); \ 813 /* Check that the flags fit in the type */ \ 814 BUILD_BUG_ON((sizeof(*_fset) * 8) <= __fls(m)); \ 815 } while (0) 816 817 #define __vcpu_get_flag(v, flagset, f, m) \ 818 ({ \ 819 __build_check_flag(v, flagset, f, m); \ 820 \ 821 READ_ONCE(v->arch.flagset) & (m); \ 822 }) 823 824 /* 825 * Note that the set/clear accessors must be preempt-safe in order to 826 * avoid nesting them with load/put which also manipulate flags... 827 */ 828 #ifdef __KVM_NVHE_HYPERVISOR__ 829 /* the nVHE hypervisor is always non-preemptible */ 830 #define __vcpu_flags_preempt_disable() 831 #define __vcpu_flags_preempt_enable() 832 #else 833 #define __vcpu_flags_preempt_disable() preempt_disable() 834 #define __vcpu_flags_preempt_enable() preempt_enable() 835 #endif 836 837 #define __vcpu_set_flag(v, flagset, f, m) \ 838 do { \ 839 typeof(v->arch.flagset) *fset; \ 840 \ 841 __build_check_flag(v, flagset, f, m); \ 842 \ 843 fset = &v->arch.flagset; \ 844 __vcpu_flags_preempt_disable(); \ 845 if (HWEIGHT(m) > 1) \ 846 *fset &= ~(m); \ 847 *fset |= (f); \ 848 __vcpu_flags_preempt_enable(); \ 849 } while (0) 850 851 #define __vcpu_clear_flag(v, flagset, f, m) \ 852 do { \ 853 typeof(v->arch.flagset) *fset; \ 854 \ 855 __build_check_flag(v, flagset, f, m); \ 856 \ 857 fset = &v->arch.flagset; \ 858 __vcpu_flags_preempt_disable(); \ 859 *fset &= ~(m); \ 860 __vcpu_flags_preempt_enable(); \ 861 } while (0) 862 863 #define vcpu_get_flag(v, ...) __vcpu_get_flag((v), __VA_ARGS__) 864 #define vcpu_set_flag(v, ...) __vcpu_set_flag((v), __VA_ARGS__) 865 #define vcpu_clear_flag(v, ...) __vcpu_clear_flag((v), __VA_ARGS__) 866 867 /* SVE exposed to guest */ 868 #define GUEST_HAS_SVE __vcpu_single_flag(cflags, BIT(0)) 869 /* SVE config completed */ 870 #define VCPU_SVE_FINALIZED __vcpu_single_flag(cflags, BIT(1)) 871 /* PTRAUTH exposed to guest */ 872 #define GUEST_HAS_PTRAUTH __vcpu_single_flag(cflags, BIT(2)) 873 /* KVM_ARM_VCPU_INIT completed */ 874 #define VCPU_INITIALIZED __vcpu_single_flag(cflags, BIT(3)) 875 876 /* Exception pending */ 877 #define PENDING_EXCEPTION __vcpu_single_flag(iflags, BIT(0)) 878 /* 879 * PC increment. Overlaps with EXCEPT_MASK on purpose so that it can't 880 * be set together with an exception... 881 */ 882 #define INCREMENT_PC __vcpu_single_flag(iflags, BIT(1)) 883 /* Target EL/MODE (not a single flag, but let's abuse the macro) */ 884 #define EXCEPT_MASK __vcpu_single_flag(iflags, GENMASK(3, 1)) 885 886 /* Helpers to encode exceptions with minimum fuss */ 887 #define __EXCEPT_MASK_VAL unpack_vcpu_flag(EXCEPT_MASK) 888 #define __EXCEPT_SHIFT __builtin_ctzl(__EXCEPT_MASK_VAL) 889 #define __vcpu_except_flags(_f) iflags, (_f << __EXCEPT_SHIFT), __EXCEPT_MASK_VAL 890 891 /* 892 * When PENDING_EXCEPTION is set, EXCEPT_MASK can take the following 893 * values: 894 * 895 * For AArch32 EL1: 896 */ 897 #define EXCEPT_AA32_UND __vcpu_except_flags(0) 898 #define EXCEPT_AA32_IABT __vcpu_except_flags(1) 899 #define EXCEPT_AA32_DABT __vcpu_except_flags(2) 900 /* For AArch64: */ 901 #define EXCEPT_AA64_EL1_SYNC __vcpu_except_flags(0) 902 #define EXCEPT_AA64_EL1_IRQ __vcpu_except_flags(1) 903 #define EXCEPT_AA64_EL1_FIQ __vcpu_except_flags(2) 904 #define EXCEPT_AA64_EL1_SERR __vcpu_except_flags(3) 905 /* For AArch64 with NV: */ 906 #define EXCEPT_AA64_EL2_SYNC __vcpu_except_flags(4) 907 #define EXCEPT_AA64_EL2_IRQ __vcpu_except_flags(5) 908 #define EXCEPT_AA64_EL2_FIQ __vcpu_except_flags(6) 909 #define EXCEPT_AA64_EL2_SERR __vcpu_except_flags(7) 910 /* Guest debug is live */ 911 #define DEBUG_DIRTY __vcpu_single_flag(iflags, BIT(4)) 912 /* Save SPE context if active */ 913 #define DEBUG_STATE_SAVE_SPE __vcpu_single_flag(iflags, BIT(5)) 914 /* Save TRBE context if active */ 915 #define DEBUG_STATE_SAVE_TRBE __vcpu_single_flag(iflags, BIT(6)) 916 917 /* SVE enabled for host EL0 */ 918 #define HOST_SVE_ENABLED __vcpu_single_flag(sflags, BIT(0)) 919 /* SME enabled for EL0 */ 920 #define HOST_SME_ENABLED __vcpu_single_flag(sflags, BIT(1)) 921 /* Physical CPU not in supported_cpus */ 922 #define ON_UNSUPPORTED_CPU __vcpu_single_flag(sflags, BIT(2)) 923 /* WFIT instruction trapped */ 924 #define IN_WFIT __vcpu_single_flag(sflags, BIT(3)) 925 /* vcpu system registers loaded on physical CPU */ 926 #define SYSREGS_ON_CPU __vcpu_single_flag(sflags, BIT(4)) 927 /* Software step state is Active-pending */ 928 #define DBG_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(5)) 929 /* PMUSERENR for the guest EL0 is on physical CPU */ 930 #define PMUSERENR_ON_CPU __vcpu_single_flag(sflags, BIT(6)) 931 /* WFI instruction trapped */ 932 #define IN_WFI __vcpu_single_flag(sflags, BIT(7)) 933 934 935 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */ 936 #define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) + \ 937 sve_ffr_offset((vcpu)->arch.sve_max_vl)) 938 939 #define vcpu_sve_max_vq(vcpu) sve_vq_from_vl((vcpu)->arch.sve_max_vl) 940 941 #define vcpu_sve_zcr_elx(vcpu) \ 942 (unlikely(is_hyp_ctxt(vcpu)) ? ZCR_EL2 : ZCR_EL1) 943 944 #define vcpu_sve_state_size(vcpu) ({ \ 945 size_t __size_ret; \ 946 unsigned int __vcpu_vq; \ 947 \ 948 if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) { \ 949 __size_ret = 0; \ 950 } else { \ 951 __vcpu_vq = vcpu_sve_max_vq(vcpu); \ 952 __size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq); \ 953 } \ 954 \ 955 __size_ret; \ 956 }) 957 958 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \ 959 KVM_GUESTDBG_USE_SW_BP | \ 960 KVM_GUESTDBG_USE_HW | \ 961 KVM_GUESTDBG_SINGLESTEP) 962 963 #define vcpu_has_sve(vcpu) (system_supports_sve() && \ 964 vcpu_get_flag(vcpu, GUEST_HAS_SVE)) 965 966 #ifdef CONFIG_ARM64_PTR_AUTH 967 #define vcpu_has_ptrauth(vcpu) \ 968 ((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) || \ 969 cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) && \ 970 vcpu_get_flag(vcpu, GUEST_HAS_PTRAUTH)) 971 #else 972 #define vcpu_has_ptrauth(vcpu) false 973 #endif 974 975 #define vcpu_on_unsupported_cpu(vcpu) \ 976 vcpu_get_flag(vcpu, ON_UNSUPPORTED_CPU) 977 978 #define vcpu_set_on_unsupported_cpu(vcpu) \ 979 vcpu_set_flag(vcpu, ON_UNSUPPORTED_CPU) 980 981 #define vcpu_clear_on_unsupported_cpu(vcpu) \ 982 vcpu_clear_flag(vcpu, ON_UNSUPPORTED_CPU) 983 984 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.regs) 985 986 /* 987 * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the 988 * memory backed version of a register, and not the one most recently 989 * accessed by a running VCPU. For example, for userspace access or 990 * for system registers that are never context switched, but only 991 * emulated. 992 * 993 * Don't bother with VNCR-based accesses in the nVHE code, it has no 994 * business dealing with NV. 995 */ 996 static inline u64 *___ctxt_sys_reg(const struct kvm_cpu_context *ctxt, int r) 997 { 998 #if !defined (__KVM_NVHE_HYPERVISOR__) 999 if (unlikely(cpus_have_final_cap(ARM64_HAS_NESTED_VIRT) && 1000 r >= __VNCR_START__ && ctxt->vncr_array)) 1001 return &ctxt->vncr_array[r - __VNCR_START__]; 1002 #endif 1003 return (u64 *)&ctxt->sys_regs[r]; 1004 } 1005 1006 #define __ctxt_sys_reg(c,r) \ 1007 ({ \ 1008 BUILD_BUG_ON(__builtin_constant_p(r) && \ 1009 (r) >= NR_SYS_REGS); \ 1010 ___ctxt_sys_reg(c, r); \ 1011 }) 1012 1013 #define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r)) 1014 1015 u64 kvm_vcpu_apply_reg_masks(const struct kvm_vcpu *, enum vcpu_sysreg, u64); 1016 #define __vcpu_sys_reg(v,r) \ 1017 (*({ \ 1018 const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \ 1019 u64 *__r = __ctxt_sys_reg(ctxt, (r)); \ 1020 if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \ 1021 *__r = kvm_vcpu_apply_reg_masks((v), (r), *__r);\ 1022 __r; \ 1023 })) 1024 1025 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg); 1026 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg); 1027 1028 static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val) 1029 { 1030 /* 1031 * *** VHE ONLY *** 1032 * 1033 * System registers listed in the switch are not saved on every 1034 * exit from the guest but are only saved on vcpu_put. 1035 * 1036 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but 1037 * should never be listed below, because the guest cannot modify its 1038 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's 1039 * thread when emulating cross-VCPU communication. 1040 */ 1041 if (!has_vhe()) 1042 return false; 1043 1044 switch (reg) { 1045 case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break; 1046 case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break; 1047 case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break; 1048 case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break; 1049 case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break; 1050 case TCR2_EL1: *val = read_sysreg_s(SYS_TCR2_EL12); break; 1051 case PIR_EL1: *val = read_sysreg_s(SYS_PIR_EL12); break; 1052 case PIRE0_EL1: *val = read_sysreg_s(SYS_PIRE0_EL12); break; 1053 case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break; 1054 case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break; 1055 case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break; 1056 case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break; 1057 case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break; 1058 case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break; 1059 case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break; 1060 case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break; 1061 case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break; 1062 case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break; 1063 case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break; 1064 case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break; 1065 case ELR_EL1: *val = read_sysreg_s(SYS_ELR_EL12); break; 1066 case SPSR_EL1: *val = read_sysreg_s(SYS_SPSR_EL12); break; 1067 case PAR_EL1: *val = read_sysreg_par(); break; 1068 case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break; 1069 case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break; 1070 case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break; 1071 case ZCR_EL1: *val = read_sysreg_s(SYS_ZCR_EL12); break; 1072 default: return false; 1073 } 1074 1075 return true; 1076 } 1077 1078 static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg) 1079 { 1080 /* 1081 * *** VHE ONLY *** 1082 * 1083 * System registers listed in the switch are not restored on every 1084 * entry to the guest but are only restored on vcpu_load. 1085 * 1086 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but 1087 * should never be listed below, because the MPIDR should only be set 1088 * once, before running the VCPU, and never changed later. 1089 */ 1090 if (!has_vhe()) 1091 return false; 1092 1093 switch (reg) { 1094 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break; 1095 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break; 1096 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break; 1097 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break; 1098 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break; 1099 case TCR2_EL1: write_sysreg_s(val, SYS_TCR2_EL12); break; 1100 case PIR_EL1: write_sysreg_s(val, SYS_PIR_EL12); break; 1101 case PIRE0_EL1: write_sysreg_s(val, SYS_PIRE0_EL12); break; 1102 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break; 1103 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break; 1104 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break; 1105 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break; 1106 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break; 1107 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break; 1108 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break; 1109 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break; 1110 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break; 1111 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break; 1112 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break; 1113 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break; 1114 case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break; 1115 case SPSR_EL1: write_sysreg_s(val, SYS_SPSR_EL12); break; 1116 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break; 1117 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break; 1118 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break; 1119 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break; 1120 case ZCR_EL1: write_sysreg_s(val, SYS_ZCR_EL12); break; 1121 default: return false; 1122 } 1123 1124 return true; 1125 } 1126 1127 struct kvm_vm_stat { 1128 struct kvm_vm_stat_generic generic; 1129 }; 1130 1131 struct kvm_vcpu_stat { 1132 struct kvm_vcpu_stat_generic generic; 1133 u64 hvc_exit_stat; 1134 u64 wfe_exit_stat; 1135 u64 wfi_exit_stat; 1136 u64 mmio_exit_user; 1137 u64 mmio_exit_kernel; 1138 u64 signal_exits; 1139 u64 exits; 1140 }; 1141 1142 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); 1143 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); 1144 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 1145 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 1146 1147 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu); 1148 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices); 1149 1150 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu, 1151 struct kvm_vcpu_events *events); 1152 1153 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu, 1154 struct kvm_vcpu_events *events); 1155 1156 void kvm_arm_halt_guest(struct kvm *kvm); 1157 void kvm_arm_resume_guest(struct kvm *kvm); 1158 1159 #define vcpu_has_run_once(vcpu) !!rcu_access_pointer((vcpu)->pid) 1160 1161 #ifndef __KVM_NVHE_HYPERVISOR__ 1162 #define kvm_call_hyp_nvhe(f, ...) \ 1163 ({ \ 1164 struct arm_smccc_res res; \ 1165 \ 1166 arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f), \ 1167 ##__VA_ARGS__, &res); \ 1168 WARN_ON(res.a0 != SMCCC_RET_SUCCESS); \ 1169 \ 1170 res.a1; \ 1171 }) 1172 1173 /* 1174 * The couple of isb() below are there to guarantee the same behaviour 1175 * on VHE as on !VHE, where the eret to EL1 acts as a context 1176 * synchronization event. 1177 */ 1178 #define kvm_call_hyp(f, ...) \ 1179 do { \ 1180 if (has_vhe()) { \ 1181 f(__VA_ARGS__); \ 1182 isb(); \ 1183 } else { \ 1184 kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 1185 } \ 1186 } while(0) 1187 1188 #define kvm_call_hyp_ret(f, ...) \ 1189 ({ \ 1190 typeof(f(__VA_ARGS__)) ret; \ 1191 \ 1192 if (has_vhe()) { \ 1193 ret = f(__VA_ARGS__); \ 1194 isb(); \ 1195 } else { \ 1196 ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 1197 } \ 1198 \ 1199 ret; \ 1200 }) 1201 #else /* __KVM_NVHE_HYPERVISOR__ */ 1202 #define kvm_call_hyp(f, ...) f(__VA_ARGS__) 1203 #define kvm_call_hyp_ret(f, ...) f(__VA_ARGS__) 1204 #define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__) 1205 #endif /* __KVM_NVHE_HYPERVISOR__ */ 1206 1207 int handle_exit(struct kvm_vcpu *vcpu, int exception_index); 1208 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index); 1209 1210 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu); 1211 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu); 1212 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu); 1213 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu); 1214 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu); 1215 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu); 1216 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu); 1217 1218 void kvm_sys_regs_create_debugfs(struct kvm *kvm); 1219 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu); 1220 1221 int __init kvm_sys_reg_table_init(void); 1222 struct sys_reg_desc; 1223 int __init populate_sysreg_config(const struct sys_reg_desc *sr, 1224 unsigned int idx); 1225 int __init populate_nv_trap_config(void); 1226 1227 bool lock_all_vcpus(struct kvm *kvm); 1228 void unlock_all_vcpus(struct kvm *kvm); 1229 1230 void kvm_calculate_traps(struct kvm_vcpu *vcpu); 1231 1232 /* MMIO helpers */ 1233 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data); 1234 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len); 1235 1236 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu); 1237 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa); 1238 1239 /* 1240 * Returns true if a Performance Monitoring Interrupt (PMI), a.k.a. perf event, 1241 * arrived in guest context. For arm64, any event that arrives while a vCPU is 1242 * loaded is considered to be "in guest". 1243 */ 1244 static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu) 1245 { 1246 return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu; 1247 } 1248 1249 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu); 1250 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu); 1251 void kvm_update_stolen_time(struct kvm_vcpu *vcpu); 1252 1253 bool kvm_arm_pvtime_supported(void); 1254 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu, 1255 struct kvm_device_attr *attr); 1256 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu, 1257 struct kvm_device_attr *attr); 1258 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu, 1259 struct kvm_device_attr *attr); 1260 1261 extern unsigned int __ro_after_init kvm_arm_vmid_bits; 1262 int __init kvm_arm_vmid_alloc_init(void); 1263 void __init kvm_arm_vmid_alloc_free(void); 1264 bool kvm_arm_vmid_update(struct kvm_vmid *kvm_vmid); 1265 void kvm_arm_vmid_clear_active(void); 1266 1267 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch) 1268 { 1269 vcpu_arch->steal.base = INVALID_GPA; 1270 } 1271 1272 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch) 1273 { 1274 return (vcpu_arch->steal.base != INVALID_GPA); 1275 } 1276 1277 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome); 1278 1279 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); 1280 1281 DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data); 1282 1283 /* 1284 * How we access per-CPU host data depends on the where we access it from, 1285 * and the mode we're in: 1286 * 1287 * - VHE and nVHE hypervisor bits use their locally defined instance 1288 * 1289 * - the rest of the kernel use either the VHE or nVHE one, depending on 1290 * the mode we're running in. 1291 * 1292 * Unless we're in protected mode, fully deprivileged, and the nVHE 1293 * per-CPU stuff is exclusively accessible to the protected EL2 code. 1294 * In this case, the EL1 code uses the *VHE* data as its private state 1295 * (which makes sense in a way as there shouldn't be any shared state 1296 * between the host and the hypervisor). 1297 * 1298 * Yes, this is all totally trivial. Shoot me now. 1299 */ 1300 #if defined(__KVM_NVHE_HYPERVISOR__) || defined(__KVM_VHE_HYPERVISOR__) 1301 #define host_data_ptr(f) (&this_cpu_ptr(&kvm_host_data)->f) 1302 #else 1303 #define host_data_ptr(f) \ 1304 (static_branch_unlikely(&kvm_protected_mode_initialized) ? \ 1305 &this_cpu_ptr(&kvm_host_data)->f : \ 1306 &this_cpu_ptr_hyp_sym(kvm_host_data)->f) 1307 #endif 1308 1309 /* Check whether the FP regs are owned by the guest */ 1310 static inline bool guest_owns_fp_regs(void) 1311 { 1312 return *host_data_ptr(fp_owner) == FP_STATE_GUEST_OWNED; 1313 } 1314 1315 /* Check whether the FP regs are owned by the host */ 1316 static inline bool host_owns_fp_regs(void) 1317 { 1318 return *host_data_ptr(fp_owner) == FP_STATE_HOST_OWNED; 1319 } 1320 1321 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt) 1322 { 1323 /* The host's MPIDR is immutable, so let's set it up at boot time */ 1324 ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr(); 1325 } 1326 1327 static inline bool kvm_system_needs_idmapped_vectors(void) 1328 { 1329 return cpus_have_final_cap(ARM64_SPECTRE_V3A); 1330 } 1331 1332 static inline void kvm_arch_sync_events(struct kvm *kvm) {} 1333 1334 void kvm_arm_init_debug(void); 1335 void kvm_arm_vcpu_init_debug(struct kvm_vcpu *vcpu); 1336 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu); 1337 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu); 1338 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu); 1339 1340 #define kvm_vcpu_os_lock_enabled(vcpu) \ 1341 (!!(__vcpu_sys_reg(vcpu, OSLSR_EL1) & OSLSR_EL1_OSLK)) 1342 1343 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, 1344 struct kvm_device_attr *attr); 1345 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, 1346 struct kvm_device_attr *attr); 1347 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, 1348 struct kvm_device_attr *attr); 1349 1350 int kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm, 1351 struct kvm_arm_copy_mte_tags *copy_tags); 1352 int kvm_vm_ioctl_set_counter_offset(struct kvm *kvm, 1353 struct kvm_arm_counter_offset *offset); 1354 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, 1355 struct reg_mask_range *range); 1356 1357 /* Guest/host FPSIMD coordination helpers */ 1358 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu); 1359 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu); 1360 void kvm_arch_vcpu_ctxflush_fp(struct kvm_vcpu *vcpu); 1361 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu); 1362 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu); 1363 1364 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr) 1365 { 1366 return (!has_vhe() && attr->exclude_host); 1367 } 1368 1369 /* Flags for host debug state */ 1370 void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu); 1371 void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu); 1372 1373 #ifdef CONFIG_KVM 1374 void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr); 1375 void kvm_clr_pmu_events(u64 clr); 1376 bool kvm_set_pmuserenr(u64 val); 1377 #else 1378 static inline void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr) {} 1379 static inline void kvm_clr_pmu_events(u64 clr) {} 1380 static inline bool kvm_set_pmuserenr(u64 val) 1381 { 1382 return false; 1383 } 1384 #endif 1385 1386 void kvm_vcpu_load_vhe(struct kvm_vcpu *vcpu); 1387 void kvm_vcpu_put_vhe(struct kvm_vcpu *vcpu); 1388 1389 int __init kvm_set_ipa_limit(void); 1390 u32 kvm_get_pa_bits(struct kvm *kvm); 1391 1392 #define __KVM_HAVE_ARCH_VM_ALLOC 1393 struct kvm *kvm_arch_alloc_vm(void); 1394 1395 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS 1396 1397 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS_RANGE 1398 1399 #define kvm_vm_is_protected(kvm) (is_protected_kvm_enabled() && (kvm)->arch.pkvm.enabled) 1400 1401 #define vcpu_is_protected(vcpu) kvm_vm_is_protected((vcpu)->kvm) 1402 1403 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature); 1404 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu); 1405 1406 #define kvm_arm_vcpu_sve_finalized(vcpu) vcpu_get_flag(vcpu, VCPU_SVE_FINALIZED) 1407 1408 #define kvm_has_mte(kvm) \ 1409 (system_supports_mte() && \ 1410 test_bit(KVM_ARCH_FLAG_MTE_ENABLED, &(kvm)->arch.flags)) 1411 1412 #define kvm_supports_32bit_el0() \ 1413 (system_supports_32bit_el0() && \ 1414 !static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1415 1416 #define kvm_vm_has_ran_once(kvm) \ 1417 (test_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &(kvm)->arch.flags)) 1418 1419 static inline bool __vcpu_has_feature(const struct kvm_arch *ka, int feature) 1420 { 1421 return test_bit(feature, ka->vcpu_features); 1422 } 1423 1424 #define vcpu_has_feature(v, f) __vcpu_has_feature(&(v)->kvm->arch, (f)) 1425 1426 #define kvm_vcpu_initialized(v) vcpu_get_flag(vcpu, VCPU_INITIALIZED) 1427 1428 int kvm_trng_call(struct kvm_vcpu *vcpu); 1429 #ifdef CONFIG_KVM 1430 extern phys_addr_t hyp_mem_base; 1431 extern phys_addr_t hyp_mem_size; 1432 void __init kvm_hyp_reserve(void); 1433 #else 1434 static inline void kvm_hyp_reserve(void) { } 1435 #endif 1436 1437 void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu); 1438 bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu); 1439 1440 static inline u64 *__vm_id_reg(struct kvm_arch *ka, u32 reg) 1441 { 1442 switch (reg) { 1443 case sys_reg(3, 0, 0, 1, 0) ... sys_reg(3, 0, 0, 7, 7): 1444 return &ka->id_regs[IDREG_IDX(reg)]; 1445 case SYS_CTR_EL0: 1446 return &ka->ctr_el0; 1447 default: 1448 WARN_ON_ONCE(1); 1449 return NULL; 1450 } 1451 } 1452 1453 #define kvm_read_vm_id_reg(kvm, reg) \ 1454 ({ u64 __val = *__vm_id_reg(&(kvm)->arch, reg); __val; }) 1455 1456 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val); 1457 1458 #define __expand_field_sign_unsigned(id, fld, val) \ 1459 ((u64)SYS_FIELD_VALUE(id, fld, val)) 1460 1461 #define __expand_field_sign_signed(id, fld, val) \ 1462 ({ \ 1463 u64 __val = SYS_FIELD_VALUE(id, fld, val); \ 1464 sign_extend64(__val, id##_##fld##_WIDTH - 1); \ 1465 }) 1466 1467 #define get_idreg_field_unsigned(kvm, id, fld) \ 1468 ({ \ 1469 u64 __val = kvm_read_vm_id_reg((kvm), SYS_##id); \ 1470 FIELD_GET(id##_##fld##_MASK, __val); \ 1471 }) 1472 1473 #define get_idreg_field_signed(kvm, id, fld) \ 1474 ({ \ 1475 u64 __val = get_idreg_field_unsigned(kvm, id, fld); \ 1476 sign_extend64(__val, id##_##fld##_WIDTH - 1); \ 1477 }) 1478 1479 #define get_idreg_field_enum(kvm, id, fld) \ 1480 get_idreg_field_unsigned(kvm, id, fld) 1481 1482 #define kvm_cmp_feat_signed(kvm, id, fld, op, limit) \ 1483 (get_idreg_field_signed((kvm), id, fld) op __expand_field_sign_signed(id, fld, limit)) 1484 1485 #define kvm_cmp_feat_unsigned(kvm, id, fld, op, limit) \ 1486 (get_idreg_field_unsigned((kvm), id, fld) op __expand_field_sign_unsigned(id, fld, limit)) 1487 1488 #define kvm_cmp_feat(kvm, id, fld, op, limit) \ 1489 (id##_##fld##_SIGNED ? \ 1490 kvm_cmp_feat_signed(kvm, id, fld, op, limit) : \ 1491 kvm_cmp_feat_unsigned(kvm, id, fld, op, limit)) 1492 1493 #define kvm_has_feat(kvm, id, fld, limit) \ 1494 kvm_cmp_feat(kvm, id, fld, >=, limit) 1495 1496 #define kvm_has_feat_enum(kvm, id, fld, val) \ 1497 kvm_cmp_feat_unsigned(kvm, id, fld, ==, val) 1498 1499 #define kvm_has_feat_range(kvm, id, fld, min, max) \ 1500 (kvm_cmp_feat(kvm, id, fld, >=, min) && \ 1501 kvm_cmp_feat(kvm, id, fld, <=, max)) 1502 1503 /* Check for a given level of PAuth support */ 1504 #define kvm_has_pauth(k, l) \ 1505 ({ \ 1506 bool pa, pi, pa3; \ 1507 \ 1508 pa = kvm_has_feat((k), ID_AA64ISAR1_EL1, APA, l); \ 1509 pa &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPA, IMP); \ 1510 pi = kvm_has_feat((k), ID_AA64ISAR1_EL1, API, l); \ 1511 pi &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPI, IMP); \ 1512 pa3 = kvm_has_feat((k), ID_AA64ISAR2_EL1, APA3, l); \ 1513 pa3 &= kvm_has_feat((k), ID_AA64ISAR2_EL1, GPA3, IMP); \ 1514 \ 1515 (pa + pi + pa3) == 1; \ 1516 }) 1517 1518 #define kvm_has_fpmr(k) \ 1519 (system_supports_fpmr() && \ 1520 kvm_has_feat((k), ID_AA64PFR2_EL1, FPMR, IMP)) 1521 1522 #endif /* __ARM64_KVM_HOST_H__ */ 1523