1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/asm/kvm_host.h: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 */ 10 11 #ifndef __ARM64_KVM_HOST_H__ 12 #define __ARM64_KVM_HOST_H__ 13 14 #include <linux/arm-smccc.h> 15 #include <linux/bitmap.h> 16 #include <linux/types.h> 17 #include <linux/jump_label.h> 18 #include <linux/kvm_types.h> 19 #include <linux/maple_tree.h> 20 #include <linux/percpu.h> 21 #include <linux/psci.h> 22 #include <asm/arch_gicv3.h> 23 #include <asm/barrier.h> 24 #include <asm/cpufeature.h> 25 #include <asm/cputype.h> 26 #include <asm/daifflags.h> 27 #include <asm/fpsimd.h> 28 #include <asm/kvm.h> 29 #include <asm/kvm_asm.h> 30 #include <asm/vncr_mapping.h> 31 32 #define __KVM_HAVE_ARCH_INTC_INITIALIZED 33 34 #define KVM_HALT_POLL_NS_DEFAULT 500000 35 36 #include <kvm/arm_vgic.h> 37 #include <kvm/arm_arch_timer.h> 38 #include <kvm/arm_pmu.h> 39 40 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS 41 42 #define KVM_VCPU_MAX_FEATURES 9 43 #define KVM_VCPU_VALID_FEATURES (BIT(KVM_VCPU_MAX_FEATURES) - 1) 44 45 #define KVM_REQ_SLEEP \ 46 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 47 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1) 48 #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2) 49 #define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(3) 50 #define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4) 51 #define KVM_REQ_RELOAD_PMU KVM_ARCH_REQ(5) 52 #define KVM_REQ_SUSPEND KVM_ARCH_REQ(6) 53 #define KVM_REQ_RESYNC_PMU_EL0 KVM_ARCH_REQ(7) 54 #define KVM_REQ_NESTED_S2_UNMAP KVM_ARCH_REQ(8) 55 #define KVM_REQ_GUEST_HYP_IRQ_PENDING KVM_ARCH_REQ(9) 56 #define KVM_REQ_MAP_L1_VNCR_EL2 KVM_ARCH_REQ(10) 57 58 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \ 59 KVM_DIRTY_LOG_INITIALLY_SET) 60 61 #define KVM_HAVE_MMU_RWLOCK 62 63 /* 64 * Mode of operation configurable with kvm-arm.mode early param. 65 * See Documentation/admin-guide/kernel-parameters.txt for more information. 66 */ 67 enum kvm_mode { 68 KVM_MODE_DEFAULT, 69 KVM_MODE_PROTECTED, 70 KVM_MODE_NV, 71 KVM_MODE_NONE, 72 }; 73 #ifdef CONFIG_KVM 74 enum kvm_mode kvm_get_mode(void); 75 #else 76 static inline enum kvm_mode kvm_get_mode(void) { return KVM_MODE_NONE; }; 77 #endif 78 79 extern unsigned int __ro_after_init kvm_sve_max_vl; 80 extern unsigned int __ro_after_init kvm_host_sve_max_vl; 81 int __init kvm_arm_init_sve(void); 82 83 u32 __attribute_const__ kvm_target_cpu(void); 84 void kvm_reset_vcpu(struct kvm_vcpu *vcpu); 85 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu); 86 87 struct kvm_hyp_memcache { 88 phys_addr_t head; 89 unsigned long nr_pages; 90 struct pkvm_mapping *mapping; /* only used from EL1 */ 91 92 #define HYP_MEMCACHE_ACCOUNT_STAGE2 BIT(1) 93 unsigned long flags; 94 }; 95 96 static inline void push_hyp_memcache(struct kvm_hyp_memcache *mc, 97 phys_addr_t *p, 98 phys_addr_t (*to_pa)(void *virt)) 99 { 100 *p = mc->head; 101 mc->head = to_pa(p); 102 mc->nr_pages++; 103 } 104 105 static inline void *pop_hyp_memcache(struct kvm_hyp_memcache *mc, 106 void *(*to_va)(phys_addr_t phys)) 107 { 108 phys_addr_t *p = to_va(mc->head & PAGE_MASK); 109 110 if (!mc->nr_pages) 111 return NULL; 112 113 mc->head = *p; 114 mc->nr_pages--; 115 116 return p; 117 } 118 119 static inline int __topup_hyp_memcache(struct kvm_hyp_memcache *mc, 120 unsigned long min_pages, 121 void *(*alloc_fn)(void *arg), 122 phys_addr_t (*to_pa)(void *virt), 123 void *arg) 124 { 125 while (mc->nr_pages < min_pages) { 126 phys_addr_t *p = alloc_fn(arg); 127 128 if (!p) 129 return -ENOMEM; 130 push_hyp_memcache(mc, p, to_pa); 131 } 132 133 return 0; 134 } 135 136 static inline void __free_hyp_memcache(struct kvm_hyp_memcache *mc, 137 void (*free_fn)(void *virt, void *arg), 138 void *(*to_va)(phys_addr_t phys), 139 void *arg) 140 { 141 while (mc->nr_pages) 142 free_fn(pop_hyp_memcache(mc, to_va), arg); 143 } 144 145 void free_hyp_memcache(struct kvm_hyp_memcache *mc); 146 int topup_hyp_memcache(struct kvm_hyp_memcache *mc, unsigned long min_pages); 147 148 struct kvm_vmid { 149 atomic64_t id; 150 }; 151 152 struct kvm_s2_mmu { 153 struct kvm_vmid vmid; 154 155 /* 156 * stage2 entry level table 157 * 158 * Two kvm_s2_mmu structures in the same VM can point to the same 159 * pgd here. This happens when running a guest using a 160 * translation regime that isn't affected by its own stage-2 161 * translation, such as a non-VHE hypervisor running at vEL2, or 162 * for vEL1/EL0 with vHCR_EL2.VM == 0. In that case, we use the 163 * canonical stage-2 page tables. 164 */ 165 phys_addr_t pgd_phys; 166 struct kvm_pgtable *pgt; 167 168 /* 169 * VTCR value used on the host. For a non-NV guest (or a NV 170 * guest that runs in a context where its own S2 doesn't 171 * apply), its T0SZ value reflects that of the IPA size. 172 * 173 * For a shadow S2 MMU, T0SZ reflects the PARange exposed to 174 * the guest. 175 */ 176 u64 vtcr; 177 178 /* The last vcpu id that ran on each physical CPU */ 179 int __percpu *last_vcpu_ran; 180 181 #define KVM_ARM_EAGER_SPLIT_CHUNK_SIZE_DEFAULT 0 182 /* 183 * Memory cache used to split 184 * KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE worth of huge pages. It 185 * is used to allocate stage2 page tables while splitting huge 186 * pages. The choice of KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE 187 * influences both the capacity of the split page cache, and 188 * how often KVM reschedules. Be wary of raising CHUNK_SIZE 189 * too high. 190 * 191 * Protected by kvm->slots_lock. 192 */ 193 struct kvm_mmu_memory_cache split_page_cache; 194 uint64_t split_page_chunk_size; 195 196 struct kvm_arch *arch; 197 198 /* 199 * For a shadow stage-2 MMU, the virtual vttbr used by the 200 * host to parse the guest S2. 201 * This either contains: 202 * - the virtual VTTBR programmed by the guest hypervisor with 203 * CnP cleared 204 * - The value 1 (VMID=0, BADDR=0, CnP=1) if invalid 205 * 206 * We also cache the full VTCR which gets used for TLB invalidation, 207 * taking the ARM ARM's "Any of the bits in VTCR_EL2 are permitted 208 * to be cached in a TLB" to the letter. 209 */ 210 u64 tlb_vttbr; 211 u64 tlb_vtcr; 212 213 /* 214 * true when this represents a nested context where virtual 215 * HCR_EL2.VM == 1 216 */ 217 bool nested_stage2_enabled; 218 219 /* 220 * true when this MMU needs to be unmapped before being used for a new 221 * purpose. 222 */ 223 bool pending_unmap; 224 225 /* 226 * 0: Nobody is currently using this, check vttbr for validity 227 * >0: Somebody is actively using this. 228 */ 229 atomic_t refcnt; 230 }; 231 232 struct kvm_arch_memory_slot { 233 }; 234 235 /** 236 * struct kvm_smccc_features: Descriptor of the hypercall services exposed to the guests 237 * 238 * @std_bmap: Bitmap of standard secure service calls 239 * @std_hyp_bmap: Bitmap of standard hypervisor service calls 240 * @vendor_hyp_bmap: Bitmap of vendor specific hypervisor service calls 241 */ 242 struct kvm_smccc_features { 243 unsigned long std_bmap; 244 unsigned long std_hyp_bmap; 245 unsigned long vendor_hyp_bmap; /* Function numbers 0-63 */ 246 unsigned long vendor_hyp_bmap_2; /* Function numbers 64-127 */ 247 }; 248 249 typedef unsigned int pkvm_handle_t; 250 251 struct kvm_protected_vm { 252 pkvm_handle_t handle; 253 struct kvm_hyp_memcache teardown_mc; 254 struct kvm_hyp_memcache stage2_teardown_mc; 255 bool is_protected; 256 bool is_created; 257 }; 258 259 struct kvm_mpidr_data { 260 u64 mpidr_mask; 261 DECLARE_FLEX_ARRAY(u16, cmpidr_to_idx); 262 }; 263 264 static inline u16 kvm_mpidr_index(struct kvm_mpidr_data *data, u64 mpidr) 265 { 266 unsigned long index = 0, mask = data->mpidr_mask; 267 unsigned long aff = mpidr & MPIDR_HWID_BITMASK; 268 269 bitmap_gather(&index, &aff, &mask, fls(mask)); 270 271 return index; 272 } 273 274 struct kvm_sysreg_masks; 275 276 enum fgt_group_id { 277 __NO_FGT_GROUP__, 278 HFGRTR_GROUP, 279 HFGWTR_GROUP = HFGRTR_GROUP, 280 HDFGRTR_GROUP, 281 HDFGWTR_GROUP = HDFGRTR_GROUP, 282 HFGITR_GROUP, 283 HAFGRTR_GROUP, 284 HFGRTR2_GROUP, 285 HFGWTR2_GROUP = HFGRTR2_GROUP, 286 HDFGRTR2_GROUP, 287 HDFGWTR2_GROUP = HDFGRTR2_GROUP, 288 HFGITR2_GROUP, 289 290 /* Must be last */ 291 __NR_FGT_GROUP_IDS__ 292 }; 293 294 struct kvm_arch { 295 struct kvm_s2_mmu mmu; 296 297 /* 298 * Fine-Grained UNDEF, mimicking the FGT layout defined by the 299 * architecture. We track them globally, as we present the 300 * same feature-set to all vcpus. 301 * 302 * Index 0 is currently spare. 303 */ 304 u64 fgu[__NR_FGT_GROUP_IDS__]; 305 306 /* 307 * Stage 2 paging state for VMs with nested S2 using a virtual 308 * VMID. 309 */ 310 struct kvm_s2_mmu *nested_mmus; 311 size_t nested_mmus_size; 312 int nested_mmus_next; 313 314 /* Interrupt controller */ 315 struct vgic_dist vgic; 316 317 /* Timers */ 318 struct arch_timer_vm_data timer_data; 319 320 /* Mandated version of PSCI */ 321 u32 psci_version; 322 323 /* Protects VM-scoped configuration data */ 324 struct mutex config_lock; 325 326 /* 327 * If we encounter a data abort without valid instruction syndrome 328 * information, report this to user space. User space can (and 329 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is 330 * supported. 331 */ 332 #define KVM_ARCH_FLAG_RETURN_NISV_IO_ABORT_TO_USER 0 333 /* Memory Tagging Extension enabled for the guest */ 334 #define KVM_ARCH_FLAG_MTE_ENABLED 1 335 /* At least one vCPU has ran in the VM */ 336 #define KVM_ARCH_FLAG_HAS_RAN_ONCE 2 337 /* The vCPU feature set for the VM is configured */ 338 #define KVM_ARCH_FLAG_VCPU_FEATURES_CONFIGURED 3 339 /* PSCI SYSTEM_SUSPEND enabled for the guest */ 340 #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED 4 341 /* VM counter offset */ 342 #define KVM_ARCH_FLAG_VM_COUNTER_OFFSET 5 343 /* Timer PPIs made immutable */ 344 #define KVM_ARCH_FLAG_TIMER_PPIS_IMMUTABLE 6 345 /* Initial ID reg values loaded */ 346 #define KVM_ARCH_FLAG_ID_REGS_INITIALIZED 7 347 /* Fine-Grained UNDEF initialised */ 348 #define KVM_ARCH_FLAG_FGU_INITIALIZED 8 349 /* SVE exposed to guest */ 350 #define KVM_ARCH_FLAG_GUEST_HAS_SVE 9 351 /* MIDR_EL1, REVIDR_EL1, and AIDR_EL1 are writable from userspace */ 352 #define KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS 10 353 unsigned long flags; 354 355 /* VM-wide vCPU feature set */ 356 DECLARE_BITMAP(vcpu_features, KVM_VCPU_MAX_FEATURES); 357 358 /* MPIDR to vcpu index mapping, optional */ 359 struct kvm_mpidr_data *mpidr_data; 360 361 /* 362 * VM-wide PMU filter, implemented as a bitmap and big enough for 363 * up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+). 364 */ 365 unsigned long *pmu_filter; 366 struct arm_pmu *arm_pmu; 367 368 cpumask_var_t supported_cpus; 369 370 /* Maximum number of counters for the guest */ 371 u8 nr_pmu_counters; 372 373 /* Iterator for idreg debugfs */ 374 u8 idreg_debugfs_iter; 375 376 /* Hypercall features firmware registers' descriptor */ 377 struct kvm_smccc_features smccc_feat; 378 struct maple_tree smccc_filter; 379 380 /* 381 * Emulated CPU ID registers per VM 382 * (Op0, Op1, CRn, CRm, Op2) of the ID registers to be saved in it 383 * is (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8. 384 * 385 * These emulated idregs are VM-wide, but accessed from the context of a vCPU. 386 * Atomic access to multiple idregs are guarded by kvm_arch.config_lock. 387 */ 388 #define IDREG_IDX(id) (((sys_reg_CRm(id) - 1) << 3) | sys_reg_Op2(id)) 389 #define KVM_ARM_ID_REG_NUM (IDREG_IDX(sys_reg(3, 0, 0, 7, 7)) + 1) 390 u64 id_regs[KVM_ARM_ID_REG_NUM]; 391 392 u64 midr_el1; 393 u64 revidr_el1; 394 u64 aidr_el1; 395 u64 ctr_el0; 396 397 /* Masks for VNCR-backed and general EL2 sysregs */ 398 struct kvm_sysreg_masks *sysreg_masks; 399 400 /* Count the number of VNCR_EL2 currently mapped */ 401 atomic_t vncr_map_count; 402 403 /* 404 * For an untrusted host VM, 'pkvm.handle' is used to lookup 405 * the associated pKVM instance in the hypervisor. 406 */ 407 struct kvm_protected_vm pkvm; 408 }; 409 410 struct kvm_vcpu_fault_info { 411 u64 esr_el2; /* Hyp Syndrom Register */ 412 u64 far_el2; /* Hyp Fault Address Register */ 413 u64 hpfar_el2; /* Hyp IPA Fault Address Register */ 414 u64 disr_el1; /* Deferred [SError] Status Register */ 415 }; 416 417 /* 418 * VNCR() just places the VNCR_capable registers in the enum after 419 * __VNCR_START__, and the value (after correction) to be an 8-byte offset 420 * from the VNCR base. As we don't require the enum to be otherwise ordered, 421 * we need the terrible hack below to ensure that we correctly size the 422 * sys_regs array, no matter what. 423 * 424 * The __MAX__ macro has been lifted from Sean Eron Anderson's wonderful 425 * treasure trove of bit hacks: 426 * https://graphics.stanford.edu/~seander/bithacks.html#IntegerMinOrMax 427 */ 428 #define __MAX__(x,y) ((x) ^ (((x) ^ (y)) & -((x) < (y)))) 429 #define VNCR(r) \ 430 __before_##r, \ 431 r = __VNCR_START__ + ((VNCR_ ## r) / 8), \ 432 __after_##r = __MAX__(__before_##r - 1, r) 433 434 #define MARKER(m) \ 435 m, __after_##m = m - 1 436 437 enum vcpu_sysreg { 438 __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ 439 MPIDR_EL1, /* MultiProcessor Affinity Register */ 440 CLIDR_EL1, /* Cache Level ID Register */ 441 CSSELR_EL1, /* Cache Size Selection Register */ 442 TPIDR_EL0, /* Thread ID, User R/W */ 443 TPIDRRO_EL0, /* Thread ID, User R/O */ 444 TPIDR_EL1, /* Thread ID, Privileged */ 445 CNTKCTL_EL1, /* Timer Control Register (EL1) */ 446 PAR_EL1, /* Physical Address Register */ 447 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ 448 OSLSR_EL1, /* OS Lock Status Register */ 449 DISR_EL1, /* Deferred Interrupt Status Register */ 450 451 /* Performance Monitors Registers */ 452 PMCR_EL0, /* Control Register */ 453 PMSELR_EL0, /* Event Counter Selection Register */ 454 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */ 455 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30, 456 PMCCNTR_EL0, /* Cycle Counter Register */ 457 PMEVTYPER0_EL0, /* Event Type Register (0-30) */ 458 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30, 459 PMCCFILTR_EL0, /* Cycle Count Filter Register */ 460 PMCNTENSET_EL0, /* Count Enable Set Register */ 461 PMINTENSET_EL1, /* Interrupt Enable Set Register */ 462 PMOVSSET_EL0, /* Overflow Flag Status Set Register */ 463 PMUSERENR_EL0, /* User Enable Register */ 464 465 /* Pointer Authentication Registers in a strict increasing order. */ 466 APIAKEYLO_EL1, 467 APIAKEYHI_EL1, 468 APIBKEYLO_EL1, 469 APIBKEYHI_EL1, 470 APDAKEYLO_EL1, 471 APDAKEYHI_EL1, 472 APDBKEYLO_EL1, 473 APDBKEYHI_EL1, 474 APGAKEYLO_EL1, 475 APGAKEYHI_EL1, 476 477 /* Memory Tagging Extension registers */ 478 RGSR_EL1, /* Random Allocation Tag Seed Register */ 479 GCR_EL1, /* Tag Control Register */ 480 TFSRE0_EL1, /* Tag Fault Status Register (EL0) */ 481 482 POR_EL0, /* Permission Overlay Register 0 (EL0) */ 483 484 /* FP/SIMD/SVE */ 485 SVCR, 486 FPMR, 487 488 /* 32bit specific registers. */ 489 DACR32_EL2, /* Domain Access Control Register */ 490 IFSR32_EL2, /* Instruction Fault Status Register */ 491 FPEXC32_EL2, /* Floating-Point Exception Control Register */ 492 DBGVCR32_EL2, /* Debug Vector Catch Register */ 493 494 /* EL2 registers */ 495 SCTLR_EL2, /* System Control Register (EL2) */ 496 ACTLR_EL2, /* Auxiliary Control Register (EL2) */ 497 CPTR_EL2, /* Architectural Feature Trap Register (EL2) */ 498 HACR_EL2, /* Hypervisor Auxiliary Control Register */ 499 ZCR_EL2, /* SVE Control Register (EL2) */ 500 TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */ 501 TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */ 502 TCR_EL2, /* Translation Control Register (EL2) */ 503 PIRE0_EL2, /* Permission Indirection Register 0 (EL2) */ 504 PIR_EL2, /* Permission Indirection Register 1 (EL2) */ 505 POR_EL2, /* Permission Overlay Register 2 (EL2) */ 506 SPSR_EL2, /* EL2 saved program status register */ 507 ELR_EL2, /* EL2 exception link register */ 508 AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */ 509 AFSR1_EL2, /* Auxiliary Fault Status Register 1 (EL2) */ 510 ESR_EL2, /* Exception Syndrome Register (EL2) */ 511 FAR_EL2, /* Fault Address Register (EL2) */ 512 HPFAR_EL2, /* Hypervisor IPA Fault Address Register */ 513 MAIR_EL2, /* Memory Attribute Indirection Register (EL2) */ 514 AMAIR_EL2, /* Auxiliary Memory Attribute Indirection Register (EL2) */ 515 VBAR_EL2, /* Vector Base Address Register (EL2) */ 516 RVBAR_EL2, /* Reset Vector Base Address Register */ 517 CONTEXTIDR_EL2, /* Context ID Register (EL2) */ 518 SP_EL2, /* EL2 Stack Pointer */ 519 CNTHP_CTL_EL2, 520 CNTHP_CVAL_EL2, 521 CNTHV_CTL_EL2, 522 CNTHV_CVAL_EL2, 523 524 /* Anything from this can be RES0/RES1 sanitised */ 525 MARKER(__SANITISED_REG_START__), 526 TCR2_EL2, /* Extended Translation Control Register (EL2) */ 527 SCTLR2_EL2, /* System Control Register 2 (EL2) */ 528 MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */ 529 CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */ 530 531 /* Any VNCR-capable reg goes after this point */ 532 MARKER(__VNCR_START__), 533 534 VNCR(SCTLR_EL1),/* System Control Register */ 535 VNCR(ACTLR_EL1),/* Auxiliary Control Register */ 536 VNCR(CPACR_EL1),/* Coprocessor Access Control */ 537 VNCR(ZCR_EL1), /* SVE Control */ 538 VNCR(TTBR0_EL1),/* Translation Table Base Register 0 */ 539 VNCR(TTBR1_EL1),/* Translation Table Base Register 1 */ 540 VNCR(TCR_EL1), /* Translation Control Register */ 541 VNCR(TCR2_EL1), /* Extended Translation Control Register */ 542 VNCR(SCTLR2_EL1), /* System Control Register 2 */ 543 VNCR(ESR_EL1), /* Exception Syndrome Register */ 544 VNCR(AFSR0_EL1),/* Auxiliary Fault Status Register 0 */ 545 VNCR(AFSR1_EL1),/* Auxiliary Fault Status Register 1 */ 546 VNCR(FAR_EL1), /* Fault Address Register */ 547 VNCR(MAIR_EL1), /* Memory Attribute Indirection Register */ 548 VNCR(VBAR_EL1), /* Vector Base Address Register */ 549 VNCR(CONTEXTIDR_EL1), /* Context ID Register */ 550 VNCR(AMAIR_EL1),/* Aux Memory Attribute Indirection Register */ 551 VNCR(MDSCR_EL1),/* Monitor Debug System Control Register */ 552 VNCR(ELR_EL1), 553 VNCR(SP_EL1), 554 VNCR(SPSR_EL1), 555 VNCR(TFSR_EL1), /* Tag Fault Status Register (EL1) */ 556 VNCR(VPIDR_EL2),/* Virtualization Processor ID Register */ 557 VNCR(VMPIDR_EL2),/* Virtualization Multiprocessor ID Register */ 558 VNCR(HCR_EL2), /* Hypervisor Configuration Register */ 559 VNCR(HSTR_EL2), /* Hypervisor System Trap Register */ 560 VNCR(VTTBR_EL2),/* Virtualization Translation Table Base Register */ 561 VNCR(VTCR_EL2), /* Virtualization Translation Control Register */ 562 VNCR(TPIDR_EL2),/* EL2 Software Thread ID Register */ 563 VNCR(HCRX_EL2), /* Extended Hypervisor Configuration Register */ 564 565 /* Permission Indirection Extension registers */ 566 VNCR(PIR_EL1), /* Permission Indirection Register 1 (EL1) */ 567 VNCR(PIRE0_EL1), /* Permission Indirection Register 0 (EL1) */ 568 569 VNCR(POR_EL1), /* Permission Overlay Register 1 (EL1) */ 570 571 /* FEAT_RAS registers */ 572 VNCR(VDISR_EL2), 573 VNCR(VSESR_EL2), 574 575 VNCR(HFGRTR_EL2), 576 VNCR(HFGWTR_EL2), 577 VNCR(HFGITR_EL2), 578 VNCR(HDFGRTR_EL2), 579 VNCR(HDFGWTR_EL2), 580 VNCR(HAFGRTR_EL2), 581 VNCR(HFGRTR2_EL2), 582 VNCR(HFGWTR2_EL2), 583 VNCR(HFGITR2_EL2), 584 VNCR(HDFGRTR2_EL2), 585 VNCR(HDFGWTR2_EL2), 586 587 VNCR(VNCR_EL2), 588 589 VNCR(CNTVOFF_EL2), 590 VNCR(CNTV_CVAL_EL0), 591 VNCR(CNTV_CTL_EL0), 592 VNCR(CNTP_CVAL_EL0), 593 VNCR(CNTP_CTL_EL0), 594 595 VNCR(ICH_LR0_EL2), 596 VNCR(ICH_LR1_EL2), 597 VNCR(ICH_LR2_EL2), 598 VNCR(ICH_LR3_EL2), 599 VNCR(ICH_LR4_EL2), 600 VNCR(ICH_LR5_EL2), 601 VNCR(ICH_LR6_EL2), 602 VNCR(ICH_LR7_EL2), 603 VNCR(ICH_LR8_EL2), 604 VNCR(ICH_LR9_EL2), 605 VNCR(ICH_LR10_EL2), 606 VNCR(ICH_LR11_EL2), 607 VNCR(ICH_LR12_EL2), 608 VNCR(ICH_LR13_EL2), 609 VNCR(ICH_LR14_EL2), 610 VNCR(ICH_LR15_EL2), 611 612 VNCR(ICH_AP0R0_EL2), 613 VNCR(ICH_AP0R1_EL2), 614 VNCR(ICH_AP0R2_EL2), 615 VNCR(ICH_AP0R3_EL2), 616 VNCR(ICH_AP1R0_EL2), 617 VNCR(ICH_AP1R1_EL2), 618 VNCR(ICH_AP1R2_EL2), 619 VNCR(ICH_AP1R3_EL2), 620 VNCR(ICH_HCR_EL2), 621 VNCR(ICH_VMCR_EL2), 622 623 NR_SYS_REGS /* Nothing after this line! */ 624 }; 625 626 struct kvm_sysreg_masks { 627 struct { 628 u64 res0; 629 u64 res1; 630 } mask[NR_SYS_REGS - __SANITISED_REG_START__]; 631 }; 632 633 struct fgt_masks { 634 const char *str; 635 u64 mask; 636 u64 nmask; 637 u64 res0; 638 }; 639 640 extern struct fgt_masks hfgrtr_masks; 641 extern struct fgt_masks hfgwtr_masks; 642 extern struct fgt_masks hfgitr_masks; 643 extern struct fgt_masks hdfgrtr_masks; 644 extern struct fgt_masks hdfgwtr_masks; 645 extern struct fgt_masks hafgrtr_masks; 646 extern struct fgt_masks hfgrtr2_masks; 647 extern struct fgt_masks hfgwtr2_masks; 648 extern struct fgt_masks hfgitr2_masks; 649 extern struct fgt_masks hdfgrtr2_masks; 650 extern struct fgt_masks hdfgwtr2_masks; 651 652 extern struct fgt_masks kvm_nvhe_sym(hfgrtr_masks); 653 extern struct fgt_masks kvm_nvhe_sym(hfgwtr_masks); 654 extern struct fgt_masks kvm_nvhe_sym(hfgitr_masks); 655 extern struct fgt_masks kvm_nvhe_sym(hdfgrtr_masks); 656 extern struct fgt_masks kvm_nvhe_sym(hdfgwtr_masks); 657 extern struct fgt_masks kvm_nvhe_sym(hafgrtr_masks); 658 extern struct fgt_masks kvm_nvhe_sym(hfgrtr2_masks); 659 extern struct fgt_masks kvm_nvhe_sym(hfgwtr2_masks); 660 extern struct fgt_masks kvm_nvhe_sym(hfgitr2_masks); 661 extern struct fgt_masks kvm_nvhe_sym(hdfgrtr2_masks); 662 extern struct fgt_masks kvm_nvhe_sym(hdfgwtr2_masks); 663 664 struct kvm_cpu_context { 665 struct user_pt_regs regs; /* sp = sp_el0 */ 666 667 u64 spsr_abt; 668 u64 spsr_und; 669 u64 spsr_irq; 670 u64 spsr_fiq; 671 672 struct user_fpsimd_state fp_regs; 673 674 u64 sys_regs[NR_SYS_REGS]; 675 676 struct kvm_vcpu *__hyp_running_vcpu; 677 678 /* This pointer has to be 4kB aligned. */ 679 u64 *vncr_array; 680 }; 681 682 struct cpu_sve_state { 683 __u64 zcr_el1; 684 685 /* 686 * Ordering is important since __sve_save_state/__sve_restore_state 687 * relies on it. 688 */ 689 __u32 fpsr; 690 __u32 fpcr; 691 692 /* Must be SVE_VQ_BYTES (128 bit) aligned. */ 693 __u8 sve_regs[]; 694 }; 695 696 /* 697 * This structure is instantiated on a per-CPU basis, and contains 698 * data that is: 699 * 700 * - tied to a single physical CPU, and 701 * - either have a lifetime that does not extend past vcpu_put() 702 * - or is an invariant for the lifetime of the system 703 * 704 * Use host_data_ptr(field) as a way to access a pointer to such a 705 * field. 706 */ 707 struct kvm_host_data { 708 #define KVM_HOST_DATA_FLAG_HAS_SPE 0 709 #define KVM_HOST_DATA_FLAG_HAS_TRBE 1 710 #define KVM_HOST_DATA_FLAG_TRBE_ENABLED 4 711 #define KVM_HOST_DATA_FLAG_EL1_TRACING_CONFIGURED 5 712 #define KVM_HOST_DATA_FLAG_VCPU_IN_HYP_CONTEXT 6 713 #define KVM_HOST_DATA_FLAG_L1_VNCR_MAPPED 7 714 #define KVM_HOST_DATA_FLAG_HAS_BRBE 8 715 unsigned long flags; 716 717 struct kvm_cpu_context host_ctxt; 718 719 /* 720 * Hyp VA. 721 * sve_state is only used in pKVM and if system_supports_sve(). 722 */ 723 struct cpu_sve_state *sve_state; 724 725 /* Used by pKVM only. */ 726 u64 fpmr; 727 728 /* Ownership of the FP regs */ 729 enum { 730 FP_STATE_FREE, 731 FP_STATE_HOST_OWNED, 732 FP_STATE_GUEST_OWNED, 733 } fp_owner; 734 735 /* 736 * host_debug_state contains the host registers which are 737 * saved and restored during world switches. 738 */ 739 struct { 740 /* {Break,watch}point registers */ 741 struct kvm_guest_debug_arch regs; 742 /* Statistical profiling extension */ 743 u64 pmscr_el1; 744 /* Self-hosted trace */ 745 u64 trfcr_el1; 746 /* Values of trap registers for the host before guest entry. */ 747 u64 mdcr_el2; 748 u64 brbcr_el1; 749 } host_debug_state; 750 751 /* Guest trace filter value */ 752 u64 trfcr_while_in_guest; 753 754 /* Number of programmable event counters (PMCR_EL0.N) for this CPU */ 755 unsigned int nr_event_counters; 756 757 /* Number of debug breakpoints/watchpoints for this CPU (minus 1) */ 758 unsigned int debug_brps; 759 unsigned int debug_wrps; 760 }; 761 762 struct kvm_host_psci_config { 763 /* PSCI version used by host. */ 764 u32 version; 765 u32 smccc_version; 766 767 /* Function IDs used by host if version is v0.1. */ 768 struct psci_0_1_function_ids function_ids_0_1; 769 770 bool psci_0_1_cpu_suspend_implemented; 771 bool psci_0_1_cpu_on_implemented; 772 bool psci_0_1_cpu_off_implemented; 773 bool psci_0_1_migrate_implemented; 774 }; 775 776 extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config); 777 #define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config) 778 779 extern s64 kvm_nvhe_sym(hyp_physvirt_offset); 780 #define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset) 781 782 extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS]; 783 #define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map) 784 785 struct vcpu_reset_state { 786 unsigned long pc; 787 unsigned long r0; 788 bool be; 789 bool reset; 790 }; 791 792 struct vncr_tlb; 793 794 struct kvm_vcpu_arch { 795 struct kvm_cpu_context ctxt; 796 797 /* 798 * Guest floating point state 799 * 800 * The architecture has two main floating point extensions, 801 * the original FPSIMD and SVE. These have overlapping 802 * register views, with the FPSIMD V registers occupying the 803 * low 128 bits of the SVE Z registers. When the core 804 * floating point code saves the register state of a task it 805 * records which view it saved in fp_type. 806 */ 807 void *sve_state; 808 enum fp_type fp_type; 809 unsigned int sve_max_vl; 810 811 /* Stage 2 paging state used by the hardware on next switch */ 812 struct kvm_s2_mmu *hw_mmu; 813 814 /* Values of trap registers for the guest. */ 815 u64 hcr_el2; 816 u64 hcrx_el2; 817 u64 mdcr_el2; 818 819 /* Exception Information */ 820 struct kvm_vcpu_fault_info fault; 821 822 /* Configuration flags, set once and for all before the vcpu can run */ 823 u8 cflags; 824 825 /* Input flags to the hypervisor code, potentially cleared after use */ 826 u8 iflags; 827 828 /* State flags for kernel bookkeeping, unused by the hypervisor code */ 829 u16 sflags; 830 831 /* 832 * Don't run the guest (internal implementation need). 833 * 834 * Contrary to the flags above, this is set/cleared outside of 835 * a vcpu context, and thus cannot be mixed with the flags 836 * themselves (or the flag accesses need to be made atomic). 837 */ 838 bool pause; 839 840 /* 841 * We maintain more than a single set of debug registers to support 842 * debugging the guest from the host and to maintain separate host and 843 * guest state during world switches. vcpu_debug_state are the debug 844 * registers of the vcpu as the guest sees them. 845 * 846 * external_debug_state contains the debug values we want to debug the 847 * guest. This is set via the KVM_SET_GUEST_DEBUG ioctl. 848 */ 849 struct kvm_guest_debug_arch vcpu_debug_state; 850 struct kvm_guest_debug_arch external_debug_state; 851 u64 external_mdscr_el1; 852 853 enum { 854 VCPU_DEBUG_FREE, 855 VCPU_DEBUG_HOST_OWNED, 856 VCPU_DEBUG_GUEST_OWNED, 857 } debug_owner; 858 859 /* VGIC state */ 860 struct vgic_cpu vgic_cpu; 861 struct arch_timer_cpu timer_cpu; 862 struct kvm_pmu pmu; 863 864 /* vcpu power state */ 865 struct kvm_mp_state mp_state; 866 spinlock_t mp_state_lock; 867 868 /* Cache some mmu pages needed inside spinlock regions */ 869 struct kvm_mmu_memory_cache mmu_page_cache; 870 871 /* Pages to top-up the pKVM/EL2 guest pool */ 872 struct kvm_hyp_memcache pkvm_memcache; 873 874 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */ 875 u64 vsesr_el2; 876 877 /* Additional reset state */ 878 struct vcpu_reset_state reset_state; 879 880 /* Guest PV state */ 881 struct { 882 u64 last_steal; 883 gpa_t base; 884 } steal; 885 886 /* Per-vcpu CCSIDR override or NULL */ 887 u32 *ccsidr; 888 889 /* Per-vcpu TLB for VNCR_EL2 -- NULL when !NV */ 890 struct vncr_tlb *vncr_tlb; 891 }; 892 893 /* 894 * Each 'flag' is composed of a comma-separated triplet: 895 * 896 * - the flag-set it belongs to in the vcpu->arch structure 897 * - the value for that flag 898 * - the mask for that flag 899 * 900 * __vcpu_single_flag() builds such a triplet for a single-bit flag. 901 * unpack_vcpu_flag() extract the flag value from the triplet for 902 * direct use outside of the flag accessors. 903 */ 904 #define __vcpu_single_flag(_set, _f) _set, (_f), (_f) 905 906 #define __unpack_flag(_set, _f, _m) _f 907 #define unpack_vcpu_flag(...) __unpack_flag(__VA_ARGS__) 908 909 #define __build_check_flag(v, flagset, f, m) \ 910 do { \ 911 typeof(v->arch.flagset) *_fset; \ 912 \ 913 /* Check that the flags fit in the mask */ \ 914 BUILD_BUG_ON(HWEIGHT(m) != HWEIGHT((f) | (m))); \ 915 /* Check that the flags fit in the type */ \ 916 BUILD_BUG_ON((sizeof(*_fset) * 8) <= __fls(m)); \ 917 } while (0) 918 919 #define __vcpu_get_flag(v, flagset, f, m) \ 920 ({ \ 921 __build_check_flag(v, flagset, f, m); \ 922 \ 923 READ_ONCE(v->arch.flagset) & (m); \ 924 }) 925 926 /* 927 * Note that the set/clear accessors must be preempt-safe in order to 928 * avoid nesting them with load/put which also manipulate flags... 929 */ 930 #ifdef __KVM_NVHE_HYPERVISOR__ 931 /* the nVHE hypervisor is always non-preemptible */ 932 #define __vcpu_flags_preempt_disable() 933 #define __vcpu_flags_preempt_enable() 934 #else 935 #define __vcpu_flags_preempt_disable() preempt_disable() 936 #define __vcpu_flags_preempt_enable() preempt_enable() 937 #endif 938 939 #define __vcpu_set_flag(v, flagset, f, m) \ 940 do { \ 941 typeof(v->arch.flagset) *fset; \ 942 \ 943 __build_check_flag(v, flagset, f, m); \ 944 \ 945 fset = &v->arch.flagset; \ 946 __vcpu_flags_preempt_disable(); \ 947 if (HWEIGHT(m) > 1) \ 948 *fset &= ~(m); \ 949 *fset |= (f); \ 950 __vcpu_flags_preempt_enable(); \ 951 } while (0) 952 953 #define __vcpu_clear_flag(v, flagset, f, m) \ 954 do { \ 955 typeof(v->arch.flagset) *fset; \ 956 \ 957 __build_check_flag(v, flagset, f, m); \ 958 \ 959 fset = &v->arch.flagset; \ 960 __vcpu_flags_preempt_disable(); \ 961 *fset &= ~(m); \ 962 __vcpu_flags_preempt_enable(); \ 963 } while (0) 964 965 #define __vcpu_test_and_clear_flag(v, flagset, f, m) \ 966 ({ \ 967 typeof(v->arch.flagset) set; \ 968 \ 969 set = __vcpu_get_flag(v, flagset, f, m); \ 970 __vcpu_clear_flag(v, flagset, f, m); \ 971 \ 972 set; \ 973 }) 974 975 #define vcpu_get_flag(v, ...) __vcpu_get_flag((v), __VA_ARGS__) 976 #define vcpu_set_flag(v, ...) __vcpu_set_flag((v), __VA_ARGS__) 977 #define vcpu_clear_flag(v, ...) __vcpu_clear_flag((v), __VA_ARGS__) 978 #define vcpu_test_and_clear_flag(v, ...) \ 979 __vcpu_test_and_clear_flag((v), __VA_ARGS__) 980 981 /* KVM_ARM_VCPU_INIT completed */ 982 #define VCPU_INITIALIZED __vcpu_single_flag(cflags, BIT(0)) 983 /* SVE config completed */ 984 #define VCPU_SVE_FINALIZED __vcpu_single_flag(cflags, BIT(1)) 985 /* pKVM VCPU setup completed */ 986 #define VCPU_PKVM_FINALIZED __vcpu_single_flag(cflags, BIT(2)) 987 988 /* Exception pending */ 989 #define PENDING_EXCEPTION __vcpu_single_flag(iflags, BIT(0)) 990 /* 991 * PC increment. Overlaps with EXCEPT_MASK on purpose so that it can't 992 * be set together with an exception... 993 */ 994 #define INCREMENT_PC __vcpu_single_flag(iflags, BIT(1)) 995 /* Target EL/MODE (not a single flag, but let's abuse the macro) */ 996 #define EXCEPT_MASK __vcpu_single_flag(iflags, GENMASK(3, 1)) 997 998 /* Helpers to encode exceptions with minimum fuss */ 999 #define __EXCEPT_MASK_VAL unpack_vcpu_flag(EXCEPT_MASK) 1000 #define __EXCEPT_SHIFT __builtin_ctzl(__EXCEPT_MASK_VAL) 1001 #define __vcpu_except_flags(_f) iflags, (_f << __EXCEPT_SHIFT), __EXCEPT_MASK_VAL 1002 1003 /* 1004 * When PENDING_EXCEPTION is set, EXCEPT_MASK can take the following 1005 * values: 1006 * 1007 * For AArch32 EL1: 1008 */ 1009 #define EXCEPT_AA32_UND __vcpu_except_flags(0) 1010 #define EXCEPT_AA32_IABT __vcpu_except_flags(1) 1011 #define EXCEPT_AA32_DABT __vcpu_except_flags(2) 1012 /* For AArch64: */ 1013 #define EXCEPT_AA64_EL1_SYNC __vcpu_except_flags(0) 1014 #define EXCEPT_AA64_EL1_IRQ __vcpu_except_flags(1) 1015 #define EXCEPT_AA64_EL1_FIQ __vcpu_except_flags(2) 1016 #define EXCEPT_AA64_EL1_SERR __vcpu_except_flags(3) 1017 /* For AArch64 with NV: */ 1018 #define EXCEPT_AA64_EL2_SYNC __vcpu_except_flags(4) 1019 #define EXCEPT_AA64_EL2_IRQ __vcpu_except_flags(5) 1020 #define EXCEPT_AA64_EL2_FIQ __vcpu_except_flags(6) 1021 #define EXCEPT_AA64_EL2_SERR __vcpu_except_flags(7) 1022 1023 /* Physical CPU not in supported_cpus */ 1024 #define ON_UNSUPPORTED_CPU __vcpu_single_flag(sflags, BIT(0)) 1025 /* WFIT instruction trapped */ 1026 #define IN_WFIT __vcpu_single_flag(sflags, BIT(1)) 1027 /* vcpu system registers loaded on physical CPU */ 1028 #define SYSREGS_ON_CPU __vcpu_single_flag(sflags, BIT(2)) 1029 /* Software step state is Active-pending for external debug */ 1030 #define HOST_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(3)) 1031 /* Software step state is Active pending for guest debug */ 1032 #define GUEST_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(4)) 1033 /* PMUSERENR for the guest EL0 is on physical CPU */ 1034 #define PMUSERENR_ON_CPU __vcpu_single_flag(sflags, BIT(5)) 1035 /* WFI instruction trapped */ 1036 #define IN_WFI __vcpu_single_flag(sflags, BIT(6)) 1037 /* KVM is currently emulating a nested ERET */ 1038 #define IN_NESTED_ERET __vcpu_single_flag(sflags, BIT(7)) 1039 /* SError pending for nested guest */ 1040 #define NESTED_SERROR_PENDING __vcpu_single_flag(sflags, BIT(8)) 1041 1042 1043 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */ 1044 #define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) + \ 1045 sve_ffr_offset((vcpu)->arch.sve_max_vl)) 1046 1047 #define vcpu_sve_max_vq(vcpu) sve_vq_from_vl((vcpu)->arch.sve_max_vl) 1048 1049 #define vcpu_sve_zcr_elx(vcpu) \ 1050 (unlikely(is_hyp_ctxt(vcpu)) ? ZCR_EL2 : ZCR_EL1) 1051 1052 #define sve_state_size_from_vl(sve_max_vl) ({ \ 1053 size_t __size_ret; \ 1054 unsigned int __vq; \ 1055 \ 1056 if (WARN_ON(!sve_vl_valid(sve_max_vl))) { \ 1057 __size_ret = 0; \ 1058 } else { \ 1059 __vq = sve_vq_from_vl(sve_max_vl); \ 1060 __size_ret = SVE_SIG_REGS_SIZE(__vq); \ 1061 } \ 1062 \ 1063 __size_ret; \ 1064 }) 1065 1066 #define vcpu_sve_state_size(vcpu) sve_state_size_from_vl((vcpu)->arch.sve_max_vl) 1067 1068 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \ 1069 KVM_GUESTDBG_USE_SW_BP | \ 1070 KVM_GUESTDBG_USE_HW | \ 1071 KVM_GUESTDBG_SINGLESTEP) 1072 1073 #define kvm_has_sve(kvm) (system_supports_sve() && \ 1074 test_bit(KVM_ARCH_FLAG_GUEST_HAS_SVE, &(kvm)->arch.flags)) 1075 1076 #ifdef __KVM_NVHE_HYPERVISOR__ 1077 #define vcpu_has_sve(vcpu) kvm_has_sve(kern_hyp_va((vcpu)->kvm)) 1078 #else 1079 #define vcpu_has_sve(vcpu) kvm_has_sve((vcpu)->kvm) 1080 #endif 1081 1082 #ifdef CONFIG_ARM64_PTR_AUTH 1083 #define vcpu_has_ptrauth(vcpu) \ 1084 ((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) || \ 1085 cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) && \ 1086 (vcpu_has_feature(vcpu, KVM_ARM_VCPU_PTRAUTH_ADDRESS) || \ 1087 vcpu_has_feature(vcpu, KVM_ARM_VCPU_PTRAUTH_GENERIC))) 1088 #else 1089 #define vcpu_has_ptrauth(vcpu) false 1090 #endif 1091 1092 #define vcpu_on_unsupported_cpu(vcpu) \ 1093 vcpu_get_flag(vcpu, ON_UNSUPPORTED_CPU) 1094 1095 #define vcpu_set_on_unsupported_cpu(vcpu) \ 1096 vcpu_set_flag(vcpu, ON_UNSUPPORTED_CPU) 1097 1098 #define vcpu_clear_on_unsupported_cpu(vcpu) \ 1099 vcpu_clear_flag(vcpu, ON_UNSUPPORTED_CPU) 1100 1101 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.regs) 1102 1103 /* 1104 * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the 1105 * memory backed version of a register, and not the one most recently 1106 * accessed by a running VCPU. For example, for userspace access or 1107 * for system registers that are never context switched, but only 1108 * emulated. 1109 * 1110 * Don't bother with VNCR-based accesses in the nVHE code, it has no 1111 * business dealing with NV. 1112 */ 1113 static inline u64 *___ctxt_sys_reg(const struct kvm_cpu_context *ctxt, int r) 1114 { 1115 #if !defined (__KVM_NVHE_HYPERVISOR__) 1116 if (unlikely(cpus_have_final_cap(ARM64_HAS_NESTED_VIRT) && 1117 r >= __VNCR_START__ && ctxt->vncr_array)) 1118 return &ctxt->vncr_array[r - __VNCR_START__]; 1119 #endif 1120 return (u64 *)&ctxt->sys_regs[r]; 1121 } 1122 1123 #define __ctxt_sys_reg(c,r) \ 1124 ({ \ 1125 BUILD_BUG_ON(__builtin_constant_p(r) && \ 1126 (r) >= NR_SYS_REGS); \ 1127 ___ctxt_sys_reg(c, r); \ 1128 }) 1129 1130 #define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r)) 1131 1132 u64 kvm_vcpu_apply_reg_masks(const struct kvm_vcpu *, enum vcpu_sysreg, u64); 1133 1134 #define __vcpu_assign_sys_reg(v, r, val) \ 1135 do { \ 1136 const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \ 1137 u64 __v = (val); \ 1138 if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \ 1139 __v = kvm_vcpu_apply_reg_masks((v), (r), __v); \ 1140 \ 1141 ctxt_sys_reg(ctxt, (r)) = __v; \ 1142 } while (0) 1143 1144 #define __vcpu_rmw_sys_reg(v, r, op, val) \ 1145 do { \ 1146 const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \ 1147 u64 __v = ctxt_sys_reg(ctxt, (r)); \ 1148 __v op (val); \ 1149 if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \ 1150 __v = kvm_vcpu_apply_reg_masks((v), (r), __v); \ 1151 \ 1152 ctxt_sys_reg(ctxt, (r)) = __v; \ 1153 } while (0) 1154 1155 #define __vcpu_sys_reg(v,r) \ 1156 ({ \ 1157 const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \ 1158 u64 __v = ctxt_sys_reg(ctxt, (r)); \ 1159 if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \ 1160 __v = kvm_vcpu_apply_reg_masks((v), (r), __v); \ 1161 __v; \ 1162 }) 1163 1164 u64 vcpu_read_sys_reg(const struct kvm_vcpu *, enum vcpu_sysreg); 1165 void vcpu_write_sys_reg(struct kvm_vcpu *, u64, enum vcpu_sysreg); 1166 1167 struct kvm_vm_stat { 1168 struct kvm_vm_stat_generic generic; 1169 }; 1170 1171 struct kvm_vcpu_stat { 1172 struct kvm_vcpu_stat_generic generic; 1173 u64 hvc_exit_stat; 1174 u64 wfe_exit_stat; 1175 u64 wfi_exit_stat; 1176 u64 mmio_exit_user; 1177 u64 mmio_exit_kernel; 1178 u64 signal_exits; 1179 u64 exits; 1180 }; 1181 1182 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); 1183 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); 1184 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 1185 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 1186 1187 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu); 1188 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices); 1189 1190 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu, 1191 struct kvm_vcpu_events *events); 1192 1193 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu, 1194 struct kvm_vcpu_events *events); 1195 1196 void kvm_arm_halt_guest(struct kvm *kvm); 1197 void kvm_arm_resume_guest(struct kvm *kvm); 1198 1199 #define vcpu_has_run_once(vcpu) (!!READ_ONCE((vcpu)->pid)) 1200 1201 #ifndef __KVM_NVHE_HYPERVISOR__ 1202 #define kvm_call_hyp_nvhe(f, ...) \ 1203 ({ \ 1204 struct arm_smccc_res res; \ 1205 \ 1206 arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f), \ 1207 ##__VA_ARGS__, &res); \ 1208 WARN_ON(res.a0 != SMCCC_RET_SUCCESS); \ 1209 \ 1210 res.a1; \ 1211 }) 1212 1213 /* 1214 * The isb() below is there to guarantee the same behaviour on VHE as on !VHE, 1215 * where the eret to EL1 acts as a context synchronization event. 1216 */ 1217 #define kvm_call_hyp(f, ...) \ 1218 do { \ 1219 if (has_vhe()) { \ 1220 f(__VA_ARGS__); \ 1221 isb(); \ 1222 } else { \ 1223 kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 1224 } \ 1225 } while(0) 1226 1227 #define kvm_call_hyp_ret(f, ...) \ 1228 ({ \ 1229 typeof(f(__VA_ARGS__)) ret; \ 1230 \ 1231 if (has_vhe()) { \ 1232 ret = f(__VA_ARGS__); \ 1233 } else { \ 1234 ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 1235 } \ 1236 \ 1237 ret; \ 1238 }) 1239 #else /* __KVM_NVHE_HYPERVISOR__ */ 1240 #define kvm_call_hyp(f, ...) f(__VA_ARGS__) 1241 #define kvm_call_hyp_ret(f, ...) f(__VA_ARGS__) 1242 #define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__) 1243 #endif /* __KVM_NVHE_HYPERVISOR__ */ 1244 1245 int handle_exit(struct kvm_vcpu *vcpu, int exception_index); 1246 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index); 1247 1248 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu); 1249 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu); 1250 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu); 1251 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu); 1252 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu); 1253 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu); 1254 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu); 1255 1256 void kvm_sys_regs_create_debugfs(struct kvm *kvm); 1257 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu); 1258 1259 int __init kvm_sys_reg_table_init(void); 1260 struct sys_reg_desc; 1261 int __init populate_sysreg_config(const struct sys_reg_desc *sr, 1262 unsigned int idx); 1263 int __init populate_nv_trap_config(void); 1264 1265 void kvm_calculate_traps(struct kvm_vcpu *vcpu); 1266 1267 /* MMIO helpers */ 1268 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data); 1269 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len); 1270 1271 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu); 1272 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa); 1273 1274 /* 1275 * Returns true if a Performance Monitoring Interrupt (PMI), a.k.a. perf event, 1276 * arrived in guest context. For arm64, any event that arrives while a vCPU is 1277 * loaded is considered to be "in guest". 1278 */ 1279 static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu) 1280 { 1281 return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu; 1282 } 1283 1284 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu); 1285 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu); 1286 void kvm_update_stolen_time(struct kvm_vcpu *vcpu); 1287 1288 bool kvm_arm_pvtime_supported(void); 1289 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu, 1290 struct kvm_device_attr *attr); 1291 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu, 1292 struct kvm_device_attr *attr); 1293 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu, 1294 struct kvm_device_attr *attr); 1295 1296 extern unsigned int __ro_after_init kvm_arm_vmid_bits; 1297 int __init kvm_arm_vmid_alloc_init(void); 1298 void __init kvm_arm_vmid_alloc_free(void); 1299 void kvm_arm_vmid_update(struct kvm_vmid *kvm_vmid); 1300 void kvm_arm_vmid_clear_active(void); 1301 1302 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch) 1303 { 1304 vcpu_arch->steal.base = INVALID_GPA; 1305 } 1306 1307 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch) 1308 { 1309 return (vcpu_arch->steal.base != INVALID_GPA); 1310 } 1311 1312 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); 1313 1314 DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data); 1315 1316 /* 1317 * How we access per-CPU host data depends on the where we access it from, 1318 * and the mode we're in: 1319 * 1320 * - VHE and nVHE hypervisor bits use their locally defined instance 1321 * 1322 * - the rest of the kernel use either the VHE or nVHE one, depending on 1323 * the mode we're running in. 1324 * 1325 * Unless we're in protected mode, fully deprivileged, and the nVHE 1326 * per-CPU stuff is exclusively accessible to the protected EL2 code. 1327 * In this case, the EL1 code uses the *VHE* data as its private state 1328 * (which makes sense in a way as there shouldn't be any shared state 1329 * between the host and the hypervisor). 1330 * 1331 * Yes, this is all totally trivial. Shoot me now. 1332 */ 1333 #if defined(__KVM_NVHE_HYPERVISOR__) || defined(__KVM_VHE_HYPERVISOR__) 1334 #define host_data_ptr(f) (&this_cpu_ptr(&kvm_host_data)->f) 1335 #else 1336 #define host_data_ptr(f) \ 1337 (static_branch_unlikely(&kvm_protected_mode_initialized) ? \ 1338 &this_cpu_ptr(&kvm_host_data)->f : \ 1339 &this_cpu_ptr_hyp_sym(kvm_host_data)->f) 1340 #endif 1341 1342 #define host_data_test_flag(flag) \ 1343 (test_bit(KVM_HOST_DATA_FLAG_##flag, host_data_ptr(flags))) 1344 #define host_data_set_flag(flag) \ 1345 set_bit(KVM_HOST_DATA_FLAG_##flag, host_data_ptr(flags)) 1346 #define host_data_clear_flag(flag) \ 1347 clear_bit(KVM_HOST_DATA_FLAG_##flag, host_data_ptr(flags)) 1348 1349 /* Check whether the FP regs are owned by the guest */ 1350 static inline bool guest_owns_fp_regs(void) 1351 { 1352 return *host_data_ptr(fp_owner) == FP_STATE_GUEST_OWNED; 1353 } 1354 1355 /* Check whether the FP regs are owned by the host */ 1356 static inline bool host_owns_fp_regs(void) 1357 { 1358 return *host_data_ptr(fp_owner) == FP_STATE_HOST_OWNED; 1359 } 1360 1361 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt) 1362 { 1363 /* The host's MPIDR is immutable, so let's set it up at boot time */ 1364 ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr(); 1365 } 1366 1367 static inline bool kvm_system_needs_idmapped_vectors(void) 1368 { 1369 return cpus_have_final_cap(ARM64_SPECTRE_V3A); 1370 } 1371 1372 void kvm_init_host_debug_data(void); 1373 void kvm_debug_init_vhe(void); 1374 void kvm_vcpu_load_debug(struct kvm_vcpu *vcpu); 1375 void kvm_vcpu_put_debug(struct kvm_vcpu *vcpu); 1376 void kvm_debug_set_guest_ownership(struct kvm_vcpu *vcpu); 1377 void kvm_debug_handle_oslar(struct kvm_vcpu *vcpu, u64 val); 1378 1379 #define kvm_vcpu_os_lock_enabled(vcpu) \ 1380 (!!(__vcpu_sys_reg(vcpu, OSLSR_EL1) & OSLSR_EL1_OSLK)) 1381 1382 #define kvm_debug_regs_in_use(vcpu) \ 1383 ((vcpu)->arch.debug_owner != VCPU_DEBUG_FREE) 1384 #define kvm_host_owns_debug_regs(vcpu) \ 1385 ((vcpu)->arch.debug_owner == VCPU_DEBUG_HOST_OWNED) 1386 #define kvm_guest_owns_debug_regs(vcpu) \ 1387 ((vcpu)->arch.debug_owner == VCPU_DEBUG_GUEST_OWNED) 1388 1389 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, 1390 struct kvm_device_attr *attr); 1391 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, 1392 struct kvm_device_attr *attr); 1393 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, 1394 struct kvm_device_attr *attr); 1395 1396 int kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm, 1397 struct kvm_arm_copy_mte_tags *copy_tags); 1398 int kvm_vm_ioctl_set_counter_offset(struct kvm *kvm, 1399 struct kvm_arm_counter_offset *offset); 1400 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, 1401 struct reg_mask_range *range); 1402 1403 /* Guest/host FPSIMD coordination helpers */ 1404 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu); 1405 void kvm_arch_vcpu_ctxflush_fp(struct kvm_vcpu *vcpu); 1406 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu); 1407 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu); 1408 1409 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr) 1410 { 1411 return (!has_vhe() && attr->exclude_host); 1412 } 1413 1414 #ifdef CONFIG_KVM 1415 void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr); 1416 void kvm_clr_pmu_events(u64 clr); 1417 bool kvm_set_pmuserenr(u64 val); 1418 void kvm_enable_trbe(void); 1419 void kvm_disable_trbe(void); 1420 void kvm_tracing_set_el1_configuration(u64 trfcr_while_in_guest); 1421 #else 1422 static inline void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr) {} 1423 static inline void kvm_clr_pmu_events(u64 clr) {} 1424 static inline bool kvm_set_pmuserenr(u64 val) 1425 { 1426 return false; 1427 } 1428 static inline void kvm_enable_trbe(void) {} 1429 static inline void kvm_disable_trbe(void) {} 1430 static inline void kvm_tracing_set_el1_configuration(u64 trfcr_while_in_guest) {} 1431 #endif 1432 1433 void kvm_vcpu_load_vhe(struct kvm_vcpu *vcpu); 1434 void kvm_vcpu_put_vhe(struct kvm_vcpu *vcpu); 1435 1436 int __init kvm_set_ipa_limit(void); 1437 u32 kvm_get_pa_bits(struct kvm *kvm); 1438 1439 #define __KVM_HAVE_ARCH_VM_ALLOC 1440 struct kvm *kvm_arch_alloc_vm(void); 1441 1442 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS 1443 1444 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS_RANGE 1445 1446 #define kvm_vm_is_protected(kvm) (is_protected_kvm_enabled() && (kvm)->arch.pkvm.is_protected) 1447 1448 #define vcpu_is_protected(vcpu) kvm_vm_is_protected((vcpu)->kvm) 1449 1450 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature); 1451 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu); 1452 1453 #define kvm_arm_vcpu_sve_finalized(vcpu) vcpu_get_flag(vcpu, VCPU_SVE_FINALIZED) 1454 1455 #define kvm_has_mte(kvm) \ 1456 (system_supports_mte() && \ 1457 test_bit(KVM_ARCH_FLAG_MTE_ENABLED, &(kvm)->arch.flags)) 1458 1459 #define kvm_supports_32bit_el0() \ 1460 (system_supports_32bit_el0() && \ 1461 !static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1462 1463 #define kvm_vm_has_ran_once(kvm) \ 1464 (test_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &(kvm)->arch.flags)) 1465 1466 static inline bool __vcpu_has_feature(const struct kvm_arch *ka, int feature) 1467 { 1468 return test_bit(feature, ka->vcpu_features); 1469 } 1470 1471 #define kvm_vcpu_has_feature(k, f) __vcpu_has_feature(&(k)->arch, (f)) 1472 #define vcpu_has_feature(v, f) __vcpu_has_feature(&(v)->kvm->arch, (f)) 1473 1474 #define kvm_vcpu_initialized(v) vcpu_get_flag(vcpu, VCPU_INITIALIZED) 1475 1476 int kvm_trng_call(struct kvm_vcpu *vcpu); 1477 #ifdef CONFIG_KVM 1478 extern phys_addr_t hyp_mem_base; 1479 extern phys_addr_t hyp_mem_size; 1480 void __init kvm_hyp_reserve(void); 1481 #else 1482 static inline void kvm_hyp_reserve(void) { } 1483 #endif 1484 1485 void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu); 1486 bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu); 1487 1488 static inline u64 *__vm_id_reg(struct kvm_arch *ka, u32 reg) 1489 { 1490 switch (reg) { 1491 case sys_reg(3, 0, 0, 1, 0) ... sys_reg(3, 0, 0, 7, 7): 1492 return &ka->id_regs[IDREG_IDX(reg)]; 1493 case SYS_CTR_EL0: 1494 return &ka->ctr_el0; 1495 case SYS_MIDR_EL1: 1496 return &ka->midr_el1; 1497 case SYS_REVIDR_EL1: 1498 return &ka->revidr_el1; 1499 case SYS_AIDR_EL1: 1500 return &ka->aidr_el1; 1501 default: 1502 WARN_ON_ONCE(1); 1503 return NULL; 1504 } 1505 } 1506 1507 #define kvm_read_vm_id_reg(kvm, reg) \ 1508 ({ u64 __val = *__vm_id_reg(&(kvm)->arch, reg); __val; }) 1509 1510 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val); 1511 1512 #define __expand_field_sign_unsigned(id, fld, val) \ 1513 ((u64)SYS_FIELD_VALUE(id, fld, val)) 1514 1515 #define __expand_field_sign_signed(id, fld, val) \ 1516 ({ \ 1517 u64 __val = SYS_FIELD_VALUE(id, fld, val); \ 1518 sign_extend64(__val, id##_##fld##_WIDTH - 1); \ 1519 }) 1520 1521 #define get_idreg_field_unsigned(kvm, id, fld) \ 1522 ({ \ 1523 u64 __val = kvm_read_vm_id_reg((kvm), SYS_##id); \ 1524 FIELD_GET(id##_##fld##_MASK, __val); \ 1525 }) 1526 1527 #define get_idreg_field_signed(kvm, id, fld) \ 1528 ({ \ 1529 u64 __val = get_idreg_field_unsigned(kvm, id, fld); \ 1530 sign_extend64(__val, id##_##fld##_WIDTH - 1); \ 1531 }) 1532 1533 #define get_idreg_field_enum(kvm, id, fld) \ 1534 get_idreg_field_unsigned(kvm, id, fld) 1535 1536 #define kvm_cmp_feat_signed(kvm, id, fld, op, limit) \ 1537 (get_idreg_field_signed((kvm), id, fld) op __expand_field_sign_signed(id, fld, limit)) 1538 1539 #define kvm_cmp_feat_unsigned(kvm, id, fld, op, limit) \ 1540 (get_idreg_field_unsigned((kvm), id, fld) op __expand_field_sign_unsigned(id, fld, limit)) 1541 1542 #define kvm_cmp_feat(kvm, id, fld, op, limit) \ 1543 (id##_##fld##_SIGNED ? \ 1544 kvm_cmp_feat_signed(kvm, id, fld, op, limit) : \ 1545 kvm_cmp_feat_unsigned(kvm, id, fld, op, limit)) 1546 1547 #define __kvm_has_feat(kvm, id, fld, limit) \ 1548 kvm_cmp_feat(kvm, id, fld, >=, limit) 1549 1550 #define kvm_has_feat(kvm, ...) __kvm_has_feat(kvm, __VA_ARGS__) 1551 1552 #define __kvm_has_feat_enum(kvm, id, fld, val) \ 1553 kvm_cmp_feat_unsigned(kvm, id, fld, ==, val) 1554 1555 #define kvm_has_feat_enum(kvm, ...) __kvm_has_feat_enum(kvm, __VA_ARGS__) 1556 1557 #define kvm_has_feat_range(kvm, id, fld, min, max) \ 1558 (kvm_cmp_feat(kvm, id, fld, >=, min) && \ 1559 kvm_cmp_feat(kvm, id, fld, <=, max)) 1560 1561 /* Check for a given level of PAuth support */ 1562 #define kvm_has_pauth(k, l) \ 1563 ({ \ 1564 bool pa, pi, pa3; \ 1565 \ 1566 pa = kvm_has_feat((k), ID_AA64ISAR1_EL1, APA, l); \ 1567 pa &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPA, IMP); \ 1568 pi = kvm_has_feat((k), ID_AA64ISAR1_EL1, API, l); \ 1569 pi &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPI, IMP); \ 1570 pa3 = kvm_has_feat((k), ID_AA64ISAR2_EL1, APA3, l); \ 1571 pa3 &= kvm_has_feat((k), ID_AA64ISAR2_EL1, GPA3, IMP); \ 1572 \ 1573 (pa + pi + pa3) == 1; \ 1574 }) 1575 1576 #define kvm_has_fpmr(k) \ 1577 (system_supports_fpmr() && \ 1578 kvm_has_feat((k), ID_AA64PFR2_EL1, FPMR, IMP)) 1579 1580 #define kvm_has_tcr2(k) \ 1581 (kvm_has_feat((k), ID_AA64MMFR3_EL1, TCRX, IMP)) 1582 1583 #define kvm_has_s1pie(k) \ 1584 (kvm_has_feat((k), ID_AA64MMFR3_EL1, S1PIE, IMP)) 1585 1586 #define kvm_has_s1poe(k) \ 1587 (kvm_has_feat((k), ID_AA64MMFR3_EL1, S1POE, IMP)) 1588 1589 #define kvm_has_ras(k) \ 1590 (kvm_has_feat((k), ID_AA64PFR0_EL1, RAS, IMP)) 1591 1592 #define kvm_has_sctlr2(k) \ 1593 (kvm_has_feat((k), ID_AA64MMFR3_EL1, SCTLRX, IMP)) 1594 1595 static inline bool kvm_arch_has_irq_bypass(void) 1596 { 1597 return true; 1598 } 1599 1600 void compute_fgu(struct kvm *kvm, enum fgt_group_id fgt); 1601 void get_reg_fixed_bits(struct kvm *kvm, enum vcpu_sysreg reg, u64 *res0, u64 *res1); 1602 void check_feature_map(void); 1603 1604 1605 #endif /* __ARM64_KVM_HOST_H__ */ 1606