1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/asm/kvm_host.h: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 */ 10 11 #ifndef __ARM64_KVM_HOST_H__ 12 #define __ARM64_KVM_HOST_H__ 13 14 #include <linux/arm-smccc.h> 15 #include <linux/bitmap.h> 16 #include <linux/types.h> 17 #include <linux/jump_label.h> 18 #include <linux/kvm_types.h> 19 #include <linux/maple_tree.h> 20 #include <linux/percpu.h> 21 #include <linux/psci.h> 22 #include <asm/arch_gicv3.h> 23 #include <asm/barrier.h> 24 #include <asm/cpufeature.h> 25 #include <asm/cputype.h> 26 #include <asm/daifflags.h> 27 #include <asm/fpsimd.h> 28 #include <asm/kvm.h> 29 #include <asm/kvm_asm.h> 30 #include <asm/vncr_mapping.h> 31 32 #define __KVM_HAVE_ARCH_INTC_INITIALIZED 33 34 #define KVM_HALT_POLL_NS_DEFAULT 500000 35 36 #include <kvm/arm_vgic.h> 37 #include <kvm/arm_arch_timer.h> 38 #include <kvm/arm_pmu.h> 39 40 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS 41 42 #define KVM_VCPU_MAX_FEATURES 7 43 #define KVM_VCPU_VALID_FEATURES (BIT(KVM_VCPU_MAX_FEATURES) - 1) 44 45 #define KVM_REQ_SLEEP \ 46 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 47 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1) 48 #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2) 49 #define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(3) 50 #define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4) 51 #define KVM_REQ_RELOAD_PMU KVM_ARCH_REQ(5) 52 #define KVM_REQ_SUSPEND KVM_ARCH_REQ(6) 53 #define KVM_REQ_RESYNC_PMU_EL0 KVM_ARCH_REQ(7) 54 55 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \ 56 KVM_DIRTY_LOG_INITIALLY_SET) 57 58 #define KVM_HAVE_MMU_RWLOCK 59 60 /* 61 * Mode of operation configurable with kvm-arm.mode early param. 62 * See Documentation/admin-guide/kernel-parameters.txt for more information. 63 */ 64 enum kvm_mode { 65 KVM_MODE_DEFAULT, 66 KVM_MODE_PROTECTED, 67 KVM_MODE_NV, 68 KVM_MODE_NONE, 69 }; 70 #ifdef CONFIG_KVM 71 enum kvm_mode kvm_get_mode(void); 72 #else 73 static inline enum kvm_mode kvm_get_mode(void) { return KVM_MODE_NONE; }; 74 #endif 75 76 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use); 77 78 extern unsigned int __ro_after_init kvm_sve_max_vl; 79 int __init kvm_arm_init_sve(void); 80 81 u32 __attribute_const__ kvm_target_cpu(void); 82 void kvm_reset_vcpu(struct kvm_vcpu *vcpu); 83 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu); 84 85 struct kvm_hyp_memcache { 86 phys_addr_t head; 87 unsigned long nr_pages; 88 }; 89 90 static inline void push_hyp_memcache(struct kvm_hyp_memcache *mc, 91 phys_addr_t *p, 92 phys_addr_t (*to_pa)(void *virt)) 93 { 94 *p = mc->head; 95 mc->head = to_pa(p); 96 mc->nr_pages++; 97 } 98 99 static inline void *pop_hyp_memcache(struct kvm_hyp_memcache *mc, 100 void *(*to_va)(phys_addr_t phys)) 101 { 102 phys_addr_t *p = to_va(mc->head); 103 104 if (!mc->nr_pages) 105 return NULL; 106 107 mc->head = *p; 108 mc->nr_pages--; 109 110 return p; 111 } 112 113 static inline int __topup_hyp_memcache(struct kvm_hyp_memcache *mc, 114 unsigned long min_pages, 115 void *(*alloc_fn)(void *arg), 116 phys_addr_t (*to_pa)(void *virt), 117 void *arg) 118 { 119 while (mc->nr_pages < min_pages) { 120 phys_addr_t *p = alloc_fn(arg); 121 122 if (!p) 123 return -ENOMEM; 124 push_hyp_memcache(mc, p, to_pa); 125 } 126 127 return 0; 128 } 129 130 static inline void __free_hyp_memcache(struct kvm_hyp_memcache *mc, 131 void (*free_fn)(void *virt, void *arg), 132 void *(*to_va)(phys_addr_t phys), 133 void *arg) 134 { 135 while (mc->nr_pages) 136 free_fn(pop_hyp_memcache(mc, to_va), arg); 137 } 138 139 void free_hyp_memcache(struct kvm_hyp_memcache *mc); 140 int topup_hyp_memcache(struct kvm_hyp_memcache *mc, unsigned long min_pages); 141 142 struct kvm_vmid { 143 atomic64_t id; 144 }; 145 146 struct kvm_s2_mmu { 147 struct kvm_vmid vmid; 148 149 /* 150 * stage2 entry level table 151 * 152 * Two kvm_s2_mmu structures in the same VM can point to the same 153 * pgd here. This happens when running a guest using a 154 * translation regime that isn't affected by its own stage-2 155 * translation, such as a non-VHE hypervisor running at vEL2, or 156 * for vEL1/EL0 with vHCR_EL2.VM == 0. In that case, we use the 157 * canonical stage-2 page tables. 158 */ 159 phys_addr_t pgd_phys; 160 struct kvm_pgtable *pgt; 161 162 /* 163 * VTCR value used on the host. For a non-NV guest (or a NV 164 * guest that runs in a context where its own S2 doesn't 165 * apply), its T0SZ value reflects that of the IPA size. 166 * 167 * For a shadow S2 MMU, T0SZ reflects the PARange exposed to 168 * the guest. 169 */ 170 u64 vtcr; 171 172 /* The last vcpu id that ran on each physical CPU */ 173 int __percpu *last_vcpu_ran; 174 175 #define KVM_ARM_EAGER_SPLIT_CHUNK_SIZE_DEFAULT 0 176 /* 177 * Memory cache used to split 178 * KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE worth of huge pages. It 179 * is used to allocate stage2 page tables while splitting huge 180 * pages. The choice of KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE 181 * influences both the capacity of the split page cache, and 182 * how often KVM reschedules. Be wary of raising CHUNK_SIZE 183 * too high. 184 * 185 * Protected by kvm->slots_lock. 186 */ 187 struct kvm_mmu_memory_cache split_page_cache; 188 uint64_t split_page_chunk_size; 189 190 struct kvm_arch *arch; 191 }; 192 193 struct kvm_arch_memory_slot { 194 }; 195 196 /** 197 * struct kvm_smccc_features: Descriptor of the hypercall services exposed to the guests 198 * 199 * @std_bmap: Bitmap of standard secure service calls 200 * @std_hyp_bmap: Bitmap of standard hypervisor service calls 201 * @vendor_hyp_bmap: Bitmap of vendor specific hypervisor service calls 202 */ 203 struct kvm_smccc_features { 204 unsigned long std_bmap; 205 unsigned long std_hyp_bmap; 206 unsigned long vendor_hyp_bmap; 207 }; 208 209 typedef unsigned int pkvm_handle_t; 210 211 struct kvm_protected_vm { 212 pkvm_handle_t handle; 213 struct kvm_hyp_memcache teardown_mc; 214 bool enabled; 215 }; 216 217 struct kvm_mpidr_data { 218 u64 mpidr_mask; 219 DECLARE_FLEX_ARRAY(u16, cmpidr_to_idx); 220 }; 221 222 static inline u16 kvm_mpidr_index(struct kvm_mpidr_data *data, u64 mpidr) 223 { 224 unsigned long mask = data->mpidr_mask; 225 u64 aff = mpidr & MPIDR_HWID_BITMASK; 226 int nbits, bit, bit_idx = 0; 227 u16 index = 0; 228 229 /* 230 * If this looks like RISC-V's BEXT or x86's PEXT 231 * instructions, it isn't by accident. 232 */ 233 nbits = fls(mask); 234 for_each_set_bit(bit, &mask, nbits) { 235 index |= (aff & BIT(bit)) >> (bit - bit_idx); 236 bit_idx++; 237 } 238 239 return index; 240 } 241 242 struct kvm_sysreg_masks; 243 244 enum fgt_group_id { 245 __NO_FGT_GROUP__, 246 HFGxTR_GROUP, 247 HDFGRTR_GROUP, 248 HDFGWTR_GROUP = HDFGRTR_GROUP, 249 HFGITR_GROUP, 250 HAFGRTR_GROUP, 251 252 /* Must be last */ 253 __NR_FGT_GROUP_IDS__ 254 }; 255 256 struct kvm_arch { 257 struct kvm_s2_mmu mmu; 258 259 /* 260 * Fine-Grained UNDEF, mimicking the FGT layout defined by the 261 * architecture. We track them globally, as we present the 262 * same feature-set to all vcpus. 263 * 264 * Index 0 is currently spare. 265 */ 266 u64 fgu[__NR_FGT_GROUP_IDS__]; 267 268 /* Interrupt controller */ 269 struct vgic_dist vgic; 270 271 /* Timers */ 272 struct arch_timer_vm_data timer_data; 273 274 /* Mandated version of PSCI */ 275 u32 psci_version; 276 277 /* Protects VM-scoped configuration data */ 278 struct mutex config_lock; 279 280 /* 281 * If we encounter a data abort without valid instruction syndrome 282 * information, report this to user space. User space can (and 283 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is 284 * supported. 285 */ 286 #define KVM_ARCH_FLAG_RETURN_NISV_IO_ABORT_TO_USER 0 287 /* Memory Tagging Extension enabled for the guest */ 288 #define KVM_ARCH_FLAG_MTE_ENABLED 1 289 /* At least one vCPU has ran in the VM */ 290 #define KVM_ARCH_FLAG_HAS_RAN_ONCE 2 291 /* The vCPU feature set for the VM is configured */ 292 #define KVM_ARCH_FLAG_VCPU_FEATURES_CONFIGURED 3 293 /* PSCI SYSTEM_SUSPEND enabled for the guest */ 294 #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED 4 295 /* VM counter offset */ 296 #define KVM_ARCH_FLAG_VM_COUNTER_OFFSET 5 297 /* Timer PPIs made immutable */ 298 #define KVM_ARCH_FLAG_TIMER_PPIS_IMMUTABLE 6 299 /* Initial ID reg values loaded */ 300 #define KVM_ARCH_FLAG_ID_REGS_INITIALIZED 7 301 /* Fine-Grained UNDEF initialised */ 302 #define KVM_ARCH_FLAG_FGU_INITIALIZED 8 303 unsigned long flags; 304 305 /* VM-wide vCPU feature set */ 306 DECLARE_BITMAP(vcpu_features, KVM_VCPU_MAX_FEATURES); 307 308 /* MPIDR to vcpu index mapping, optional */ 309 struct kvm_mpidr_data *mpidr_data; 310 311 /* 312 * VM-wide PMU filter, implemented as a bitmap and big enough for 313 * up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+). 314 */ 315 unsigned long *pmu_filter; 316 struct arm_pmu *arm_pmu; 317 318 cpumask_var_t supported_cpus; 319 320 /* PMCR_EL0.N value for the guest */ 321 u8 pmcr_n; 322 323 /* Iterator for idreg debugfs */ 324 u8 idreg_debugfs_iter; 325 326 /* Hypercall features firmware registers' descriptor */ 327 struct kvm_smccc_features smccc_feat; 328 struct maple_tree smccc_filter; 329 330 /* 331 * Emulated CPU ID registers per VM 332 * (Op0, Op1, CRn, CRm, Op2) of the ID registers to be saved in it 333 * is (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8. 334 * 335 * These emulated idregs are VM-wide, but accessed from the context of a vCPU. 336 * Atomic access to multiple idregs are guarded by kvm_arch.config_lock. 337 */ 338 #define IDREG_IDX(id) (((sys_reg_CRm(id) - 1) << 3) | sys_reg_Op2(id)) 339 #define IDX_IDREG(idx) sys_reg(3, 0, 0, ((idx) >> 3) + 1, (idx) & Op2_mask) 340 #define IDREG(kvm, id) ((kvm)->arch.id_regs[IDREG_IDX(id)]) 341 #define KVM_ARM_ID_REG_NUM (IDREG_IDX(sys_reg(3, 0, 0, 7, 7)) + 1) 342 u64 id_regs[KVM_ARM_ID_REG_NUM]; 343 344 /* Masks for VNCR-baked sysregs */ 345 struct kvm_sysreg_masks *sysreg_masks; 346 347 /* 348 * For an untrusted host VM, 'pkvm.handle' is used to lookup 349 * the associated pKVM instance in the hypervisor. 350 */ 351 struct kvm_protected_vm pkvm; 352 }; 353 354 struct kvm_vcpu_fault_info { 355 u64 esr_el2; /* Hyp Syndrom Register */ 356 u64 far_el2; /* Hyp Fault Address Register */ 357 u64 hpfar_el2; /* Hyp IPA Fault Address Register */ 358 u64 disr_el1; /* Deferred [SError] Status Register */ 359 }; 360 361 /* 362 * VNCR() just places the VNCR_capable registers in the enum after 363 * __VNCR_START__, and the value (after correction) to be an 8-byte offset 364 * from the VNCR base. As we don't require the enum to be otherwise ordered, 365 * we need the terrible hack below to ensure that we correctly size the 366 * sys_regs array, no matter what. 367 * 368 * The __MAX__ macro has been lifted from Sean Eron Anderson's wonderful 369 * treasure trove of bit hacks: 370 * https://graphics.stanford.edu/~seander/bithacks.html#IntegerMinOrMax 371 */ 372 #define __MAX__(x,y) ((x) ^ (((x) ^ (y)) & -((x) < (y)))) 373 #define VNCR(r) \ 374 __before_##r, \ 375 r = __VNCR_START__ + ((VNCR_ ## r) / 8), \ 376 __after_##r = __MAX__(__before_##r - 1, r) 377 378 enum vcpu_sysreg { 379 __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ 380 MPIDR_EL1, /* MultiProcessor Affinity Register */ 381 CLIDR_EL1, /* Cache Level ID Register */ 382 CSSELR_EL1, /* Cache Size Selection Register */ 383 TPIDR_EL0, /* Thread ID, User R/W */ 384 TPIDRRO_EL0, /* Thread ID, User R/O */ 385 TPIDR_EL1, /* Thread ID, Privileged */ 386 CNTKCTL_EL1, /* Timer Control Register (EL1) */ 387 PAR_EL1, /* Physical Address Register */ 388 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ 389 OSLSR_EL1, /* OS Lock Status Register */ 390 DISR_EL1, /* Deferred Interrupt Status Register */ 391 392 /* Performance Monitors Registers */ 393 PMCR_EL0, /* Control Register */ 394 PMSELR_EL0, /* Event Counter Selection Register */ 395 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */ 396 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30, 397 PMCCNTR_EL0, /* Cycle Counter Register */ 398 PMEVTYPER0_EL0, /* Event Type Register (0-30) */ 399 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30, 400 PMCCFILTR_EL0, /* Cycle Count Filter Register */ 401 PMCNTENSET_EL0, /* Count Enable Set Register */ 402 PMINTENSET_EL1, /* Interrupt Enable Set Register */ 403 PMOVSSET_EL0, /* Overflow Flag Status Set Register */ 404 PMUSERENR_EL0, /* User Enable Register */ 405 406 /* Pointer Authentication Registers in a strict increasing order. */ 407 APIAKEYLO_EL1, 408 APIAKEYHI_EL1, 409 APIBKEYLO_EL1, 410 APIBKEYHI_EL1, 411 APDAKEYLO_EL1, 412 APDAKEYHI_EL1, 413 APDBKEYLO_EL1, 414 APDBKEYHI_EL1, 415 APGAKEYLO_EL1, 416 APGAKEYHI_EL1, 417 418 /* Memory Tagging Extension registers */ 419 RGSR_EL1, /* Random Allocation Tag Seed Register */ 420 GCR_EL1, /* Tag Control Register */ 421 TFSRE0_EL1, /* Tag Fault Status Register (EL0) */ 422 423 /* 32bit specific registers. */ 424 DACR32_EL2, /* Domain Access Control Register */ 425 IFSR32_EL2, /* Instruction Fault Status Register */ 426 FPEXC32_EL2, /* Floating-Point Exception Control Register */ 427 DBGVCR32_EL2, /* Debug Vector Catch Register */ 428 429 /* EL2 registers */ 430 SCTLR_EL2, /* System Control Register (EL2) */ 431 ACTLR_EL2, /* Auxiliary Control Register (EL2) */ 432 MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */ 433 CPTR_EL2, /* Architectural Feature Trap Register (EL2) */ 434 HACR_EL2, /* Hypervisor Auxiliary Control Register */ 435 TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */ 436 TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */ 437 TCR_EL2, /* Translation Control Register (EL2) */ 438 SPSR_EL2, /* EL2 saved program status register */ 439 ELR_EL2, /* EL2 exception link register */ 440 AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */ 441 AFSR1_EL2, /* Auxiliary Fault Status Register 1 (EL2) */ 442 ESR_EL2, /* Exception Syndrome Register (EL2) */ 443 FAR_EL2, /* Fault Address Register (EL2) */ 444 HPFAR_EL2, /* Hypervisor IPA Fault Address Register */ 445 MAIR_EL2, /* Memory Attribute Indirection Register (EL2) */ 446 AMAIR_EL2, /* Auxiliary Memory Attribute Indirection Register (EL2) */ 447 VBAR_EL2, /* Vector Base Address Register (EL2) */ 448 RVBAR_EL2, /* Reset Vector Base Address Register */ 449 CONTEXTIDR_EL2, /* Context ID Register (EL2) */ 450 CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */ 451 SP_EL2, /* EL2 Stack Pointer */ 452 CNTHP_CTL_EL2, 453 CNTHP_CVAL_EL2, 454 CNTHV_CTL_EL2, 455 CNTHV_CVAL_EL2, 456 457 __VNCR_START__, /* Any VNCR-capable reg goes after this point */ 458 459 VNCR(SCTLR_EL1),/* System Control Register */ 460 VNCR(ACTLR_EL1),/* Auxiliary Control Register */ 461 VNCR(CPACR_EL1),/* Coprocessor Access Control */ 462 VNCR(ZCR_EL1), /* SVE Control */ 463 VNCR(TTBR0_EL1),/* Translation Table Base Register 0 */ 464 VNCR(TTBR1_EL1),/* Translation Table Base Register 1 */ 465 VNCR(TCR_EL1), /* Translation Control Register */ 466 VNCR(TCR2_EL1), /* Extended Translation Control Register */ 467 VNCR(ESR_EL1), /* Exception Syndrome Register */ 468 VNCR(AFSR0_EL1),/* Auxiliary Fault Status Register 0 */ 469 VNCR(AFSR1_EL1),/* Auxiliary Fault Status Register 1 */ 470 VNCR(FAR_EL1), /* Fault Address Register */ 471 VNCR(MAIR_EL1), /* Memory Attribute Indirection Register */ 472 VNCR(VBAR_EL1), /* Vector Base Address Register */ 473 VNCR(CONTEXTIDR_EL1), /* Context ID Register */ 474 VNCR(AMAIR_EL1),/* Aux Memory Attribute Indirection Register */ 475 VNCR(MDSCR_EL1),/* Monitor Debug System Control Register */ 476 VNCR(ELR_EL1), 477 VNCR(SP_EL1), 478 VNCR(SPSR_EL1), 479 VNCR(TFSR_EL1), /* Tag Fault Status Register (EL1) */ 480 VNCR(VPIDR_EL2),/* Virtualization Processor ID Register */ 481 VNCR(VMPIDR_EL2),/* Virtualization Multiprocessor ID Register */ 482 VNCR(HCR_EL2), /* Hypervisor Configuration Register */ 483 VNCR(HSTR_EL2), /* Hypervisor System Trap Register */ 484 VNCR(VTTBR_EL2),/* Virtualization Translation Table Base Register */ 485 VNCR(VTCR_EL2), /* Virtualization Translation Control Register */ 486 VNCR(TPIDR_EL2),/* EL2 Software Thread ID Register */ 487 VNCR(HCRX_EL2), /* Extended Hypervisor Configuration Register */ 488 489 /* Permission Indirection Extension registers */ 490 VNCR(PIR_EL1), /* Permission Indirection Register 1 (EL1) */ 491 VNCR(PIRE0_EL1), /* Permission Indirection Register 0 (EL1) */ 492 493 VNCR(HFGRTR_EL2), 494 VNCR(HFGWTR_EL2), 495 VNCR(HFGITR_EL2), 496 VNCR(HDFGRTR_EL2), 497 VNCR(HDFGWTR_EL2), 498 VNCR(HAFGRTR_EL2), 499 500 VNCR(CNTVOFF_EL2), 501 VNCR(CNTV_CVAL_EL0), 502 VNCR(CNTV_CTL_EL0), 503 VNCR(CNTP_CVAL_EL0), 504 VNCR(CNTP_CTL_EL0), 505 506 NR_SYS_REGS /* Nothing after this line! */ 507 }; 508 509 struct kvm_sysreg_masks { 510 struct { 511 u64 res0; 512 u64 res1; 513 } mask[NR_SYS_REGS - __VNCR_START__]; 514 }; 515 516 struct kvm_cpu_context { 517 struct user_pt_regs regs; /* sp = sp_el0 */ 518 519 u64 spsr_abt; 520 u64 spsr_und; 521 u64 spsr_irq; 522 u64 spsr_fiq; 523 524 struct user_fpsimd_state fp_regs; 525 526 u64 sys_regs[NR_SYS_REGS]; 527 528 struct kvm_vcpu *__hyp_running_vcpu; 529 530 /* This pointer has to be 4kB aligned. */ 531 u64 *vncr_array; 532 }; 533 534 /* 535 * This structure is instantiated on a per-CPU basis, and contains 536 * data that is: 537 * 538 * - tied to a single physical CPU, and 539 * - either have a lifetime that does not extend past vcpu_put() 540 * - or is an invariant for the lifetime of the system 541 * 542 * Use host_data_ptr(field) as a way to access a pointer to such a 543 * field. 544 */ 545 struct kvm_host_data { 546 struct kvm_cpu_context host_ctxt; 547 struct user_fpsimd_state *fpsimd_state; /* hyp VA */ 548 549 /* Ownership of the FP regs */ 550 enum { 551 FP_STATE_FREE, 552 FP_STATE_HOST_OWNED, 553 FP_STATE_GUEST_OWNED, 554 } fp_owner; 555 556 /* 557 * host_debug_state contains the host registers which are 558 * saved and restored during world switches. 559 */ 560 struct { 561 /* {Break,watch}point registers */ 562 struct kvm_guest_debug_arch regs; 563 /* Statistical profiling extension */ 564 u64 pmscr_el1; 565 /* Self-hosted trace */ 566 u64 trfcr_el1; 567 /* Values of trap registers for the host before guest entry. */ 568 u64 mdcr_el2; 569 } host_debug_state; 570 }; 571 572 struct kvm_host_psci_config { 573 /* PSCI version used by host. */ 574 u32 version; 575 u32 smccc_version; 576 577 /* Function IDs used by host if version is v0.1. */ 578 struct psci_0_1_function_ids function_ids_0_1; 579 580 bool psci_0_1_cpu_suspend_implemented; 581 bool psci_0_1_cpu_on_implemented; 582 bool psci_0_1_cpu_off_implemented; 583 bool psci_0_1_migrate_implemented; 584 }; 585 586 extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config); 587 #define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config) 588 589 extern s64 kvm_nvhe_sym(hyp_physvirt_offset); 590 #define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset) 591 592 extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS]; 593 #define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map) 594 595 struct vcpu_reset_state { 596 unsigned long pc; 597 unsigned long r0; 598 bool be; 599 bool reset; 600 }; 601 602 struct kvm_vcpu_arch { 603 struct kvm_cpu_context ctxt; 604 605 /* 606 * Guest floating point state 607 * 608 * The architecture has two main floating point extensions, 609 * the original FPSIMD and SVE. These have overlapping 610 * register views, with the FPSIMD V registers occupying the 611 * low 128 bits of the SVE Z registers. When the core 612 * floating point code saves the register state of a task it 613 * records which view it saved in fp_type. 614 */ 615 void *sve_state; 616 enum fp_type fp_type; 617 unsigned int sve_max_vl; 618 u64 svcr; 619 u64 fpmr; 620 621 /* Stage 2 paging state used by the hardware on next switch */ 622 struct kvm_s2_mmu *hw_mmu; 623 624 /* Values of trap registers for the guest. */ 625 u64 hcr_el2; 626 u64 hcrx_el2; 627 u64 mdcr_el2; 628 u64 cptr_el2; 629 630 /* Exception Information */ 631 struct kvm_vcpu_fault_info fault; 632 633 /* Configuration flags, set once and for all before the vcpu can run */ 634 u8 cflags; 635 636 /* Input flags to the hypervisor code, potentially cleared after use */ 637 u8 iflags; 638 639 /* State flags for kernel bookkeeping, unused by the hypervisor code */ 640 u8 sflags; 641 642 /* 643 * Don't run the guest (internal implementation need). 644 * 645 * Contrary to the flags above, this is set/cleared outside of 646 * a vcpu context, and thus cannot be mixed with the flags 647 * themselves (or the flag accesses need to be made atomic). 648 */ 649 bool pause; 650 651 /* 652 * We maintain more than a single set of debug registers to support 653 * debugging the guest from the host and to maintain separate host and 654 * guest state during world switches. vcpu_debug_state are the debug 655 * registers of the vcpu as the guest sees them. 656 * 657 * external_debug_state contains the debug values we want to debug the 658 * guest. This is set via the KVM_SET_GUEST_DEBUG ioctl. 659 * 660 * debug_ptr points to the set of debug registers that should be loaded 661 * onto the hardware when running the guest. 662 */ 663 struct kvm_guest_debug_arch *debug_ptr; 664 struct kvm_guest_debug_arch vcpu_debug_state; 665 struct kvm_guest_debug_arch external_debug_state; 666 667 /* VGIC state */ 668 struct vgic_cpu vgic_cpu; 669 struct arch_timer_cpu timer_cpu; 670 struct kvm_pmu pmu; 671 672 /* 673 * Guest registers we preserve during guest debugging. 674 * 675 * These shadow registers are updated by the kvm_handle_sys_reg 676 * trap handler if the guest accesses or updates them while we 677 * are using guest debug. 678 */ 679 struct { 680 u32 mdscr_el1; 681 bool pstate_ss; 682 } guest_debug_preserved; 683 684 /* vcpu power state */ 685 struct kvm_mp_state mp_state; 686 spinlock_t mp_state_lock; 687 688 /* Cache some mmu pages needed inside spinlock regions */ 689 struct kvm_mmu_memory_cache mmu_page_cache; 690 691 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */ 692 u64 vsesr_el2; 693 694 /* Additional reset state */ 695 struct vcpu_reset_state reset_state; 696 697 /* Guest PV state */ 698 struct { 699 u64 last_steal; 700 gpa_t base; 701 } steal; 702 703 /* Per-vcpu CCSIDR override or NULL */ 704 u32 *ccsidr; 705 }; 706 707 /* 708 * Each 'flag' is composed of a comma-separated triplet: 709 * 710 * - the flag-set it belongs to in the vcpu->arch structure 711 * - the value for that flag 712 * - the mask for that flag 713 * 714 * __vcpu_single_flag() builds such a triplet for a single-bit flag. 715 * unpack_vcpu_flag() extract the flag value from the triplet for 716 * direct use outside of the flag accessors. 717 */ 718 #define __vcpu_single_flag(_set, _f) _set, (_f), (_f) 719 720 #define __unpack_flag(_set, _f, _m) _f 721 #define unpack_vcpu_flag(...) __unpack_flag(__VA_ARGS__) 722 723 #define __build_check_flag(v, flagset, f, m) \ 724 do { \ 725 typeof(v->arch.flagset) *_fset; \ 726 \ 727 /* Check that the flags fit in the mask */ \ 728 BUILD_BUG_ON(HWEIGHT(m) != HWEIGHT((f) | (m))); \ 729 /* Check that the flags fit in the type */ \ 730 BUILD_BUG_ON((sizeof(*_fset) * 8) <= __fls(m)); \ 731 } while (0) 732 733 #define __vcpu_get_flag(v, flagset, f, m) \ 734 ({ \ 735 __build_check_flag(v, flagset, f, m); \ 736 \ 737 READ_ONCE(v->arch.flagset) & (m); \ 738 }) 739 740 /* 741 * Note that the set/clear accessors must be preempt-safe in order to 742 * avoid nesting them with load/put which also manipulate flags... 743 */ 744 #ifdef __KVM_NVHE_HYPERVISOR__ 745 /* the nVHE hypervisor is always non-preemptible */ 746 #define __vcpu_flags_preempt_disable() 747 #define __vcpu_flags_preempt_enable() 748 #else 749 #define __vcpu_flags_preempt_disable() preempt_disable() 750 #define __vcpu_flags_preempt_enable() preempt_enable() 751 #endif 752 753 #define __vcpu_set_flag(v, flagset, f, m) \ 754 do { \ 755 typeof(v->arch.flagset) *fset; \ 756 \ 757 __build_check_flag(v, flagset, f, m); \ 758 \ 759 fset = &v->arch.flagset; \ 760 __vcpu_flags_preempt_disable(); \ 761 if (HWEIGHT(m) > 1) \ 762 *fset &= ~(m); \ 763 *fset |= (f); \ 764 __vcpu_flags_preempt_enable(); \ 765 } while (0) 766 767 #define __vcpu_clear_flag(v, flagset, f, m) \ 768 do { \ 769 typeof(v->arch.flagset) *fset; \ 770 \ 771 __build_check_flag(v, flagset, f, m); \ 772 \ 773 fset = &v->arch.flagset; \ 774 __vcpu_flags_preempt_disable(); \ 775 *fset &= ~(m); \ 776 __vcpu_flags_preempt_enable(); \ 777 } while (0) 778 779 #define vcpu_get_flag(v, ...) __vcpu_get_flag((v), __VA_ARGS__) 780 #define vcpu_set_flag(v, ...) __vcpu_set_flag((v), __VA_ARGS__) 781 #define vcpu_clear_flag(v, ...) __vcpu_clear_flag((v), __VA_ARGS__) 782 783 /* SVE exposed to guest */ 784 #define GUEST_HAS_SVE __vcpu_single_flag(cflags, BIT(0)) 785 /* SVE config completed */ 786 #define VCPU_SVE_FINALIZED __vcpu_single_flag(cflags, BIT(1)) 787 /* PTRAUTH exposed to guest */ 788 #define GUEST_HAS_PTRAUTH __vcpu_single_flag(cflags, BIT(2)) 789 /* KVM_ARM_VCPU_INIT completed */ 790 #define VCPU_INITIALIZED __vcpu_single_flag(cflags, BIT(3)) 791 792 /* Exception pending */ 793 #define PENDING_EXCEPTION __vcpu_single_flag(iflags, BIT(0)) 794 /* 795 * PC increment. Overlaps with EXCEPT_MASK on purpose so that it can't 796 * be set together with an exception... 797 */ 798 #define INCREMENT_PC __vcpu_single_flag(iflags, BIT(1)) 799 /* Target EL/MODE (not a single flag, but let's abuse the macro) */ 800 #define EXCEPT_MASK __vcpu_single_flag(iflags, GENMASK(3, 1)) 801 802 /* Helpers to encode exceptions with minimum fuss */ 803 #define __EXCEPT_MASK_VAL unpack_vcpu_flag(EXCEPT_MASK) 804 #define __EXCEPT_SHIFT __builtin_ctzl(__EXCEPT_MASK_VAL) 805 #define __vcpu_except_flags(_f) iflags, (_f << __EXCEPT_SHIFT), __EXCEPT_MASK_VAL 806 807 /* 808 * When PENDING_EXCEPTION is set, EXCEPT_MASK can take the following 809 * values: 810 * 811 * For AArch32 EL1: 812 */ 813 #define EXCEPT_AA32_UND __vcpu_except_flags(0) 814 #define EXCEPT_AA32_IABT __vcpu_except_flags(1) 815 #define EXCEPT_AA32_DABT __vcpu_except_flags(2) 816 /* For AArch64: */ 817 #define EXCEPT_AA64_EL1_SYNC __vcpu_except_flags(0) 818 #define EXCEPT_AA64_EL1_IRQ __vcpu_except_flags(1) 819 #define EXCEPT_AA64_EL1_FIQ __vcpu_except_flags(2) 820 #define EXCEPT_AA64_EL1_SERR __vcpu_except_flags(3) 821 /* For AArch64 with NV: */ 822 #define EXCEPT_AA64_EL2_SYNC __vcpu_except_flags(4) 823 #define EXCEPT_AA64_EL2_IRQ __vcpu_except_flags(5) 824 #define EXCEPT_AA64_EL2_FIQ __vcpu_except_flags(6) 825 #define EXCEPT_AA64_EL2_SERR __vcpu_except_flags(7) 826 /* Guest debug is live */ 827 #define DEBUG_DIRTY __vcpu_single_flag(iflags, BIT(4)) 828 /* Save SPE context if active */ 829 #define DEBUG_STATE_SAVE_SPE __vcpu_single_flag(iflags, BIT(5)) 830 /* Save TRBE context if active */ 831 #define DEBUG_STATE_SAVE_TRBE __vcpu_single_flag(iflags, BIT(6)) 832 833 /* SVE enabled for host EL0 */ 834 #define HOST_SVE_ENABLED __vcpu_single_flag(sflags, BIT(0)) 835 /* SME enabled for EL0 */ 836 #define HOST_SME_ENABLED __vcpu_single_flag(sflags, BIT(1)) 837 /* Physical CPU not in supported_cpus */ 838 #define ON_UNSUPPORTED_CPU __vcpu_single_flag(sflags, BIT(2)) 839 /* WFIT instruction trapped */ 840 #define IN_WFIT __vcpu_single_flag(sflags, BIT(3)) 841 /* vcpu system registers loaded on physical CPU */ 842 #define SYSREGS_ON_CPU __vcpu_single_flag(sflags, BIT(4)) 843 /* Software step state is Active-pending */ 844 #define DBG_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(5)) 845 /* PMUSERENR for the guest EL0 is on physical CPU */ 846 #define PMUSERENR_ON_CPU __vcpu_single_flag(sflags, BIT(6)) 847 /* WFI instruction trapped */ 848 #define IN_WFI __vcpu_single_flag(sflags, BIT(7)) 849 850 851 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */ 852 #define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) + \ 853 sve_ffr_offset((vcpu)->arch.sve_max_vl)) 854 855 #define vcpu_sve_max_vq(vcpu) sve_vq_from_vl((vcpu)->arch.sve_max_vl) 856 857 #define vcpu_sve_state_size(vcpu) ({ \ 858 size_t __size_ret; \ 859 unsigned int __vcpu_vq; \ 860 \ 861 if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) { \ 862 __size_ret = 0; \ 863 } else { \ 864 __vcpu_vq = vcpu_sve_max_vq(vcpu); \ 865 __size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq); \ 866 } \ 867 \ 868 __size_ret; \ 869 }) 870 871 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \ 872 KVM_GUESTDBG_USE_SW_BP | \ 873 KVM_GUESTDBG_USE_HW | \ 874 KVM_GUESTDBG_SINGLESTEP) 875 876 #define vcpu_has_sve(vcpu) (system_supports_sve() && \ 877 vcpu_get_flag(vcpu, GUEST_HAS_SVE)) 878 879 #ifdef CONFIG_ARM64_PTR_AUTH 880 #define vcpu_has_ptrauth(vcpu) \ 881 ((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) || \ 882 cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) && \ 883 vcpu_get_flag(vcpu, GUEST_HAS_PTRAUTH)) 884 #else 885 #define vcpu_has_ptrauth(vcpu) false 886 #endif 887 888 #define vcpu_on_unsupported_cpu(vcpu) \ 889 vcpu_get_flag(vcpu, ON_UNSUPPORTED_CPU) 890 891 #define vcpu_set_on_unsupported_cpu(vcpu) \ 892 vcpu_set_flag(vcpu, ON_UNSUPPORTED_CPU) 893 894 #define vcpu_clear_on_unsupported_cpu(vcpu) \ 895 vcpu_clear_flag(vcpu, ON_UNSUPPORTED_CPU) 896 897 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.regs) 898 899 /* 900 * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the 901 * memory backed version of a register, and not the one most recently 902 * accessed by a running VCPU. For example, for userspace access or 903 * for system registers that are never context switched, but only 904 * emulated. 905 * 906 * Don't bother with VNCR-based accesses in the nVHE code, it has no 907 * business dealing with NV. 908 */ 909 static inline u64 *___ctxt_sys_reg(const struct kvm_cpu_context *ctxt, int r) 910 { 911 #if !defined (__KVM_NVHE_HYPERVISOR__) 912 if (unlikely(cpus_have_final_cap(ARM64_HAS_NESTED_VIRT) && 913 r >= __VNCR_START__ && ctxt->vncr_array)) 914 return &ctxt->vncr_array[r - __VNCR_START__]; 915 #endif 916 return (u64 *)&ctxt->sys_regs[r]; 917 } 918 919 #define __ctxt_sys_reg(c,r) \ 920 ({ \ 921 BUILD_BUG_ON(__builtin_constant_p(r) && \ 922 (r) >= NR_SYS_REGS); \ 923 ___ctxt_sys_reg(c, r); \ 924 }) 925 926 #define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r)) 927 928 u64 kvm_vcpu_sanitise_vncr_reg(const struct kvm_vcpu *, enum vcpu_sysreg); 929 #define __vcpu_sys_reg(v,r) \ 930 (*({ \ 931 const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \ 932 u64 *__r = __ctxt_sys_reg(ctxt, (r)); \ 933 if (vcpu_has_nv((v)) && (r) >= __VNCR_START__) \ 934 *__r = kvm_vcpu_sanitise_vncr_reg((v), (r)); \ 935 __r; \ 936 })) 937 938 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg); 939 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg); 940 941 static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val) 942 { 943 /* 944 * *** VHE ONLY *** 945 * 946 * System registers listed in the switch are not saved on every 947 * exit from the guest but are only saved on vcpu_put. 948 * 949 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but 950 * should never be listed below, because the guest cannot modify its 951 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's 952 * thread when emulating cross-VCPU communication. 953 */ 954 if (!has_vhe()) 955 return false; 956 957 switch (reg) { 958 case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break; 959 case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break; 960 case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break; 961 case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break; 962 case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break; 963 case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break; 964 case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break; 965 case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break; 966 case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break; 967 case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break; 968 case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break; 969 case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break; 970 case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break; 971 case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break; 972 case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break; 973 case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break; 974 case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break; 975 case ELR_EL1: *val = read_sysreg_s(SYS_ELR_EL12); break; 976 case SPSR_EL1: *val = read_sysreg_s(SYS_SPSR_EL12); break; 977 case PAR_EL1: *val = read_sysreg_par(); break; 978 case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break; 979 case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break; 980 case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break; 981 default: return false; 982 } 983 984 return true; 985 } 986 987 static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg) 988 { 989 /* 990 * *** VHE ONLY *** 991 * 992 * System registers listed in the switch are not restored on every 993 * entry to the guest but are only restored on vcpu_load. 994 * 995 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but 996 * should never be listed below, because the MPIDR should only be set 997 * once, before running the VCPU, and never changed later. 998 */ 999 if (!has_vhe()) 1000 return false; 1001 1002 switch (reg) { 1003 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break; 1004 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break; 1005 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break; 1006 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break; 1007 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break; 1008 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break; 1009 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break; 1010 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break; 1011 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break; 1012 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break; 1013 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break; 1014 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break; 1015 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break; 1016 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break; 1017 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break; 1018 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break; 1019 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break; 1020 case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break; 1021 case SPSR_EL1: write_sysreg_s(val, SYS_SPSR_EL12); break; 1022 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break; 1023 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break; 1024 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break; 1025 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break; 1026 default: return false; 1027 } 1028 1029 return true; 1030 } 1031 1032 struct kvm_vm_stat { 1033 struct kvm_vm_stat_generic generic; 1034 }; 1035 1036 struct kvm_vcpu_stat { 1037 struct kvm_vcpu_stat_generic generic; 1038 u64 hvc_exit_stat; 1039 u64 wfe_exit_stat; 1040 u64 wfi_exit_stat; 1041 u64 mmio_exit_user; 1042 u64 mmio_exit_kernel; 1043 u64 signal_exits; 1044 u64 exits; 1045 }; 1046 1047 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); 1048 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); 1049 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 1050 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 1051 1052 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu); 1053 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices); 1054 1055 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu, 1056 struct kvm_vcpu_events *events); 1057 1058 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu, 1059 struct kvm_vcpu_events *events); 1060 1061 void kvm_arm_halt_guest(struct kvm *kvm); 1062 void kvm_arm_resume_guest(struct kvm *kvm); 1063 1064 #define vcpu_has_run_once(vcpu) !!rcu_access_pointer((vcpu)->pid) 1065 1066 #ifndef __KVM_NVHE_HYPERVISOR__ 1067 #define kvm_call_hyp_nvhe(f, ...) \ 1068 ({ \ 1069 struct arm_smccc_res res; \ 1070 \ 1071 arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f), \ 1072 ##__VA_ARGS__, &res); \ 1073 WARN_ON(res.a0 != SMCCC_RET_SUCCESS); \ 1074 \ 1075 res.a1; \ 1076 }) 1077 1078 /* 1079 * The couple of isb() below are there to guarantee the same behaviour 1080 * on VHE as on !VHE, where the eret to EL1 acts as a context 1081 * synchronization event. 1082 */ 1083 #define kvm_call_hyp(f, ...) \ 1084 do { \ 1085 if (has_vhe()) { \ 1086 f(__VA_ARGS__); \ 1087 isb(); \ 1088 } else { \ 1089 kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 1090 } \ 1091 } while(0) 1092 1093 #define kvm_call_hyp_ret(f, ...) \ 1094 ({ \ 1095 typeof(f(__VA_ARGS__)) ret; \ 1096 \ 1097 if (has_vhe()) { \ 1098 ret = f(__VA_ARGS__); \ 1099 isb(); \ 1100 } else { \ 1101 ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 1102 } \ 1103 \ 1104 ret; \ 1105 }) 1106 #else /* __KVM_NVHE_HYPERVISOR__ */ 1107 #define kvm_call_hyp(f, ...) f(__VA_ARGS__) 1108 #define kvm_call_hyp_ret(f, ...) f(__VA_ARGS__) 1109 #define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__) 1110 #endif /* __KVM_NVHE_HYPERVISOR__ */ 1111 1112 int handle_exit(struct kvm_vcpu *vcpu, int exception_index); 1113 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index); 1114 1115 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu); 1116 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu); 1117 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu); 1118 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu); 1119 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu); 1120 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu); 1121 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu); 1122 1123 void kvm_sys_regs_create_debugfs(struct kvm *kvm); 1124 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu); 1125 1126 int __init kvm_sys_reg_table_init(void); 1127 struct sys_reg_desc; 1128 int __init populate_sysreg_config(const struct sys_reg_desc *sr, 1129 unsigned int idx); 1130 int __init populate_nv_trap_config(void); 1131 1132 bool lock_all_vcpus(struct kvm *kvm); 1133 void unlock_all_vcpus(struct kvm *kvm); 1134 1135 void kvm_init_sysreg(struct kvm_vcpu *); 1136 1137 /* MMIO helpers */ 1138 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data); 1139 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len); 1140 1141 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu); 1142 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa); 1143 1144 /* 1145 * Returns true if a Performance Monitoring Interrupt (PMI), a.k.a. perf event, 1146 * arrived in guest context. For arm64, any event that arrives while a vCPU is 1147 * loaded is considered to be "in guest". 1148 */ 1149 static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu) 1150 { 1151 return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu; 1152 } 1153 1154 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu); 1155 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu); 1156 void kvm_update_stolen_time(struct kvm_vcpu *vcpu); 1157 1158 bool kvm_arm_pvtime_supported(void); 1159 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu, 1160 struct kvm_device_attr *attr); 1161 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu, 1162 struct kvm_device_attr *attr); 1163 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu, 1164 struct kvm_device_attr *attr); 1165 1166 extern unsigned int __ro_after_init kvm_arm_vmid_bits; 1167 int __init kvm_arm_vmid_alloc_init(void); 1168 void __init kvm_arm_vmid_alloc_free(void); 1169 bool kvm_arm_vmid_update(struct kvm_vmid *kvm_vmid); 1170 void kvm_arm_vmid_clear_active(void); 1171 1172 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch) 1173 { 1174 vcpu_arch->steal.base = INVALID_GPA; 1175 } 1176 1177 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch) 1178 { 1179 return (vcpu_arch->steal.base != INVALID_GPA); 1180 } 1181 1182 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome); 1183 1184 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); 1185 1186 DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data); 1187 1188 /* 1189 * How we access per-CPU host data depends on the where we access it from, 1190 * and the mode we're in: 1191 * 1192 * - VHE and nVHE hypervisor bits use their locally defined instance 1193 * 1194 * - the rest of the kernel use either the VHE or nVHE one, depending on 1195 * the mode we're running in. 1196 * 1197 * Unless we're in protected mode, fully deprivileged, and the nVHE 1198 * per-CPU stuff is exclusively accessible to the protected EL2 code. 1199 * In this case, the EL1 code uses the *VHE* data as its private state 1200 * (which makes sense in a way as there shouldn't be any shared state 1201 * between the host and the hypervisor). 1202 * 1203 * Yes, this is all totally trivial. Shoot me now. 1204 */ 1205 #if defined(__KVM_NVHE_HYPERVISOR__) || defined(__KVM_VHE_HYPERVISOR__) 1206 #define host_data_ptr(f) (&this_cpu_ptr(&kvm_host_data)->f) 1207 #else 1208 #define host_data_ptr(f) \ 1209 (static_branch_unlikely(&kvm_protected_mode_initialized) ? \ 1210 &this_cpu_ptr(&kvm_host_data)->f : \ 1211 &this_cpu_ptr_hyp_sym(kvm_host_data)->f) 1212 #endif 1213 1214 /* Check whether the FP regs are owned by the guest */ 1215 static inline bool guest_owns_fp_regs(void) 1216 { 1217 return *host_data_ptr(fp_owner) == FP_STATE_GUEST_OWNED; 1218 } 1219 1220 /* Check whether the FP regs are owned by the host */ 1221 static inline bool host_owns_fp_regs(void) 1222 { 1223 return *host_data_ptr(fp_owner) == FP_STATE_HOST_OWNED; 1224 } 1225 1226 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt) 1227 { 1228 /* The host's MPIDR is immutable, so let's set it up at boot time */ 1229 ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr(); 1230 } 1231 1232 static inline bool kvm_system_needs_idmapped_vectors(void) 1233 { 1234 return cpus_have_final_cap(ARM64_SPECTRE_V3A); 1235 } 1236 1237 static inline void kvm_arch_sync_events(struct kvm *kvm) {} 1238 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {} 1239 1240 void kvm_arm_init_debug(void); 1241 void kvm_arm_vcpu_init_debug(struct kvm_vcpu *vcpu); 1242 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu); 1243 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu); 1244 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu); 1245 1246 #define kvm_vcpu_os_lock_enabled(vcpu) \ 1247 (!!(__vcpu_sys_reg(vcpu, OSLSR_EL1) & OSLSR_EL1_OSLK)) 1248 1249 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, 1250 struct kvm_device_attr *attr); 1251 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, 1252 struct kvm_device_attr *attr); 1253 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, 1254 struct kvm_device_attr *attr); 1255 1256 int kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm, 1257 struct kvm_arm_copy_mte_tags *copy_tags); 1258 int kvm_vm_ioctl_set_counter_offset(struct kvm *kvm, 1259 struct kvm_arm_counter_offset *offset); 1260 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, 1261 struct reg_mask_range *range); 1262 1263 /* Guest/host FPSIMD coordination helpers */ 1264 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu); 1265 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu); 1266 void kvm_arch_vcpu_ctxflush_fp(struct kvm_vcpu *vcpu); 1267 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu); 1268 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu); 1269 1270 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr) 1271 { 1272 return (!has_vhe() && attr->exclude_host); 1273 } 1274 1275 /* Flags for host debug state */ 1276 void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu); 1277 void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu); 1278 1279 #ifdef CONFIG_KVM 1280 void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr); 1281 void kvm_clr_pmu_events(u32 clr); 1282 bool kvm_set_pmuserenr(u64 val); 1283 #else 1284 static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {} 1285 static inline void kvm_clr_pmu_events(u32 clr) {} 1286 static inline bool kvm_set_pmuserenr(u64 val) 1287 { 1288 return false; 1289 } 1290 #endif 1291 1292 void kvm_vcpu_load_vhe(struct kvm_vcpu *vcpu); 1293 void kvm_vcpu_put_vhe(struct kvm_vcpu *vcpu); 1294 1295 int __init kvm_set_ipa_limit(void); 1296 1297 #define __KVM_HAVE_ARCH_VM_ALLOC 1298 struct kvm *kvm_arch_alloc_vm(void); 1299 1300 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS 1301 1302 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS_RANGE 1303 1304 #define kvm_vm_is_protected(kvm) (is_protected_kvm_enabled() && (kvm)->arch.pkvm.enabled) 1305 1306 #define vcpu_is_protected(vcpu) kvm_vm_is_protected((vcpu)->kvm) 1307 1308 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature); 1309 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu); 1310 1311 #define kvm_arm_vcpu_sve_finalized(vcpu) vcpu_get_flag(vcpu, VCPU_SVE_FINALIZED) 1312 1313 #define kvm_has_mte(kvm) \ 1314 (system_supports_mte() && \ 1315 test_bit(KVM_ARCH_FLAG_MTE_ENABLED, &(kvm)->arch.flags)) 1316 1317 #define kvm_supports_32bit_el0() \ 1318 (system_supports_32bit_el0() && \ 1319 !static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1320 1321 #define kvm_vm_has_ran_once(kvm) \ 1322 (test_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &(kvm)->arch.flags)) 1323 1324 static inline bool __vcpu_has_feature(const struct kvm_arch *ka, int feature) 1325 { 1326 return test_bit(feature, ka->vcpu_features); 1327 } 1328 1329 #define vcpu_has_feature(v, f) __vcpu_has_feature(&(v)->kvm->arch, (f)) 1330 1331 int kvm_trng_call(struct kvm_vcpu *vcpu); 1332 #ifdef CONFIG_KVM 1333 extern phys_addr_t hyp_mem_base; 1334 extern phys_addr_t hyp_mem_size; 1335 void __init kvm_hyp_reserve(void); 1336 #else 1337 static inline void kvm_hyp_reserve(void) { } 1338 #endif 1339 1340 void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu); 1341 bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu); 1342 1343 #define __expand_field_sign_unsigned(id, fld, val) \ 1344 ((u64)SYS_FIELD_VALUE(id, fld, val)) 1345 1346 #define __expand_field_sign_signed(id, fld, val) \ 1347 ({ \ 1348 u64 __val = SYS_FIELD_VALUE(id, fld, val); \ 1349 sign_extend64(__val, id##_##fld##_WIDTH - 1); \ 1350 }) 1351 1352 #define expand_field_sign(id, fld, val) \ 1353 (id##_##fld##_SIGNED ? \ 1354 __expand_field_sign_signed(id, fld, val) : \ 1355 __expand_field_sign_unsigned(id, fld, val)) 1356 1357 #define get_idreg_field_unsigned(kvm, id, fld) \ 1358 ({ \ 1359 u64 __val = IDREG((kvm), SYS_##id); \ 1360 FIELD_GET(id##_##fld##_MASK, __val); \ 1361 }) 1362 1363 #define get_idreg_field_signed(kvm, id, fld) \ 1364 ({ \ 1365 u64 __val = get_idreg_field_unsigned(kvm, id, fld); \ 1366 sign_extend64(__val, id##_##fld##_WIDTH - 1); \ 1367 }) 1368 1369 #define get_idreg_field_enum(kvm, id, fld) \ 1370 get_idreg_field_unsigned(kvm, id, fld) 1371 1372 #define get_idreg_field(kvm, id, fld) \ 1373 (id##_##fld##_SIGNED ? \ 1374 get_idreg_field_signed(kvm, id, fld) : \ 1375 get_idreg_field_unsigned(kvm, id, fld)) 1376 1377 #define kvm_has_feat(kvm, id, fld, limit) \ 1378 (get_idreg_field((kvm), id, fld) >= expand_field_sign(id, fld, limit)) 1379 1380 #define kvm_has_feat_enum(kvm, id, fld, val) \ 1381 (get_idreg_field_unsigned((kvm), id, fld) == __expand_field_sign_unsigned(id, fld, val)) 1382 1383 #define kvm_has_feat_range(kvm, id, fld, min, max) \ 1384 (get_idreg_field((kvm), id, fld) >= expand_field_sign(id, fld, min) && \ 1385 get_idreg_field((kvm), id, fld) <= expand_field_sign(id, fld, max)) 1386 1387 /* Check for a given level of PAuth support */ 1388 #define kvm_has_pauth(k, l) \ 1389 ({ \ 1390 bool pa, pi, pa3; \ 1391 \ 1392 pa = kvm_has_feat((k), ID_AA64ISAR1_EL1, APA, l); \ 1393 pa &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPA, IMP); \ 1394 pi = kvm_has_feat((k), ID_AA64ISAR1_EL1, API, l); \ 1395 pi &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPI, IMP); \ 1396 pa3 = kvm_has_feat((k), ID_AA64ISAR2_EL1, APA3, l); \ 1397 pa3 &= kvm_has_feat((k), ID_AA64ISAR2_EL1, GPA3, IMP); \ 1398 \ 1399 (pa + pi + pa3) == 1; \ 1400 }) 1401 1402 #endif /* __ARM64_KVM_HOST_H__ */ 1403