1 /* 2 * Copyright (C) 2012,2013 - ARM Ltd 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * Derived from arch/arm/include/asm/kvm_host.h: 6 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 7 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef __ARM64_KVM_HOST_H__ 23 #define __ARM64_KVM_HOST_H__ 24 25 #include <linux/types.h> 26 #include <linux/kvm_types.h> 27 #include <asm/cpufeature.h> 28 #include <asm/daifflags.h> 29 #include <asm/fpsimd.h> 30 #include <asm/kvm.h> 31 #include <asm/kvm_asm.h> 32 #include <asm/kvm_mmio.h> 33 34 #define __KVM_HAVE_ARCH_INTC_INITIALIZED 35 36 #define KVM_USER_MEM_SLOTS 512 37 #define KVM_HALT_POLL_NS_DEFAULT 500000 38 39 #include <kvm/arm_vgic.h> 40 #include <kvm/arm_arch_timer.h> 41 #include <kvm/arm_pmu.h> 42 43 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS 44 45 #define KVM_VCPU_MAX_FEATURES 4 46 47 #define KVM_REQ_SLEEP \ 48 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 49 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1) 50 51 int __attribute_const__ kvm_target_cpu(void); 52 int kvm_reset_vcpu(struct kvm_vcpu *vcpu); 53 int kvm_arch_dev_ioctl_check_extension(struct kvm *kvm, long ext); 54 void __extended_idmap_trampoline(phys_addr_t boot_pgd, phys_addr_t idmap_start); 55 56 struct kvm_arch { 57 /* The VMID generation used for the virt. memory system */ 58 u64 vmid_gen; 59 u32 vmid; 60 61 /* 1-level 2nd stage table and lock */ 62 spinlock_t pgd_lock; 63 pgd_t *pgd; 64 65 /* VTTBR value associated with above pgd and vmid */ 66 u64 vttbr; 67 68 /* The last vcpu id that ran on each physical CPU */ 69 int __percpu *last_vcpu_ran; 70 71 /* The maximum number of vCPUs depends on the used GIC model */ 72 int max_vcpus; 73 74 /* Interrupt controller */ 75 struct vgic_dist vgic; 76 }; 77 78 #define KVM_NR_MEM_OBJS 40 79 80 /* 81 * We don't want allocation failures within the mmu code, so we preallocate 82 * enough memory for a single page fault in a cache. 83 */ 84 struct kvm_mmu_memory_cache { 85 int nobjs; 86 void *objects[KVM_NR_MEM_OBJS]; 87 }; 88 89 struct kvm_vcpu_fault_info { 90 u32 esr_el2; /* Hyp Syndrom Register */ 91 u64 far_el2; /* Hyp Fault Address Register */ 92 u64 hpfar_el2; /* Hyp IPA Fault Address Register */ 93 u64 disr_el1; /* Deferred [SError] Status Register */ 94 }; 95 96 /* 97 * 0 is reserved as an invalid value. 98 * Order should be kept in sync with the save/restore code. 99 */ 100 enum vcpu_sysreg { 101 __INVALID_SYSREG__, 102 MPIDR_EL1, /* MultiProcessor Affinity Register */ 103 CSSELR_EL1, /* Cache Size Selection Register */ 104 SCTLR_EL1, /* System Control Register */ 105 ACTLR_EL1, /* Auxiliary Control Register */ 106 CPACR_EL1, /* Coprocessor Access Control */ 107 TTBR0_EL1, /* Translation Table Base Register 0 */ 108 TTBR1_EL1, /* Translation Table Base Register 1 */ 109 TCR_EL1, /* Translation Control Register */ 110 ESR_EL1, /* Exception Syndrome Register */ 111 AFSR0_EL1, /* Auxiliary Fault Status Register 0 */ 112 AFSR1_EL1, /* Auxiliary Fault Status Register 1 */ 113 FAR_EL1, /* Fault Address Register */ 114 MAIR_EL1, /* Memory Attribute Indirection Register */ 115 VBAR_EL1, /* Vector Base Address Register */ 116 CONTEXTIDR_EL1, /* Context ID Register */ 117 TPIDR_EL0, /* Thread ID, User R/W */ 118 TPIDRRO_EL0, /* Thread ID, User R/O */ 119 TPIDR_EL1, /* Thread ID, Privileged */ 120 AMAIR_EL1, /* Aux Memory Attribute Indirection Register */ 121 CNTKCTL_EL1, /* Timer Control Register (EL1) */ 122 PAR_EL1, /* Physical Address Register */ 123 MDSCR_EL1, /* Monitor Debug System Control Register */ 124 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ 125 DISR_EL1, /* Deferred Interrupt Status Register */ 126 127 /* Performance Monitors Registers */ 128 PMCR_EL0, /* Control Register */ 129 PMSELR_EL0, /* Event Counter Selection Register */ 130 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */ 131 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30, 132 PMCCNTR_EL0, /* Cycle Counter Register */ 133 PMEVTYPER0_EL0, /* Event Type Register (0-30) */ 134 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30, 135 PMCCFILTR_EL0, /* Cycle Count Filter Register */ 136 PMCNTENSET_EL0, /* Count Enable Set Register */ 137 PMINTENSET_EL1, /* Interrupt Enable Set Register */ 138 PMOVSSET_EL0, /* Overflow Flag Status Set Register */ 139 PMSWINC_EL0, /* Software Increment Register */ 140 PMUSERENR_EL0, /* User Enable Register */ 141 142 /* 32bit specific registers. Keep them at the end of the range */ 143 DACR32_EL2, /* Domain Access Control Register */ 144 IFSR32_EL2, /* Instruction Fault Status Register */ 145 FPEXC32_EL2, /* Floating-Point Exception Control Register */ 146 DBGVCR32_EL2, /* Debug Vector Catch Register */ 147 148 NR_SYS_REGS /* Nothing after this line! */ 149 }; 150 151 /* 32bit mapping */ 152 #define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */ 153 #define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */ 154 #define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */ 155 #define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */ 156 #define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */ 157 #define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */ 158 #define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */ 159 #define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */ 160 #define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */ 161 #define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */ 162 #define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */ 163 #define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */ 164 #define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */ 165 #define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */ 166 #define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */ 167 #define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */ 168 #define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */ 169 #define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */ 170 #define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */ 171 #define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */ 172 #define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */ 173 #define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */ 174 #define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */ 175 #define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */ 176 #define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */ 177 #define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */ 178 #define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */ 179 #define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */ 180 #define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */ 181 182 #define cp14_DBGDSCRext (MDSCR_EL1 * 2) 183 #define cp14_DBGBCR0 (DBGBCR0_EL1 * 2) 184 #define cp14_DBGBVR0 (DBGBVR0_EL1 * 2) 185 #define cp14_DBGBXVR0 (cp14_DBGBVR0 + 1) 186 #define cp14_DBGWCR0 (DBGWCR0_EL1 * 2) 187 #define cp14_DBGWVR0 (DBGWVR0_EL1 * 2) 188 #define cp14_DBGDCCINT (MDCCINT_EL1 * 2) 189 190 #define NR_COPRO_REGS (NR_SYS_REGS * 2) 191 192 struct kvm_cpu_context { 193 struct kvm_regs gp_regs; 194 union { 195 u64 sys_regs[NR_SYS_REGS]; 196 u32 copro[NR_COPRO_REGS]; 197 }; 198 199 struct kvm_vcpu *__hyp_running_vcpu; 200 }; 201 202 typedef struct kvm_cpu_context kvm_cpu_context_t; 203 204 struct kvm_vcpu_arch { 205 struct kvm_cpu_context ctxt; 206 207 /* HYP configuration */ 208 u64 hcr_el2; 209 u32 mdcr_el2; 210 211 /* Exception Information */ 212 struct kvm_vcpu_fault_info fault; 213 214 /* Guest debug state */ 215 u64 debug_flags; 216 217 /* 218 * We maintain more than a single set of debug registers to support 219 * debugging the guest from the host and to maintain separate host and 220 * guest state during world switches. vcpu_debug_state are the debug 221 * registers of the vcpu as the guest sees them. host_debug_state are 222 * the host registers which are saved and restored during 223 * world switches. external_debug_state contains the debug 224 * values we want to debug the guest. This is set via the 225 * KVM_SET_GUEST_DEBUG ioctl. 226 * 227 * debug_ptr points to the set of debug registers that should be loaded 228 * onto the hardware when running the guest. 229 */ 230 struct kvm_guest_debug_arch *debug_ptr; 231 struct kvm_guest_debug_arch vcpu_debug_state; 232 struct kvm_guest_debug_arch external_debug_state; 233 234 /* Pointer to host CPU context */ 235 kvm_cpu_context_t *host_cpu_context; 236 struct { 237 /* {Break,watch}point registers */ 238 struct kvm_guest_debug_arch regs; 239 /* Statistical profiling extension */ 240 u64 pmscr_el1; 241 } host_debug_state; 242 243 /* VGIC state */ 244 struct vgic_cpu vgic_cpu; 245 struct arch_timer_cpu timer_cpu; 246 struct kvm_pmu pmu; 247 248 /* 249 * Anything that is not used directly from assembly code goes 250 * here. 251 */ 252 253 /* 254 * Guest registers we preserve during guest debugging. 255 * 256 * These shadow registers are updated by the kvm_handle_sys_reg 257 * trap handler if the guest accesses or updates them while we 258 * are using guest debug. 259 */ 260 struct { 261 u32 mdscr_el1; 262 } guest_debug_preserved; 263 264 /* vcpu power-off state */ 265 bool power_off; 266 267 /* Don't run the guest (internal implementation need) */ 268 bool pause; 269 270 /* IO related fields */ 271 struct kvm_decode mmio_decode; 272 273 /* Interrupt related fields */ 274 u64 irq_lines; /* IRQ and FIQ levels */ 275 276 /* Cache some mmu pages needed inside spinlock regions */ 277 struct kvm_mmu_memory_cache mmu_page_cache; 278 279 /* Target CPU and feature flags */ 280 int target; 281 DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES); 282 283 /* Detect first run of a vcpu */ 284 bool has_run_once; 285 286 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */ 287 u64 vsesr_el2; 288 }; 289 290 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.gp_regs) 291 #define vcpu_sys_reg(v,r) ((v)->arch.ctxt.sys_regs[(r)]) 292 /* 293 * CP14 and CP15 live in the same array, as they are backed by the 294 * same system registers. 295 */ 296 #define vcpu_cp14(v,r) ((v)->arch.ctxt.copro[(r)]) 297 #define vcpu_cp15(v,r) ((v)->arch.ctxt.copro[(r)]) 298 299 #ifdef CONFIG_CPU_BIG_ENDIAN 300 #define vcpu_cp15_64_high(v,r) vcpu_cp15((v),(r)) 301 #define vcpu_cp15_64_low(v,r) vcpu_cp15((v),(r) + 1) 302 #else 303 #define vcpu_cp15_64_high(v,r) vcpu_cp15((v),(r) + 1) 304 #define vcpu_cp15_64_low(v,r) vcpu_cp15((v),(r)) 305 #endif 306 307 struct kvm_vm_stat { 308 ulong remote_tlb_flush; 309 }; 310 311 struct kvm_vcpu_stat { 312 u64 halt_successful_poll; 313 u64 halt_attempted_poll; 314 u64 halt_poll_invalid; 315 u64 halt_wakeup; 316 u64 hvc_exit_stat; 317 u64 wfe_exit_stat; 318 u64 wfi_exit_stat; 319 u64 mmio_exit_user; 320 u64 mmio_exit_kernel; 321 u64 exits; 322 }; 323 324 int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init); 325 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); 326 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); 327 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 328 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 329 330 #define KVM_ARCH_WANT_MMU_NOTIFIER 331 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva); 332 int kvm_unmap_hva_range(struct kvm *kvm, 333 unsigned long start, unsigned long end); 334 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); 335 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); 336 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); 337 338 struct kvm_vcpu *kvm_arm_get_running_vcpu(void); 339 struct kvm_vcpu * __percpu *kvm_get_running_vcpus(void); 340 void kvm_arm_halt_guest(struct kvm *kvm); 341 void kvm_arm_resume_guest(struct kvm *kvm); 342 343 u64 __kvm_call_hyp(void *hypfn, ...); 344 #define kvm_call_hyp(f, ...) __kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__) 345 346 void force_vm_exit(const cpumask_t *mask); 347 void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot); 348 349 int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, 350 int exception_index); 351 void handle_exit_early(struct kvm_vcpu *vcpu, struct kvm_run *run, 352 int exception_index); 353 354 int kvm_perf_init(void); 355 int kvm_perf_teardown(void); 356 357 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); 358 359 static inline void __cpu_init_hyp_mode(phys_addr_t pgd_ptr, 360 unsigned long hyp_stack_ptr, 361 unsigned long vector_ptr) 362 { 363 /* 364 * Call initialization code, and switch to the full blown HYP code. 365 * If the cpucaps haven't been finalized yet, something has gone very 366 * wrong, and hyp will crash and burn when it uses any 367 * cpus_have_const_cap() wrapper. 368 */ 369 BUG_ON(!static_branch_likely(&arm64_const_caps_ready)); 370 __kvm_call_hyp((void *)pgd_ptr, hyp_stack_ptr, vector_ptr); 371 } 372 373 static inline void kvm_arch_hardware_unsetup(void) {} 374 static inline void kvm_arch_sync_events(struct kvm *kvm) {} 375 static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {} 376 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {} 377 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} 378 379 void kvm_arm_init_debug(void); 380 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu); 381 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu); 382 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu); 383 bool kvm_arm_handle_step_debug(struct kvm_vcpu *vcpu, struct kvm_run *run); 384 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, 385 struct kvm_device_attr *attr); 386 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, 387 struct kvm_device_attr *attr); 388 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, 389 struct kvm_device_attr *attr); 390 391 static inline void __cpu_init_stage2(void) 392 { 393 u32 parange = kvm_call_hyp(__init_stage2_translation); 394 395 WARN_ONCE(parange < 40, 396 "PARange is %d bits, unsupported configuration!", parange); 397 } 398 399 /* 400 * All host FP/SIMD state is restored on guest exit, so nothing needs 401 * doing here except in the SVE case: 402 */ 403 static inline void kvm_fpsimd_flush_cpu_state(void) 404 { 405 if (system_supports_sve()) 406 sve_flush_cpu_state(); 407 } 408 409 static inline void kvm_arm_vhe_guest_enter(void) 410 { 411 local_daif_mask(); 412 } 413 414 static inline void kvm_arm_vhe_guest_exit(void) 415 { 416 local_daif_restore(DAIF_PROCCTX_NOIRQ); 417 } 418 #endif /* __ARM64_KVM_HOST_H__ */ 419