1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/asm/kvm_host.h: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 */ 10 11 #ifndef __ARM64_KVM_HOST_H__ 12 #define __ARM64_KVM_HOST_H__ 13 14 #include <linux/arm-smccc.h> 15 #include <linux/bitmap.h> 16 #include <linux/types.h> 17 #include <linux/jump_label.h> 18 #include <linux/kvm_types.h> 19 #include <linux/maple_tree.h> 20 #include <linux/percpu.h> 21 #include <linux/psci.h> 22 #include <asm/arch_gicv3.h> 23 #include <asm/barrier.h> 24 #include <asm/cpufeature.h> 25 #include <asm/cputype.h> 26 #include <asm/daifflags.h> 27 #include <asm/fpsimd.h> 28 #include <asm/kvm.h> 29 #include <asm/kvm_asm.h> 30 #include <asm/vncr_mapping.h> 31 32 #define __KVM_HAVE_ARCH_INTC_INITIALIZED 33 34 #define KVM_HALT_POLL_NS_DEFAULT 500000 35 36 #include <kvm/arm_vgic.h> 37 #include <kvm/arm_arch_timer.h> 38 #include <kvm/arm_pmu.h> 39 40 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS 41 42 #define KVM_VCPU_MAX_FEATURES 7 43 #define KVM_VCPU_VALID_FEATURES (BIT(KVM_VCPU_MAX_FEATURES) - 1) 44 45 #define KVM_REQ_SLEEP \ 46 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 47 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1) 48 #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2) 49 #define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(3) 50 #define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4) 51 #define KVM_REQ_RELOAD_PMU KVM_ARCH_REQ(5) 52 #define KVM_REQ_SUSPEND KVM_ARCH_REQ(6) 53 #define KVM_REQ_RESYNC_PMU_EL0 KVM_ARCH_REQ(7) 54 55 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \ 56 KVM_DIRTY_LOG_INITIALLY_SET) 57 58 #define KVM_HAVE_MMU_RWLOCK 59 60 /* 61 * Mode of operation configurable with kvm-arm.mode early param. 62 * See Documentation/admin-guide/kernel-parameters.txt for more information. 63 */ 64 enum kvm_mode { 65 KVM_MODE_DEFAULT, 66 KVM_MODE_PROTECTED, 67 KVM_MODE_NV, 68 KVM_MODE_NONE, 69 }; 70 #ifdef CONFIG_KVM 71 enum kvm_mode kvm_get_mode(void); 72 #else 73 static inline enum kvm_mode kvm_get_mode(void) { return KVM_MODE_NONE; }; 74 #endif 75 76 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use); 77 78 extern unsigned int __ro_after_init kvm_sve_max_vl; 79 int __init kvm_arm_init_sve(void); 80 81 u32 __attribute_const__ kvm_target_cpu(void); 82 void kvm_reset_vcpu(struct kvm_vcpu *vcpu); 83 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu); 84 85 struct kvm_hyp_memcache { 86 phys_addr_t head; 87 unsigned long nr_pages; 88 }; 89 90 static inline void push_hyp_memcache(struct kvm_hyp_memcache *mc, 91 phys_addr_t *p, 92 phys_addr_t (*to_pa)(void *virt)) 93 { 94 *p = mc->head; 95 mc->head = to_pa(p); 96 mc->nr_pages++; 97 } 98 99 static inline void *pop_hyp_memcache(struct kvm_hyp_memcache *mc, 100 void *(*to_va)(phys_addr_t phys)) 101 { 102 phys_addr_t *p = to_va(mc->head); 103 104 if (!mc->nr_pages) 105 return NULL; 106 107 mc->head = *p; 108 mc->nr_pages--; 109 110 return p; 111 } 112 113 static inline int __topup_hyp_memcache(struct kvm_hyp_memcache *mc, 114 unsigned long min_pages, 115 void *(*alloc_fn)(void *arg), 116 phys_addr_t (*to_pa)(void *virt), 117 void *arg) 118 { 119 while (mc->nr_pages < min_pages) { 120 phys_addr_t *p = alloc_fn(arg); 121 122 if (!p) 123 return -ENOMEM; 124 push_hyp_memcache(mc, p, to_pa); 125 } 126 127 return 0; 128 } 129 130 static inline void __free_hyp_memcache(struct kvm_hyp_memcache *mc, 131 void (*free_fn)(void *virt, void *arg), 132 void *(*to_va)(phys_addr_t phys), 133 void *arg) 134 { 135 while (mc->nr_pages) 136 free_fn(pop_hyp_memcache(mc, to_va), arg); 137 } 138 139 void free_hyp_memcache(struct kvm_hyp_memcache *mc); 140 int topup_hyp_memcache(struct kvm_hyp_memcache *mc, unsigned long min_pages); 141 142 struct kvm_vmid { 143 atomic64_t id; 144 }; 145 146 struct kvm_s2_mmu { 147 struct kvm_vmid vmid; 148 149 /* 150 * stage2 entry level table 151 * 152 * Two kvm_s2_mmu structures in the same VM can point to the same 153 * pgd here. This happens when running a guest using a 154 * translation regime that isn't affected by its own stage-2 155 * translation, such as a non-VHE hypervisor running at vEL2, or 156 * for vEL1/EL0 with vHCR_EL2.VM == 0. In that case, we use the 157 * canonical stage-2 page tables. 158 */ 159 phys_addr_t pgd_phys; 160 struct kvm_pgtable *pgt; 161 162 /* 163 * VTCR value used on the host. For a non-NV guest (or a NV 164 * guest that runs in a context where its own S2 doesn't 165 * apply), its T0SZ value reflects that of the IPA size. 166 * 167 * For a shadow S2 MMU, T0SZ reflects the PARange exposed to 168 * the guest. 169 */ 170 u64 vtcr; 171 172 /* The last vcpu id that ran on each physical CPU */ 173 int __percpu *last_vcpu_ran; 174 175 #define KVM_ARM_EAGER_SPLIT_CHUNK_SIZE_DEFAULT 0 176 /* 177 * Memory cache used to split 178 * KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE worth of huge pages. It 179 * is used to allocate stage2 page tables while splitting huge 180 * pages. The choice of KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE 181 * influences both the capacity of the split page cache, and 182 * how often KVM reschedules. Be wary of raising CHUNK_SIZE 183 * too high. 184 * 185 * Protected by kvm->slots_lock. 186 */ 187 struct kvm_mmu_memory_cache split_page_cache; 188 uint64_t split_page_chunk_size; 189 190 struct kvm_arch *arch; 191 }; 192 193 struct kvm_arch_memory_slot { 194 }; 195 196 /** 197 * struct kvm_smccc_features: Descriptor of the hypercall services exposed to the guests 198 * 199 * @std_bmap: Bitmap of standard secure service calls 200 * @std_hyp_bmap: Bitmap of standard hypervisor service calls 201 * @vendor_hyp_bmap: Bitmap of vendor specific hypervisor service calls 202 */ 203 struct kvm_smccc_features { 204 unsigned long std_bmap; 205 unsigned long std_hyp_bmap; 206 unsigned long vendor_hyp_bmap; 207 }; 208 209 typedef unsigned int pkvm_handle_t; 210 211 struct kvm_protected_vm { 212 pkvm_handle_t handle; 213 struct kvm_hyp_memcache teardown_mc; 214 bool enabled; 215 }; 216 217 struct kvm_mpidr_data { 218 u64 mpidr_mask; 219 DECLARE_FLEX_ARRAY(u16, cmpidr_to_idx); 220 }; 221 222 static inline u16 kvm_mpidr_index(struct kvm_mpidr_data *data, u64 mpidr) 223 { 224 unsigned long index = 0, mask = data->mpidr_mask; 225 unsigned long aff = mpidr & MPIDR_HWID_BITMASK; 226 227 bitmap_gather(&index, &aff, &mask, fls(mask)); 228 229 return index; 230 } 231 232 struct kvm_sysreg_masks; 233 234 enum fgt_group_id { 235 __NO_FGT_GROUP__, 236 HFGxTR_GROUP, 237 HDFGRTR_GROUP, 238 HDFGWTR_GROUP = HDFGRTR_GROUP, 239 HFGITR_GROUP, 240 HAFGRTR_GROUP, 241 242 /* Must be last */ 243 __NR_FGT_GROUP_IDS__ 244 }; 245 246 struct kvm_arch { 247 struct kvm_s2_mmu mmu; 248 249 /* 250 * Fine-Grained UNDEF, mimicking the FGT layout defined by the 251 * architecture. We track them globally, as we present the 252 * same feature-set to all vcpus. 253 * 254 * Index 0 is currently spare. 255 */ 256 u64 fgu[__NR_FGT_GROUP_IDS__]; 257 258 /* Interrupt controller */ 259 struct vgic_dist vgic; 260 261 /* Timers */ 262 struct arch_timer_vm_data timer_data; 263 264 /* Mandated version of PSCI */ 265 u32 psci_version; 266 267 /* Protects VM-scoped configuration data */ 268 struct mutex config_lock; 269 270 /* 271 * If we encounter a data abort without valid instruction syndrome 272 * information, report this to user space. User space can (and 273 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is 274 * supported. 275 */ 276 #define KVM_ARCH_FLAG_RETURN_NISV_IO_ABORT_TO_USER 0 277 /* Memory Tagging Extension enabled for the guest */ 278 #define KVM_ARCH_FLAG_MTE_ENABLED 1 279 /* At least one vCPU has ran in the VM */ 280 #define KVM_ARCH_FLAG_HAS_RAN_ONCE 2 281 /* The vCPU feature set for the VM is configured */ 282 #define KVM_ARCH_FLAG_VCPU_FEATURES_CONFIGURED 3 283 /* PSCI SYSTEM_SUSPEND enabled for the guest */ 284 #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED 4 285 /* VM counter offset */ 286 #define KVM_ARCH_FLAG_VM_COUNTER_OFFSET 5 287 /* Timer PPIs made immutable */ 288 #define KVM_ARCH_FLAG_TIMER_PPIS_IMMUTABLE 6 289 /* Initial ID reg values loaded */ 290 #define KVM_ARCH_FLAG_ID_REGS_INITIALIZED 7 291 /* Fine-Grained UNDEF initialised */ 292 #define KVM_ARCH_FLAG_FGU_INITIALIZED 8 293 unsigned long flags; 294 295 /* VM-wide vCPU feature set */ 296 DECLARE_BITMAP(vcpu_features, KVM_VCPU_MAX_FEATURES); 297 298 /* MPIDR to vcpu index mapping, optional */ 299 struct kvm_mpidr_data *mpidr_data; 300 301 /* 302 * VM-wide PMU filter, implemented as a bitmap and big enough for 303 * up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+). 304 */ 305 unsigned long *pmu_filter; 306 struct arm_pmu *arm_pmu; 307 308 cpumask_var_t supported_cpus; 309 310 /* PMCR_EL0.N value for the guest */ 311 u8 pmcr_n; 312 313 /* Iterator for idreg debugfs */ 314 u8 idreg_debugfs_iter; 315 316 /* Hypercall features firmware registers' descriptor */ 317 struct kvm_smccc_features smccc_feat; 318 struct maple_tree smccc_filter; 319 320 /* 321 * Emulated CPU ID registers per VM 322 * (Op0, Op1, CRn, CRm, Op2) of the ID registers to be saved in it 323 * is (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8. 324 * 325 * These emulated idregs are VM-wide, but accessed from the context of a vCPU. 326 * Atomic access to multiple idregs are guarded by kvm_arch.config_lock. 327 */ 328 #define IDREG_IDX(id) (((sys_reg_CRm(id) - 1) << 3) | sys_reg_Op2(id)) 329 #define IDX_IDREG(idx) sys_reg(3, 0, 0, ((idx) >> 3) + 1, (idx) & Op2_mask) 330 #define IDREG(kvm, id) ((kvm)->arch.id_regs[IDREG_IDX(id)]) 331 #define KVM_ARM_ID_REG_NUM (IDREG_IDX(sys_reg(3, 0, 0, 7, 7)) + 1) 332 u64 id_regs[KVM_ARM_ID_REG_NUM]; 333 334 /* Masks for VNCR-baked sysregs */ 335 struct kvm_sysreg_masks *sysreg_masks; 336 337 /* 338 * For an untrusted host VM, 'pkvm.handle' is used to lookup 339 * the associated pKVM instance in the hypervisor. 340 */ 341 struct kvm_protected_vm pkvm; 342 }; 343 344 struct kvm_vcpu_fault_info { 345 u64 esr_el2; /* Hyp Syndrom Register */ 346 u64 far_el2; /* Hyp Fault Address Register */ 347 u64 hpfar_el2; /* Hyp IPA Fault Address Register */ 348 u64 disr_el1; /* Deferred [SError] Status Register */ 349 }; 350 351 /* 352 * VNCR() just places the VNCR_capable registers in the enum after 353 * __VNCR_START__, and the value (after correction) to be an 8-byte offset 354 * from the VNCR base. As we don't require the enum to be otherwise ordered, 355 * we need the terrible hack below to ensure that we correctly size the 356 * sys_regs array, no matter what. 357 * 358 * The __MAX__ macro has been lifted from Sean Eron Anderson's wonderful 359 * treasure trove of bit hacks: 360 * https://graphics.stanford.edu/~seander/bithacks.html#IntegerMinOrMax 361 */ 362 #define __MAX__(x,y) ((x) ^ (((x) ^ (y)) & -((x) < (y)))) 363 #define VNCR(r) \ 364 __before_##r, \ 365 r = __VNCR_START__ + ((VNCR_ ## r) / 8), \ 366 __after_##r = __MAX__(__before_##r - 1, r) 367 368 enum vcpu_sysreg { 369 __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ 370 MPIDR_EL1, /* MultiProcessor Affinity Register */ 371 CLIDR_EL1, /* Cache Level ID Register */ 372 CSSELR_EL1, /* Cache Size Selection Register */ 373 TPIDR_EL0, /* Thread ID, User R/W */ 374 TPIDRRO_EL0, /* Thread ID, User R/O */ 375 TPIDR_EL1, /* Thread ID, Privileged */ 376 CNTKCTL_EL1, /* Timer Control Register (EL1) */ 377 PAR_EL1, /* Physical Address Register */ 378 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ 379 OSLSR_EL1, /* OS Lock Status Register */ 380 DISR_EL1, /* Deferred Interrupt Status Register */ 381 382 /* Performance Monitors Registers */ 383 PMCR_EL0, /* Control Register */ 384 PMSELR_EL0, /* Event Counter Selection Register */ 385 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */ 386 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30, 387 PMCCNTR_EL0, /* Cycle Counter Register */ 388 PMEVTYPER0_EL0, /* Event Type Register (0-30) */ 389 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30, 390 PMCCFILTR_EL0, /* Cycle Count Filter Register */ 391 PMCNTENSET_EL0, /* Count Enable Set Register */ 392 PMINTENSET_EL1, /* Interrupt Enable Set Register */ 393 PMOVSSET_EL0, /* Overflow Flag Status Set Register */ 394 PMUSERENR_EL0, /* User Enable Register */ 395 396 /* Pointer Authentication Registers in a strict increasing order. */ 397 APIAKEYLO_EL1, 398 APIAKEYHI_EL1, 399 APIBKEYLO_EL1, 400 APIBKEYHI_EL1, 401 APDAKEYLO_EL1, 402 APDAKEYHI_EL1, 403 APDBKEYLO_EL1, 404 APDBKEYHI_EL1, 405 APGAKEYLO_EL1, 406 APGAKEYHI_EL1, 407 408 /* Memory Tagging Extension registers */ 409 RGSR_EL1, /* Random Allocation Tag Seed Register */ 410 GCR_EL1, /* Tag Control Register */ 411 TFSRE0_EL1, /* Tag Fault Status Register (EL0) */ 412 413 /* 32bit specific registers. */ 414 DACR32_EL2, /* Domain Access Control Register */ 415 IFSR32_EL2, /* Instruction Fault Status Register */ 416 FPEXC32_EL2, /* Floating-Point Exception Control Register */ 417 DBGVCR32_EL2, /* Debug Vector Catch Register */ 418 419 /* EL2 registers */ 420 SCTLR_EL2, /* System Control Register (EL2) */ 421 ACTLR_EL2, /* Auxiliary Control Register (EL2) */ 422 MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */ 423 CPTR_EL2, /* Architectural Feature Trap Register (EL2) */ 424 HACR_EL2, /* Hypervisor Auxiliary Control Register */ 425 TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */ 426 TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */ 427 TCR_EL2, /* Translation Control Register (EL2) */ 428 SPSR_EL2, /* EL2 saved program status register */ 429 ELR_EL2, /* EL2 exception link register */ 430 AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */ 431 AFSR1_EL2, /* Auxiliary Fault Status Register 1 (EL2) */ 432 ESR_EL2, /* Exception Syndrome Register (EL2) */ 433 FAR_EL2, /* Fault Address Register (EL2) */ 434 HPFAR_EL2, /* Hypervisor IPA Fault Address Register */ 435 MAIR_EL2, /* Memory Attribute Indirection Register (EL2) */ 436 AMAIR_EL2, /* Auxiliary Memory Attribute Indirection Register (EL2) */ 437 VBAR_EL2, /* Vector Base Address Register (EL2) */ 438 RVBAR_EL2, /* Reset Vector Base Address Register */ 439 CONTEXTIDR_EL2, /* Context ID Register (EL2) */ 440 CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */ 441 SP_EL2, /* EL2 Stack Pointer */ 442 CNTHP_CTL_EL2, 443 CNTHP_CVAL_EL2, 444 CNTHV_CTL_EL2, 445 CNTHV_CVAL_EL2, 446 447 __VNCR_START__, /* Any VNCR-capable reg goes after this point */ 448 449 VNCR(SCTLR_EL1),/* System Control Register */ 450 VNCR(ACTLR_EL1),/* Auxiliary Control Register */ 451 VNCR(CPACR_EL1),/* Coprocessor Access Control */ 452 VNCR(ZCR_EL1), /* SVE Control */ 453 VNCR(TTBR0_EL1),/* Translation Table Base Register 0 */ 454 VNCR(TTBR1_EL1),/* Translation Table Base Register 1 */ 455 VNCR(TCR_EL1), /* Translation Control Register */ 456 VNCR(TCR2_EL1), /* Extended Translation Control Register */ 457 VNCR(ESR_EL1), /* Exception Syndrome Register */ 458 VNCR(AFSR0_EL1),/* Auxiliary Fault Status Register 0 */ 459 VNCR(AFSR1_EL1),/* Auxiliary Fault Status Register 1 */ 460 VNCR(FAR_EL1), /* Fault Address Register */ 461 VNCR(MAIR_EL1), /* Memory Attribute Indirection Register */ 462 VNCR(VBAR_EL1), /* Vector Base Address Register */ 463 VNCR(CONTEXTIDR_EL1), /* Context ID Register */ 464 VNCR(AMAIR_EL1),/* Aux Memory Attribute Indirection Register */ 465 VNCR(MDSCR_EL1),/* Monitor Debug System Control Register */ 466 VNCR(ELR_EL1), 467 VNCR(SP_EL1), 468 VNCR(SPSR_EL1), 469 VNCR(TFSR_EL1), /* Tag Fault Status Register (EL1) */ 470 VNCR(VPIDR_EL2),/* Virtualization Processor ID Register */ 471 VNCR(VMPIDR_EL2),/* Virtualization Multiprocessor ID Register */ 472 VNCR(HCR_EL2), /* Hypervisor Configuration Register */ 473 VNCR(HSTR_EL2), /* Hypervisor System Trap Register */ 474 VNCR(VTTBR_EL2),/* Virtualization Translation Table Base Register */ 475 VNCR(VTCR_EL2), /* Virtualization Translation Control Register */ 476 VNCR(TPIDR_EL2),/* EL2 Software Thread ID Register */ 477 VNCR(HCRX_EL2), /* Extended Hypervisor Configuration Register */ 478 479 /* Permission Indirection Extension registers */ 480 VNCR(PIR_EL1), /* Permission Indirection Register 1 (EL1) */ 481 VNCR(PIRE0_EL1), /* Permission Indirection Register 0 (EL1) */ 482 483 VNCR(HFGRTR_EL2), 484 VNCR(HFGWTR_EL2), 485 VNCR(HFGITR_EL2), 486 VNCR(HDFGRTR_EL2), 487 VNCR(HDFGWTR_EL2), 488 VNCR(HAFGRTR_EL2), 489 490 VNCR(CNTVOFF_EL2), 491 VNCR(CNTV_CVAL_EL0), 492 VNCR(CNTV_CTL_EL0), 493 VNCR(CNTP_CVAL_EL0), 494 VNCR(CNTP_CTL_EL0), 495 496 NR_SYS_REGS /* Nothing after this line! */ 497 }; 498 499 struct kvm_sysreg_masks { 500 struct { 501 u64 res0; 502 u64 res1; 503 } mask[NR_SYS_REGS - __VNCR_START__]; 504 }; 505 506 struct kvm_cpu_context { 507 struct user_pt_regs regs; /* sp = sp_el0 */ 508 509 u64 spsr_abt; 510 u64 spsr_und; 511 u64 spsr_irq; 512 u64 spsr_fiq; 513 514 struct user_fpsimd_state fp_regs; 515 516 u64 sys_regs[NR_SYS_REGS]; 517 518 struct kvm_vcpu *__hyp_running_vcpu; 519 520 /* This pointer has to be 4kB aligned. */ 521 u64 *vncr_array; 522 }; 523 524 /* 525 * This structure is instantiated on a per-CPU basis, and contains 526 * data that is: 527 * 528 * - tied to a single physical CPU, and 529 * - either have a lifetime that does not extend past vcpu_put() 530 * - or is an invariant for the lifetime of the system 531 * 532 * Use host_data_ptr(field) as a way to access a pointer to such a 533 * field. 534 */ 535 struct kvm_host_data { 536 struct kvm_cpu_context host_ctxt; 537 struct user_fpsimd_state *fpsimd_state; /* hyp VA */ 538 539 /* Ownership of the FP regs */ 540 enum { 541 FP_STATE_FREE, 542 FP_STATE_HOST_OWNED, 543 FP_STATE_GUEST_OWNED, 544 } fp_owner; 545 546 /* 547 * host_debug_state contains the host registers which are 548 * saved and restored during world switches. 549 */ 550 struct { 551 /* {Break,watch}point registers */ 552 struct kvm_guest_debug_arch regs; 553 /* Statistical profiling extension */ 554 u64 pmscr_el1; 555 /* Self-hosted trace */ 556 u64 trfcr_el1; 557 /* Values of trap registers for the host before guest entry. */ 558 u64 mdcr_el2; 559 } host_debug_state; 560 }; 561 562 struct kvm_host_psci_config { 563 /* PSCI version used by host. */ 564 u32 version; 565 u32 smccc_version; 566 567 /* Function IDs used by host if version is v0.1. */ 568 struct psci_0_1_function_ids function_ids_0_1; 569 570 bool psci_0_1_cpu_suspend_implemented; 571 bool psci_0_1_cpu_on_implemented; 572 bool psci_0_1_cpu_off_implemented; 573 bool psci_0_1_migrate_implemented; 574 }; 575 576 extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config); 577 #define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config) 578 579 extern s64 kvm_nvhe_sym(hyp_physvirt_offset); 580 #define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset) 581 582 extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS]; 583 #define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map) 584 585 struct vcpu_reset_state { 586 unsigned long pc; 587 unsigned long r0; 588 bool be; 589 bool reset; 590 }; 591 592 struct kvm_vcpu_arch { 593 struct kvm_cpu_context ctxt; 594 595 /* 596 * Guest floating point state 597 * 598 * The architecture has two main floating point extensions, 599 * the original FPSIMD and SVE. These have overlapping 600 * register views, with the FPSIMD V registers occupying the 601 * low 128 bits of the SVE Z registers. When the core 602 * floating point code saves the register state of a task it 603 * records which view it saved in fp_type. 604 */ 605 void *sve_state; 606 enum fp_type fp_type; 607 unsigned int sve_max_vl; 608 u64 svcr; 609 u64 fpmr; 610 611 /* Stage 2 paging state used by the hardware on next switch */ 612 struct kvm_s2_mmu *hw_mmu; 613 614 /* Values of trap registers for the guest. */ 615 u64 hcr_el2; 616 u64 hcrx_el2; 617 u64 mdcr_el2; 618 u64 cptr_el2; 619 620 /* Exception Information */ 621 struct kvm_vcpu_fault_info fault; 622 623 /* Configuration flags, set once and for all before the vcpu can run */ 624 u8 cflags; 625 626 /* Input flags to the hypervisor code, potentially cleared after use */ 627 u8 iflags; 628 629 /* State flags for kernel bookkeeping, unused by the hypervisor code */ 630 u8 sflags; 631 632 /* 633 * Don't run the guest (internal implementation need). 634 * 635 * Contrary to the flags above, this is set/cleared outside of 636 * a vcpu context, and thus cannot be mixed with the flags 637 * themselves (or the flag accesses need to be made atomic). 638 */ 639 bool pause; 640 641 /* 642 * We maintain more than a single set of debug registers to support 643 * debugging the guest from the host and to maintain separate host and 644 * guest state during world switches. vcpu_debug_state are the debug 645 * registers of the vcpu as the guest sees them. 646 * 647 * external_debug_state contains the debug values we want to debug the 648 * guest. This is set via the KVM_SET_GUEST_DEBUG ioctl. 649 * 650 * debug_ptr points to the set of debug registers that should be loaded 651 * onto the hardware when running the guest. 652 */ 653 struct kvm_guest_debug_arch *debug_ptr; 654 struct kvm_guest_debug_arch vcpu_debug_state; 655 struct kvm_guest_debug_arch external_debug_state; 656 657 /* VGIC state */ 658 struct vgic_cpu vgic_cpu; 659 struct arch_timer_cpu timer_cpu; 660 struct kvm_pmu pmu; 661 662 /* 663 * Guest registers we preserve during guest debugging. 664 * 665 * These shadow registers are updated by the kvm_handle_sys_reg 666 * trap handler if the guest accesses or updates them while we 667 * are using guest debug. 668 */ 669 struct { 670 u32 mdscr_el1; 671 bool pstate_ss; 672 } guest_debug_preserved; 673 674 /* vcpu power state */ 675 struct kvm_mp_state mp_state; 676 spinlock_t mp_state_lock; 677 678 /* Cache some mmu pages needed inside spinlock regions */ 679 struct kvm_mmu_memory_cache mmu_page_cache; 680 681 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */ 682 u64 vsesr_el2; 683 684 /* Additional reset state */ 685 struct vcpu_reset_state reset_state; 686 687 /* Guest PV state */ 688 struct { 689 u64 last_steal; 690 gpa_t base; 691 } steal; 692 693 /* Per-vcpu CCSIDR override or NULL */ 694 u32 *ccsidr; 695 }; 696 697 /* 698 * Each 'flag' is composed of a comma-separated triplet: 699 * 700 * - the flag-set it belongs to in the vcpu->arch structure 701 * - the value for that flag 702 * - the mask for that flag 703 * 704 * __vcpu_single_flag() builds such a triplet for a single-bit flag. 705 * unpack_vcpu_flag() extract the flag value from the triplet for 706 * direct use outside of the flag accessors. 707 */ 708 #define __vcpu_single_flag(_set, _f) _set, (_f), (_f) 709 710 #define __unpack_flag(_set, _f, _m) _f 711 #define unpack_vcpu_flag(...) __unpack_flag(__VA_ARGS__) 712 713 #define __build_check_flag(v, flagset, f, m) \ 714 do { \ 715 typeof(v->arch.flagset) *_fset; \ 716 \ 717 /* Check that the flags fit in the mask */ \ 718 BUILD_BUG_ON(HWEIGHT(m) != HWEIGHT((f) | (m))); \ 719 /* Check that the flags fit in the type */ \ 720 BUILD_BUG_ON((sizeof(*_fset) * 8) <= __fls(m)); \ 721 } while (0) 722 723 #define __vcpu_get_flag(v, flagset, f, m) \ 724 ({ \ 725 __build_check_flag(v, flagset, f, m); \ 726 \ 727 READ_ONCE(v->arch.flagset) & (m); \ 728 }) 729 730 /* 731 * Note that the set/clear accessors must be preempt-safe in order to 732 * avoid nesting them with load/put which also manipulate flags... 733 */ 734 #ifdef __KVM_NVHE_HYPERVISOR__ 735 /* the nVHE hypervisor is always non-preemptible */ 736 #define __vcpu_flags_preempt_disable() 737 #define __vcpu_flags_preempt_enable() 738 #else 739 #define __vcpu_flags_preempt_disable() preempt_disable() 740 #define __vcpu_flags_preempt_enable() preempt_enable() 741 #endif 742 743 #define __vcpu_set_flag(v, flagset, f, m) \ 744 do { \ 745 typeof(v->arch.flagset) *fset; \ 746 \ 747 __build_check_flag(v, flagset, f, m); \ 748 \ 749 fset = &v->arch.flagset; \ 750 __vcpu_flags_preempt_disable(); \ 751 if (HWEIGHT(m) > 1) \ 752 *fset &= ~(m); \ 753 *fset |= (f); \ 754 __vcpu_flags_preempt_enable(); \ 755 } while (0) 756 757 #define __vcpu_clear_flag(v, flagset, f, m) \ 758 do { \ 759 typeof(v->arch.flagset) *fset; \ 760 \ 761 __build_check_flag(v, flagset, f, m); \ 762 \ 763 fset = &v->arch.flagset; \ 764 __vcpu_flags_preempt_disable(); \ 765 *fset &= ~(m); \ 766 __vcpu_flags_preempt_enable(); \ 767 } while (0) 768 769 #define vcpu_get_flag(v, ...) __vcpu_get_flag((v), __VA_ARGS__) 770 #define vcpu_set_flag(v, ...) __vcpu_set_flag((v), __VA_ARGS__) 771 #define vcpu_clear_flag(v, ...) __vcpu_clear_flag((v), __VA_ARGS__) 772 773 /* SVE exposed to guest */ 774 #define GUEST_HAS_SVE __vcpu_single_flag(cflags, BIT(0)) 775 /* SVE config completed */ 776 #define VCPU_SVE_FINALIZED __vcpu_single_flag(cflags, BIT(1)) 777 /* PTRAUTH exposed to guest */ 778 #define GUEST_HAS_PTRAUTH __vcpu_single_flag(cflags, BIT(2)) 779 /* KVM_ARM_VCPU_INIT completed */ 780 #define VCPU_INITIALIZED __vcpu_single_flag(cflags, BIT(3)) 781 782 /* Exception pending */ 783 #define PENDING_EXCEPTION __vcpu_single_flag(iflags, BIT(0)) 784 /* 785 * PC increment. Overlaps with EXCEPT_MASK on purpose so that it can't 786 * be set together with an exception... 787 */ 788 #define INCREMENT_PC __vcpu_single_flag(iflags, BIT(1)) 789 /* Target EL/MODE (not a single flag, but let's abuse the macro) */ 790 #define EXCEPT_MASK __vcpu_single_flag(iflags, GENMASK(3, 1)) 791 792 /* Helpers to encode exceptions with minimum fuss */ 793 #define __EXCEPT_MASK_VAL unpack_vcpu_flag(EXCEPT_MASK) 794 #define __EXCEPT_SHIFT __builtin_ctzl(__EXCEPT_MASK_VAL) 795 #define __vcpu_except_flags(_f) iflags, (_f << __EXCEPT_SHIFT), __EXCEPT_MASK_VAL 796 797 /* 798 * When PENDING_EXCEPTION is set, EXCEPT_MASK can take the following 799 * values: 800 * 801 * For AArch32 EL1: 802 */ 803 #define EXCEPT_AA32_UND __vcpu_except_flags(0) 804 #define EXCEPT_AA32_IABT __vcpu_except_flags(1) 805 #define EXCEPT_AA32_DABT __vcpu_except_flags(2) 806 /* For AArch64: */ 807 #define EXCEPT_AA64_EL1_SYNC __vcpu_except_flags(0) 808 #define EXCEPT_AA64_EL1_IRQ __vcpu_except_flags(1) 809 #define EXCEPT_AA64_EL1_FIQ __vcpu_except_flags(2) 810 #define EXCEPT_AA64_EL1_SERR __vcpu_except_flags(3) 811 /* For AArch64 with NV: */ 812 #define EXCEPT_AA64_EL2_SYNC __vcpu_except_flags(4) 813 #define EXCEPT_AA64_EL2_IRQ __vcpu_except_flags(5) 814 #define EXCEPT_AA64_EL2_FIQ __vcpu_except_flags(6) 815 #define EXCEPT_AA64_EL2_SERR __vcpu_except_flags(7) 816 /* Guest debug is live */ 817 #define DEBUG_DIRTY __vcpu_single_flag(iflags, BIT(4)) 818 /* Save SPE context if active */ 819 #define DEBUG_STATE_SAVE_SPE __vcpu_single_flag(iflags, BIT(5)) 820 /* Save TRBE context if active */ 821 #define DEBUG_STATE_SAVE_TRBE __vcpu_single_flag(iflags, BIT(6)) 822 823 /* SVE enabled for host EL0 */ 824 #define HOST_SVE_ENABLED __vcpu_single_flag(sflags, BIT(0)) 825 /* SME enabled for EL0 */ 826 #define HOST_SME_ENABLED __vcpu_single_flag(sflags, BIT(1)) 827 /* Physical CPU not in supported_cpus */ 828 #define ON_UNSUPPORTED_CPU __vcpu_single_flag(sflags, BIT(2)) 829 /* WFIT instruction trapped */ 830 #define IN_WFIT __vcpu_single_flag(sflags, BIT(3)) 831 /* vcpu system registers loaded on physical CPU */ 832 #define SYSREGS_ON_CPU __vcpu_single_flag(sflags, BIT(4)) 833 /* Software step state is Active-pending */ 834 #define DBG_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(5)) 835 /* PMUSERENR for the guest EL0 is on physical CPU */ 836 #define PMUSERENR_ON_CPU __vcpu_single_flag(sflags, BIT(6)) 837 /* WFI instruction trapped */ 838 #define IN_WFI __vcpu_single_flag(sflags, BIT(7)) 839 840 841 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */ 842 #define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) + \ 843 sve_ffr_offset((vcpu)->arch.sve_max_vl)) 844 845 #define vcpu_sve_max_vq(vcpu) sve_vq_from_vl((vcpu)->arch.sve_max_vl) 846 847 #define vcpu_sve_state_size(vcpu) ({ \ 848 size_t __size_ret; \ 849 unsigned int __vcpu_vq; \ 850 \ 851 if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) { \ 852 __size_ret = 0; \ 853 } else { \ 854 __vcpu_vq = vcpu_sve_max_vq(vcpu); \ 855 __size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq); \ 856 } \ 857 \ 858 __size_ret; \ 859 }) 860 861 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \ 862 KVM_GUESTDBG_USE_SW_BP | \ 863 KVM_GUESTDBG_USE_HW | \ 864 KVM_GUESTDBG_SINGLESTEP) 865 866 #define vcpu_has_sve(vcpu) (system_supports_sve() && \ 867 vcpu_get_flag(vcpu, GUEST_HAS_SVE)) 868 869 #ifdef CONFIG_ARM64_PTR_AUTH 870 #define vcpu_has_ptrauth(vcpu) \ 871 ((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) || \ 872 cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) && \ 873 vcpu_get_flag(vcpu, GUEST_HAS_PTRAUTH)) 874 #else 875 #define vcpu_has_ptrauth(vcpu) false 876 #endif 877 878 #define vcpu_on_unsupported_cpu(vcpu) \ 879 vcpu_get_flag(vcpu, ON_UNSUPPORTED_CPU) 880 881 #define vcpu_set_on_unsupported_cpu(vcpu) \ 882 vcpu_set_flag(vcpu, ON_UNSUPPORTED_CPU) 883 884 #define vcpu_clear_on_unsupported_cpu(vcpu) \ 885 vcpu_clear_flag(vcpu, ON_UNSUPPORTED_CPU) 886 887 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.regs) 888 889 /* 890 * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the 891 * memory backed version of a register, and not the one most recently 892 * accessed by a running VCPU. For example, for userspace access or 893 * for system registers that are never context switched, but only 894 * emulated. 895 * 896 * Don't bother with VNCR-based accesses in the nVHE code, it has no 897 * business dealing with NV. 898 */ 899 static inline u64 *___ctxt_sys_reg(const struct kvm_cpu_context *ctxt, int r) 900 { 901 #if !defined (__KVM_NVHE_HYPERVISOR__) 902 if (unlikely(cpus_have_final_cap(ARM64_HAS_NESTED_VIRT) && 903 r >= __VNCR_START__ && ctxt->vncr_array)) 904 return &ctxt->vncr_array[r - __VNCR_START__]; 905 #endif 906 return (u64 *)&ctxt->sys_regs[r]; 907 } 908 909 #define __ctxt_sys_reg(c,r) \ 910 ({ \ 911 BUILD_BUG_ON(__builtin_constant_p(r) && \ 912 (r) >= NR_SYS_REGS); \ 913 ___ctxt_sys_reg(c, r); \ 914 }) 915 916 #define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r)) 917 918 u64 kvm_vcpu_sanitise_vncr_reg(const struct kvm_vcpu *, enum vcpu_sysreg); 919 #define __vcpu_sys_reg(v,r) \ 920 (*({ \ 921 const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \ 922 u64 *__r = __ctxt_sys_reg(ctxt, (r)); \ 923 if (vcpu_has_nv((v)) && (r) >= __VNCR_START__) \ 924 *__r = kvm_vcpu_sanitise_vncr_reg((v), (r)); \ 925 __r; \ 926 })) 927 928 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg); 929 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg); 930 931 static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val) 932 { 933 /* 934 * *** VHE ONLY *** 935 * 936 * System registers listed in the switch are not saved on every 937 * exit from the guest but are only saved on vcpu_put. 938 * 939 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but 940 * should never be listed below, because the guest cannot modify its 941 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's 942 * thread when emulating cross-VCPU communication. 943 */ 944 if (!has_vhe()) 945 return false; 946 947 switch (reg) { 948 case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break; 949 case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break; 950 case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break; 951 case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break; 952 case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break; 953 case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break; 954 case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break; 955 case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break; 956 case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break; 957 case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break; 958 case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break; 959 case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break; 960 case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break; 961 case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break; 962 case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break; 963 case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break; 964 case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break; 965 case ELR_EL1: *val = read_sysreg_s(SYS_ELR_EL12); break; 966 case SPSR_EL1: *val = read_sysreg_s(SYS_SPSR_EL12); break; 967 case PAR_EL1: *val = read_sysreg_par(); break; 968 case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break; 969 case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break; 970 case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break; 971 default: return false; 972 } 973 974 return true; 975 } 976 977 static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg) 978 { 979 /* 980 * *** VHE ONLY *** 981 * 982 * System registers listed in the switch are not restored on every 983 * entry to the guest but are only restored on vcpu_load. 984 * 985 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but 986 * should never be listed below, because the MPIDR should only be set 987 * once, before running the VCPU, and never changed later. 988 */ 989 if (!has_vhe()) 990 return false; 991 992 switch (reg) { 993 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break; 994 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break; 995 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break; 996 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break; 997 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break; 998 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break; 999 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break; 1000 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break; 1001 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break; 1002 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break; 1003 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break; 1004 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break; 1005 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break; 1006 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break; 1007 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break; 1008 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break; 1009 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break; 1010 case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break; 1011 case SPSR_EL1: write_sysreg_s(val, SYS_SPSR_EL12); break; 1012 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break; 1013 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break; 1014 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break; 1015 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break; 1016 default: return false; 1017 } 1018 1019 return true; 1020 } 1021 1022 struct kvm_vm_stat { 1023 struct kvm_vm_stat_generic generic; 1024 }; 1025 1026 struct kvm_vcpu_stat { 1027 struct kvm_vcpu_stat_generic generic; 1028 u64 hvc_exit_stat; 1029 u64 wfe_exit_stat; 1030 u64 wfi_exit_stat; 1031 u64 mmio_exit_user; 1032 u64 mmio_exit_kernel; 1033 u64 signal_exits; 1034 u64 exits; 1035 }; 1036 1037 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); 1038 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); 1039 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 1040 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 1041 1042 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu); 1043 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices); 1044 1045 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu, 1046 struct kvm_vcpu_events *events); 1047 1048 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu, 1049 struct kvm_vcpu_events *events); 1050 1051 void kvm_arm_halt_guest(struct kvm *kvm); 1052 void kvm_arm_resume_guest(struct kvm *kvm); 1053 1054 #define vcpu_has_run_once(vcpu) !!rcu_access_pointer((vcpu)->pid) 1055 1056 #ifndef __KVM_NVHE_HYPERVISOR__ 1057 #define kvm_call_hyp_nvhe(f, ...) \ 1058 ({ \ 1059 struct arm_smccc_res res; \ 1060 \ 1061 arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f), \ 1062 ##__VA_ARGS__, &res); \ 1063 WARN_ON(res.a0 != SMCCC_RET_SUCCESS); \ 1064 \ 1065 res.a1; \ 1066 }) 1067 1068 /* 1069 * The couple of isb() below are there to guarantee the same behaviour 1070 * on VHE as on !VHE, where the eret to EL1 acts as a context 1071 * synchronization event. 1072 */ 1073 #define kvm_call_hyp(f, ...) \ 1074 do { \ 1075 if (has_vhe()) { \ 1076 f(__VA_ARGS__); \ 1077 isb(); \ 1078 } else { \ 1079 kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 1080 } \ 1081 } while(0) 1082 1083 #define kvm_call_hyp_ret(f, ...) \ 1084 ({ \ 1085 typeof(f(__VA_ARGS__)) ret; \ 1086 \ 1087 if (has_vhe()) { \ 1088 ret = f(__VA_ARGS__); \ 1089 isb(); \ 1090 } else { \ 1091 ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 1092 } \ 1093 \ 1094 ret; \ 1095 }) 1096 #else /* __KVM_NVHE_HYPERVISOR__ */ 1097 #define kvm_call_hyp(f, ...) f(__VA_ARGS__) 1098 #define kvm_call_hyp_ret(f, ...) f(__VA_ARGS__) 1099 #define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__) 1100 #endif /* __KVM_NVHE_HYPERVISOR__ */ 1101 1102 int handle_exit(struct kvm_vcpu *vcpu, int exception_index); 1103 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index); 1104 1105 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu); 1106 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu); 1107 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu); 1108 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu); 1109 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu); 1110 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu); 1111 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu); 1112 1113 void kvm_sys_regs_create_debugfs(struct kvm *kvm); 1114 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu); 1115 1116 int __init kvm_sys_reg_table_init(void); 1117 struct sys_reg_desc; 1118 int __init populate_sysreg_config(const struct sys_reg_desc *sr, 1119 unsigned int idx); 1120 int __init populate_nv_trap_config(void); 1121 1122 bool lock_all_vcpus(struct kvm *kvm); 1123 void unlock_all_vcpus(struct kvm *kvm); 1124 1125 void kvm_init_sysreg(struct kvm_vcpu *); 1126 1127 /* MMIO helpers */ 1128 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data); 1129 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len); 1130 1131 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu); 1132 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa); 1133 1134 /* 1135 * Returns true if a Performance Monitoring Interrupt (PMI), a.k.a. perf event, 1136 * arrived in guest context. For arm64, any event that arrives while a vCPU is 1137 * loaded is considered to be "in guest". 1138 */ 1139 static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu) 1140 { 1141 return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu; 1142 } 1143 1144 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu); 1145 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu); 1146 void kvm_update_stolen_time(struct kvm_vcpu *vcpu); 1147 1148 bool kvm_arm_pvtime_supported(void); 1149 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu, 1150 struct kvm_device_attr *attr); 1151 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu, 1152 struct kvm_device_attr *attr); 1153 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu, 1154 struct kvm_device_attr *attr); 1155 1156 extern unsigned int __ro_after_init kvm_arm_vmid_bits; 1157 int __init kvm_arm_vmid_alloc_init(void); 1158 void __init kvm_arm_vmid_alloc_free(void); 1159 bool kvm_arm_vmid_update(struct kvm_vmid *kvm_vmid); 1160 void kvm_arm_vmid_clear_active(void); 1161 1162 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch) 1163 { 1164 vcpu_arch->steal.base = INVALID_GPA; 1165 } 1166 1167 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch) 1168 { 1169 return (vcpu_arch->steal.base != INVALID_GPA); 1170 } 1171 1172 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome); 1173 1174 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); 1175 1176 DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data); 1177 1178 /* 1179 * How we access per-CPU host data depends on the where we access it from, 1180 * and the mode we're in: 1181 * 1182 * - VHE and nVHE hypervisor bits use their locally defined instance 1183 * 1184 * - the rest of the kernel use either the VHE or nVHE one, depending on 1185 * the mode we're running in. 1186 * 1187 * Unless we're in protected mode, fully deprivileged, and the nVHE 1188 * per-CPU stuff is exclusively accessible to the protected EL2 code. 1189 * In this case, the EL1 code uses the *VHE* data as its private state 1190 * (which makes sense in a way as there shouldn't be any shared state 1191 * between the host and the hypervisor). 1192 * 1193 * Yes, this is all totally trivial. Shoot me now. 1194 */ 1195 #if defined(__KVM_NVHE_HYPERVISOR__) || defined(__KVM_VHE_HYPERVISOR__) 1196 #define host_data_ptr(f) (&this_cpu_ptr(&kvm_host_data)->f) 1197 #else 1198 #define host_data_ptr(f) \ 1199 (static_branch_unlikely(&kvm_protected_mode_initialized) ? \ 1200 &this_cpu_ptr(&kvm_host_data)->f : \ 1201 &this_cpu_ptr_hyp_sym(kvm_host_data)->f) 1202 #endif 1203 1204 /* Check whether the FP regs are owned by the guest */ 1205 static inline bool guest_owns_fp_regs(void) 1206 { 1207 return *host_data_ptr(fp_owner) == FP_STATE_GUEST_OWNED; 1208 } 1209 1210 /* Check whether the FP regs are owned by the host */ 1211 static inline bool host_owns_fp_regs(void) 1212 { 1213 return *host_data_ptr(fp_owner) == FP_STATE_HOST_OWNED; 1214 } 1215 1216 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt) 1217 { 1218 /* The host's MPIDR is immutable, so let's set it up at boot time */ 1219 ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr(); 1220 } 1221 1222 static inline bool kvm_system_needs_idmapped_vectors(void) 1223 { 1224 return cpus_have_final_cap(ARM64_SPECTRE_V3A); 1225 } 1226 1227 static inline void kvm_arch_sync_events(struct kvm *kvm) {} 1228 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {} 1229 1230 void kvm_arm_init_debug(void); 1231 void kvm_arm_vcpu_init_debug(struct kvm_vcpu *vcpu); 1232 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu); 1233 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu); 1234 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu); 1235 1236 #define kvm_vcpu_os_lock_enabled(vcpu) \ 1237 (!!(__vcpu_sys_reg(vcpu, OSLSR_EL1) & OSLSR_EL1_OSLK)) 1238 1239 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, 1240 struct kvm_device_attr *attr); 1241 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, 1242 struct kvm_device_attr *attr); 1243 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, 1244 struct kvm_device_attr *attr); 1245 1246 int kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm, 1247 struct kvm_arm_copy_mte_tags *copy_tags); 1248 int kvm_vm_ioctl_set_counter_offset(struct kvm *kvm, 1249 struct kvm_arm_counter_offset *offset); 1250 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, 1251 struct reg_mask_range *range); 1252 1253 /* Guest/host FPSIMD coordination helpers */ 1254 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu); 1255 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu); 1256 void kvm_arch_vcpu_ctxflush_fp(struct kvm_vcpu *vcpu); 1257 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu); 1258 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu); 1259 1260 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr) 1261 { 1262 return (!has_vhe() && attr->exclude_host); 1263 } 1264 1265 /* Flags for host debug state */ 1266 void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu); 1267 void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu); 1268 1269 #ifdef CONFIG_KVM 1270 void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr); 1271 void kvm_clr_pmu_events(u32 clr); 1272 bool kvm_set_pmuserenr(u64 val); 1273 #else 1274 static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {} 1275 static inline void kvm_clr_pmu_events(u32 clr) {} 1276 static inline bool kvm_set_pmuserenr(u64 val) 1277 { 1278 return false; 1279 } 1280 #endif 1281 1282 void kvm_vcpu_load_vhe(struct kvm_vcpu *vcpu); 1283 void kvm_vcpu_put_vhe(struct kvm_vcpu *vcpu); 1284 1285 int __init kvm_set_ipa_limit(void); 1286 1287 #define __KVM_HAVE_ARCH_VM_ALLOC 1288 struct kvm *kvm_arch_alloc_vm(void); 1289 1290 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS 1291 1292 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS_RANGE 1293 1294 #define kvm_vm_is_protected(kvm) (is_protected_kvm_enabled() && (kvm)->arch.pkvm.enabled) 1295 1296 #define vcpu_is_protected(vcpu) kvm_vm_is_protected((vcpu)->kvm) 1297 1298 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature); 1299 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu); 1300 1301 #define kvm_arm_vcpu_sve_finalized(vcpu) vcpu_get_flag(vcpu, VCPU_SVE_FINALIZED) 1302 1303 #define kvm_has_mte(kvm) \ 1304 (system_supports_mte() && \ 1305 test_bit(KVM_ARCH_FLAG_MTE_ENABLED, &(kvm)->arch.flags)) 1306 1307 #define kvm_supports_32bit_el0() \ 1308 (system_supports_32bit_el0() && \ 1309 !static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1310 1311 #define kvm_vm_has_ran_once(kvm) \ 1312 (test_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &(kvm)->arch.flags)) 1313 1314 static inline bool __vcpu_has_feature(const struct kvm_arch *ka, int feature) 1315 { 1316 return test_bit(feature, ka->vcpu_features); 1317 } 1318 1319 #define vcpu_has_feature(v, f) __vcpu_has_feature(&(v)->kvm->arch, (f)) 1320 1321 #define kvm_vcpu_initialized(v) vcpu_get_flag(vcpu, VCPU_INITIALIZED) 1322 1323 int kvm_trng_call(struct kvm_vcpu *vcpu); 1324 #ifdef CONFIG_KVM 1325 extern phys_addr_t hyp_mem_base; 1326 extern phys_addr_t hyp_mem_size; 1327 void __init kvm_hyp_reserve(void); 1328 #else 1329 static inline void kvm_hyp_reserve(void) { } 1330 #endif 1331 1332 void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu); 1333 bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu); 1334 1335 #define __expand_field_sign_unsigned(id, fld, val) \ 1336 ((u64)SYS_FIELD_VALUE(id, fld, val)) 1337 1338 #define __expand_field_sign_signed(id, fld, val) \ 1339 ({ \ 1340 u64 __val = SYS_FIELD_VALUE(id, fld, val); \ 1341 sign_extend64(__val, id##_##fld##_WIDTH - 1); \ 1342 }) 1343 1344 #define expand_field_sign(id, fld, val) \ 1345 (id##_##fld##_SIGNED ? \ 1346 __expand_field_sign_signed(id, fld, val) : \ 1347 __expand_field_sign_unsigned(id, fld, val)) 1348 1349 #define get_idreg_field_unsigned(kvm, id, fld) \ 1350 ({ \ 1351 u64 __val = IDREG((kvm), SYS_##id); \ 1352 FIELD_GET(id##_##fld##_MASK, __val); \ 1353 }) 1354 1355 #define get_idreg_field_signed(kvm, id, fld) \ 1356 ({ \ 1357 u64 __val = get_idreg_field_unsigned(kvm, id, fld); \ 1358 sign_extend64(__val, id##_##fld##_WIDTH - 1); \ 1359 }) 1360 1361 #define get_idreg_field_enum(kvm, id, fld) \ 1362 get_idreg_field_unsigned(kvm, id, fld) 1363 1364 #define get_idreg_field(kvm, id, fld) \ 1365 (id##_##fld##_SIGNED ? \ 1366 get_idreg_field_signed(kvm, id, fld) : \ 1367 get_idreg_field_unsigned(kvm, id, fld)) 1368 1369 #define kvm_has_feat(kvm, id, fld, limit) \ 1370 (get_idreg_field((kvm), id, fld) >= expand_field_sign(id, fld, limit)) 1371 1372 #define kvm_has_feat_enum(kvm, id, fld, val) \ 1373 (get_idreg_field_unsigned((kvm), id, fld) == __expand_field_sign_unsigned(id, fld, val)) 1374 1375 #define kvm_has_feat_range(kvm, id, fld, min, max) \ 1376 (get_idreg_field((kvm), id, fld) >= expand_field_sign(id, fld, min) && \ 1377 get_idreg_field((kvm), id, fld) <= expand_field_sign(id, fld, max)) 1378 1379 /* Check for a given level of PAuth support */ 1380 #define kvm_has_pauth(k, l) \ 1381 ({ \ 1382 bool pa, pi, pa3; \ 1383 \ 1384 pa = kvm_has_feat((k), ID_AA64ISAR1_EL1, APA, l); \ 1385 pa &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPA, IMP); \ 1386 pi = kvm_has_feat((k), ID_AA64ISAR1_EL1, API, l); \ 1387 pi &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPI, IMP); \ 1388 pa3 = kvm_has_feat((k), ID_AA64ISAR2_EL1, APA3, l); \ 1389 pa3 &= kvm_has_feat((k), ID_AA64ISAR2_EL1, GPA3, IMP); \ 1390 \ 1391 (pa + pi + pa3) == 1; \ 1392 }) 1393 1394 #endif /* __ARM64_KVM_HOST_H__ */ 1395