1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/asm/kvm_host.h: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 */ 10 11 #ifndef __ARM64_KVM_HOST_H__ 12 #define __ARM64_KVM_HOST_H__ 13 14 #include <linux/arm-smccc.h> 15 #include <linux/bitmap.h> 16 #include <linux/types.h> 17 #include <linux/jump_label.h> 18 #include <linux/kvm_types.h> 19 #include <linux/maple_tree.h> 20 #include <linux/percpu.h> 21 #include <linux/psci.h> 22 #include <asm/arch_gicv3.h> 23 #include <asm/barrier.h> 24 #include <asm/cpufeature.h> 25 #include <asm/cputype.h> 26 #include <asm/daifflags.h> 27 #include <asm/fpsimd.h> 28 #include <asm/kvm.h> 29 #include <asm/kvm_asm.h> 30 #include <asm/vncr_mapping.h> 31 32 #define __KVM_HAVE_ARCH_INTC_INITIALIZED 33 34 #define KVM_HALT_POLL_NS_DEFAULT 500000 35 36 #include <kvm/arm_vgic.h> 37 #include <kvm/arm_arch_timer.h> 38 #include <kvm/arm_pmu.h> 39 40 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS 41 42 #define KVM_VCPU_MAX_FEATURES 9 43 #define KVM_VCPU_VALID_FEATURES (BIT(KVM_VCPU_MAX_FEATURES) - 1) 44 45 #define KVM_REQ_SLEEP \ 46 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 47 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1) 48 #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2) 49 #define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(3) 50 #define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4) 51 #define KVM_REQ_RELOAD_PMU KVM_ARCH_REQ(5) 52 #define KVM_REQ_SUSPEND KVM_ARCH_REQ(6) 53 #define KVM_REQ_RESYNC_PMU_EL0 KVM_ARCH_REQ(7) 54 #define KVM_REQ_NESTED_S2_UNMAP KVM_ARCH_REQ(8) 55 #define KVM_REQ_GUEST_HYP_IRQ_PENDING KVM_ARCH_REQ(9) 56 #define KVM_REQ_MAP_L1_VNCR_EL2 KVM_ARCH_REQ(10) 57 58 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \ 59 KVM_DIRTY_LOG_INITIALLY_SET) 60 61 #define KVM_HAVE_MMU_RWLOCK 62 63 /* 64 * Mode of operation configurable with kvm-arm.mode early param. 65 * See Documentation/admin-guide/kernel-parameters.txt for more information. 66 */ 67 enum kvm_mode { 68 KVM_MODE_DEFAULT, 69 KVM_MODE_PROTECTED, 70 KVM_MODE_NV, 71 KVM_MODE_NONE, 72 }; 73 #ifdef CONFIG_KVM 74 enum kvm_mode kvm_get_mode(void); 75 #else 76 static inline enum kvm_mode kvm_get_mode(void) { return KVM_MODE_NONE; }; 77 #endif 78 79 extern unsigned int __ro_after_init kvm_sve_max_vl; 80 extern unsigned int __ro_after_init kvm_host_sve_max_vl; 81 int __init kvm_arm_init_sve(void); 82 83 u32 __attribute_const__ kvm_target_cpu(void); 84 void kvm_reset_vcpu(struct kvm_vcpu *vcpu); 85 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu); 86 87 struct kvm_hyp_memcache { 88 phys_addr_t head; 89 unsigned long nr_pages; 90 struct pkvm_mapping *mapping; /* only used from EL1 */ 91 92 #define HYP_MEMCACHE_ACCOUNT_STAGE2 BIT(1) 93 unsigned long flags; 94 }; 95 96 static inline void push_hyp_memcache(struct kvm_hyp_memcache *mc, 97 phys_addr_t *p, 98 phys_addr_t (*to_pa)(void *virt)) 99 { 100 *p = mc->head; 101 mc->head = to_pa(p); 102 mc->nr_pages++; 103 } 104 105 static inline void *pop_hyp_memcache(struct kvm_hyp_memcache *mc, 106 void *(*to_va)(phys_addr_t phys)) 107 { 108 phys_addr_t *p = to_va(mc->head & PAGE_MASK); 109 110 if (!mc->nr_pages) 111 return NULL; 112 113 mc->head = *p; 114 mc->nr_pages--; 115 116 return p; 117 } 118 119 static inline int __topup_hyp_memcache(struct kvm_hyp_memcache *mc, 120 unsigned long min_pages, 121 void *(*alloc_fn)(void *arg), 122 phys_addr_t (*to_pa)(void *virt), 123 void *arg) 124 { 125 while (mc->nr_pages < min_pages) { 126 phys_addr_t *p = alloc_fn(arg); 127 128 if (!p) 129 return -ENOMEM; 130 push_hyp_memcache(mc, p, to_pa); 131 } 132 133 return 0; 134 } 135 136 static inline void __free_hyp_memcache(struct kvm_hyp_memcache *mc, 137 void (*free_fn)(void *virt, void *arg), 138 void *(*to_va)(phys_addr_t phys), 139 void *arg) 140 { 141 while (mc->nr_pages) 142 free_fn(pop_hyp_memcache(mc, to_va), arg); 143 } 144 145 void free_hyp_memcache(struct kvm_hyp_memcache *mc); 146 int topup_hyp_memcache(struct kvm_hyp_memcache *mc, unsigned long min_pages); 147 148 struct kvm_vmid { 149 atomic64_t id; 150 }; 151 152 struct kvm_s2_mmu { 153 struct kvm_vmid vmid; 154 155 /* 156 * stage2 entry level table 157 * 158 * Two kvm_s2_mmu structures in the same VM can point to the same 159 * pgd here. This happens when running a guest using a 160 * translation regime that isn't affected by its own stage-2 161 * translation, such as a non-VHE hypervisor running at vEL2, or 162 * for vEL1/EL0 with vHCR_EL2.VM == 0. In that case, we use the 163 * canonical stage-2 page tables. 164 */ 165 phys_addr_t pgd_phys; 166 struct kvm_pgtable *pgt; 167 168 /* 169 * VTCR value used on the host. For a non-NV guest (or a NV 170 * guest that runs in a context where its own S2 doesn't 171 * apply), its T0SZ value reflects that of the IPA size. 172 * 173 * For a shadow S2 MMU, T0SZ reflects the PARange exposed to 174 * the guest. 175 */ 176 u64 vtcr; 177 178 /* The last vcpu id that ran on each physical CPU */ 179 int __percpu *last_vcpu_ran; 180 181 #define KVM_ARM_EAGER_SPLIT_CHUNK_SIZE_DEFAULT 0 182 /* 183 * Memory cache used to split 184 * KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE worth of huge pages. It 185 * is used to allocate stage2 page tables while splitting huge 186 * pages. The choice of KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE 187 * influences both the capacity of the split page cache, and 188 * how often KVM reschedules. Be wary of raising CHUNK_SIZE 189 * too high. 190 * 191 * Protected by kvm->slots_lock. 192 */ 193 struct kvm_mmu_memory_cache split_page_cache; 194 uint64_t split_page_chunk_size; 195 196 struct kvm_arch *arch; 197 198 /* 199 * For a shadow stage-2 MMU, the virtual vttbr used by the 200 * host to parse the guest S2. 201 * This either contains: 202 * - the virtual VTTBR programmed by the guest hypervisor with 203 * CnP cleared 204 * - The value 1 (VMID=0, BADDR=0, CnP=1) if invalid 205 * 206 * We also cache the full VTCR which gets used for TLB invalidation, 207 * taking the ARM ARM's "Any of the bits in VTCR_EL2 are permitted 208 * to be cached in a TLB" to the letter. 209 */ 210 u64 tlb_vttbr; 211 u64 tlb_vtcr; 212 213 /* 214 * true when this represents a nested context where virtual 215 * HCR_EL2.VM == 1 216 */ 217 bool nested_stage2_enabled; 218 219 /* 220 * true when this MMU needs to be unmapped before being used for a new 221 * purpose. 222 */ 223 bool pending_unmap; 224 225 /* 226 * 0: Nobody is currently using this, check vttbr for validity 227 * >0: Somebody is actively using this. 228 */ 229 atomic_t refcnt; 230 }; 231 232 struct kvm_arch_memory_slot { 233 }; 234 235 /** 236 * struct kvm_smccc_features: Descriptor of the hypercall services exposed to the guests 237 * 238 * @std_bmap: Bitmap of standard secure service calls 239 * @std_hyp_bmap: Bitmap of standard hypervisor service calls 240 * @vendor_hyp_bmap: Bitmap of vendor specific hypervisor service calls 241 */ 242 struct kvm_smccc_features { 243 unsigned long std_bmap; 244 unsigned long std_hyp_bmap; 245 unsigned long vendor_hyp_bmap; /* Function numbers 0-63 */ 246 unsigned long vendor_hyp_bmap_2; /* Function numbers 64-127 */ 247 }; 248 249 typedef unsigned int pkvm_handle_t; 250 251 struct kvm_protected_vm { 252 pkvm_handle_t handle; 253 struct kvm_hyp_memcache teardown_mc; 254 struct kvm_hyp_memcache stage2_teardown_mc; 255 bool enabled; 256 }; 257 258 struct kvm_mpidr_data { 259 u64 mpidr_mask; 260 DECLARE_FLEX_ARRAY(u16, cmpidr_to_idx); 261 }; 262 263 static inline u16 kvm_mpidr_index(struct kvm_mpidr_data *data, u64 mpidr) 264 { 265 unsigned long index = 0, mask = data->mpidr_mask; 266 unsigned long aff = mpidr & MPIDR_HWID_BITMASK; 267 268 bitmap_gather(&index, &aff, &mask, fls(mask)); 269 270 return index; 271 } 272 273 struct kvm_sysreg_masks; 274 275 enum fgt_group_id { 276 __NO_FGT_GROUP__, 277 HFGRTR_GROUP, 278 HFGWTR_GROUP = HFGRTR_GROUP, 279 HDFGRTR_GROUP, 280 HDFGWTR_GROUP = HDFGRTR_GROUP, 281 HFGITR_GROUP, 282 HAFGRTR_GROUP, 283 HFGRTR2_GROUP, 284 HFGWTR2_GROUP = HFGRTR2_GROUP, 285 HDFGRTR2_GROUP, 286 HDFGWTR2_GROUP = HDFGRTR2_GROUP, 287 HFGITR2_GROUP, 288 289 /* Must be last */ 290 __NR_FGT_GROUP_IDS__ 291 }; 292 293 struct kvm_arch { 294 struct kvm_s2_mmu mmu; 295 296 /* 297 * Fine-Grained UNDEF, mimicking the FGT layout defined by the 298 * architecture. We track them globally, as we present the 299 * same feature-set to all vcpus. 300 * 301 * Index 0 is currently spare. 302 */ 303 u64 fgu[__NR_FGT_GROUP_IDS__]; 304 305 /* 306 * Stage 2 paging state for VMs with nested S2 using a virtual 307 * VMID. 308 */ 309 struct kvm_s2_mmu *nested_mmus; 310 size_t nested_mmus_size; 311 int nested_mmus_next; 312 313 /* Interrupt controller */ 314 struct vgic_dist vgic; 315 316 /* Timers */ 317 struct arch_timer_vm_data timer_data; 318 319 /* Mandated version of PSCI */ 320 u32 psci_version; 321 322 /* Protects VM-scoped configuration data */ 323 struct mutex config_lock; 324 325 /* 326 * If we encounter a data abort without valid instruction syndrome 327 * information, report this to user space. User space can (and 328 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is 329 * supported. 330 */ 331 #define KVM_ARCH_FLAG_RETURN_NISV_IO_ABORT_TO_USER 0 332 /* Memory Tagging Extension enabled for the guest */ 333 #define KVM_ARCH_FLAG_MTE_ENABLED 1 334 /* At least one vCPU has ran in the VM */ 335 #define KVM_ARCH_FLAG_HAS_RAN_ONCE 2 336 /* The vCPU feature set for the VM is configured */ 337 #define KVM_ARCH_FLAG_VCPU_FEATURES_CONFIGURED 3 338 /* PSCI SYSTEM_SUSPEND enabled for the guest */ 339 #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED 4 340 /* VM counter offset */ 341 #define KVM_ARCH_FLAG_VM_COUNTER_OFFSET 5 342 /* Timer PPIs made immutable */ 343 #define KVM_ARCH_FLAG_TIMER_PPIS_IMMUTABLE 6 344 /* Initial ID reg values loaded */ 345 #define KVM_ARCH_FLAG_ID_REGS_INITIALIZED 7 346 /* Fine-Grained UNDEF initialised */ 347 #define KVM_ARCH_FLAG_FGU_INITIALIZED 8 348 /* SVE exposed to guest */ 349 #define KVM_ARCH_FLAG_GUEST_HAS_SVE 9 350 /* MIDR_EL1, REVIDR_EL1, and AIDR_EL1 are writable from userspace */ 351 #define KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS 10 352 unsigned long flags; 353 354 /* VM-wide vCPU feature set */ 355 DECLARE_BITMAP(vcpu_features, KVM_VCPU_MAX_FEATURES); 356 357 /* MPIDR to vcpu index mapping, optional */ 358 struct kvm_mpidr_data *mpidr_data; 359 360 /* 361 * VM-wide PMU filter, implemented as a bitmap and big enough for 362 * up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+). 363 */ 364 unsigned long *pmu_filter; 365 struct arm_pmu *arm_pmu; 366 367 cpumask_var_t supported_cpus; 368 369 /* Maximum number of counters for the guest */ 370 u8 nr_pmu_counters; 371 372 /* Iterator for idreg debugfs */ 373 u8 idreg_debugfs_iter; 374 375 /* Hypercall features firmware registers' descriptor */ 376 struct kvm_smccc_features smccc_feat; 377 struct maple_tree smccc_filter; 378 379 /* 380 * Emulated CPU ID registers per VM 381 * (Op0, Op1, CRn, CRm, Op2) of the ID registers to be saved in it 382 * is (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8. 383 * 384 * These emulated idregs are VM-wide, but accessed from the context of a vCPU. 385 * Atomic access to multiple idregs are guarded by kvm_arch.config_lock. 386 */ 387 #define IDREG_IDX(id) (((sys_reg_CRm(id) - 1) << 3) | sys_reg_Op2(id)) 388 #define KVM_ARM_ID_REG_NUM (IDREG_IDX(sys_reg(3, 0, 0, 7, 7)) + 1) 389 u64 id_regs[KVM_ARM_ID_REG_NUM]; 390 391 u64 midr_el1; 392 u64 revidr_el1; 393 u64 aidr_el1; 394 u64 ctr_el0; 395 396 /* Masks for VNCR-backed and general EL2 sysregs */ 397 struct kvm_sysreg_masks *sysreg_masks; 398 399 /* Count the number of VNCR_EL2 currently mapped */ 400 atomic_t vncr_map_count; 401 402 /* 403 * For an untrusted host VM, 'pkvm.handle' is used to lookup 404 * the associated pKVM instance in the hypervisor. 405 */ 406 struct kvm_protected_vm pkvm; 407 }; 408 409 struct kvm_vcpu_fault_info { 410 u64 esr_el2; /* Hyp Syndrom Register */ 411 u64 far_el2; /* Hyp Fault Address Register */ 412 u64 hpfar_el2; /* Hyp IPA Fault Address Register */ 413 u64 disr_el1; /* Deferred [SError] Status Register */ 414 }; 415 416 /* 417 * VNCR() just places the VNCR_capable registers in the enum after 418 * __VNCR_START__, and the value (after correction) to be an 8-byte offset 419 * from the VNCR base. As we don't require the enum to be otherwise ordered, 420 * we need the terrible hack below to ensure that we correctly size the 421 * sys_regs array, no matter what. 422 * 423 * The __MAX__ macro has been lifted from Sean Eron Anderson's wonderful 424 * treasure trove of bit hacks: 425 * https://graphics.stanford.edu/~seander/bithacks.html#IntegerMinOrMax 426 */ 427 #define __MAX__(x,y) ((x) ^ (((x) ^ (y)) & -((x) < (y)))) 428 #define VNCR(r) \ 429 __before_##r, \ 430 r = __VNCR_START__ + ((VNCR_ ## r) / 8), \ 431 __after_##r = __MAX__(__before_##r - 1, r) 432 433 #define MARKER(m) \ 434 m, __after_##m = m - 1 435 436 enum vcpu_sysreg { 437 __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ 438 MPIDR_EL1, /* MultiProcessor Affinity Register */ 439 CLIDR_EL1, /* Cache Level ID Register */ 440 CSSELR_EL1, /* Cache Size Selection Register */ 441 TPIDR_EL0, /* Thread ID, User R/W */ 442 TPIDRRO_EL0, /* Thread ID, User R/O */ 443 TPIDR_EL1, /* Thread ID, Privileged */ 444 CNTKCTL_EL1, /* Timer Control Register (EL1) */ 445 PAR_EL1, /* Physical Address Register */ 446 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ 447 OSLSR_EL1, /* OS Lock Status Register */ 448 DISR_EL1, /* Deferred Interrupt Status Register */ 449 450 /* Performance Monitors Registers */ 451 PMCR_EL0, /* Control Register */ 452 PMSELR_EL0, /* Event Counter Selection Register */ 453 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */ 454 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30, 455 PMCCNTR_EL0, /* Cycle Counter Register */ 456 PMEVTYPER0_EL0, /* Event Type Register (0-30) */ 457 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30, 458 PMCCFILTR_EL0, /* Cycle Count Filter Register */ 459 PMCNTENSET_EL0, /* Count Enable Set Register */ 460 PMINTENSET_EL1, /* Interrupt Enable Set Register */ 461 PMOVSSET_EL0, /* Overflow Flag Status Set Register */ 462 PMUSERENR_EL0, /* User Enable Register */ 463 464 /* Pointer Authentication Registers in a strict increasing order. */ 465 APIAKEYLO_EL1, 466 APIAKEYHI_EL1, 467 APIBKEYLO_EL1, 468 APIBKEYHI_EL1, 469 APDAKEYLO_EL1, 470 APDAKEYHI_EL1, 471 APDBKEYLO_EL1, 472 APDBKEYHI_EL1, 473 APGAKEYLO_EL1, 474 APGAKEYHI_EL1, 475 476 /* Memory Tagging Extension registers */ 477 RGSR_EL1, /* Random Allocation Tag Seed Register */ 478 GCR_EL1, /* Tag Control Register */ 479 TFSRE0_EL1, /* Tag Fault Status Register (EL0) */ 480 481 POR_EL0, /* Permission Overlay Register 0 (EL0) */ 482 483 /* FP/SIMD/SVE */ 484 SVCR, 485 FPMR, 486 487 /* 32bit specific registers. */ 488 DACR32_EL2, /* Domain Access Control Register */ 489 IFSR32_EL2, /* Instruction Fault Status Register */ 490 FPEXC32_EL2, /* Floating-Point Exception Control Register */ 491 DBGVCR32_EL2, /* Debug Vector Catch Register */ 492 493 /* EL2 registers */ 494 SCTLR_EL2, /* System Control Register (EL2) */ 495 ACTLR_EL2, /* Auxiliary Control Register (EL2) */ 496 CPTR_EL2, /* Architectural Feature Trap Register (EL2) */ 497 HACR_EL2, /* Hypervisor Auxiliary Control Register */ 498 ZCR_EL2, /* SVE Control Register (EL2) */ 499 TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */ 500 TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */ 501 TCR_EL2, /* Translation Control Register (EL2) */ 502 PIRE0_EL2, /* Permission Indirection Register 0 (EL2) */ 503 PIR_EL2, /* Permission Indirection Register 1 (EL2) */ 504 POR_EL2, /* Permission Overlay Register 2 (EL2) */ 505 SPSR_EL2, /* EL2 saved program status register */ 506 ELR_EL2, /* EL2 exception link register */ 507 AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */ 508 AFSR1_EL2, /* Auxiliary Fault Status Register 1 (EL2) */ 509 ESR_EL2, /* Exception Syndrome Register (EL2) */ 510 FAR_EL2, /* Fault Address Register (EL2) */ 511 HPFAR_EL2, /* Hypervisor IPA Fault Address Register */ 512 MAIR_EL2, /* Memory Attribute Indirection Register (EL2) */ 513 AMAIR_EL2, /* Auxiliary Memory Attribute Indirection Register (EL2) */ 514 VBAR_EL2, /* Vector Base Address Register (EL2) */ 515 RVBAR_EL2, /* Reset Vector Base Address Register */ 516 CONTEXTIDR_EL2, /* Context ID Register (EL2) */ 517 SP_EL2, /* EL2 Stack Pointer */ 518 CNTHP_CTL_EL2, 519 CNTHP_CVAL_EL2, 520 CNTHV_CTL_EL2, 521 CNTHV_CVAL_EL2, 522 523 /* Anything from this can be RES0/RES1 sanitised */ 524 MARKER(__SANITISED_REG_START__), 525 TCR2_EL2, /* Extended Translation Control Register (EL2) */ 526 SCTLR2_EL2, /* System Control Register 2 (EL2) */ 527 MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */ 528 CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */ 529 530 /* Any VNCR-capable reg goes after this point */ 531 MARKER(__VNCR_START__), 532 533 VNCR(SCTLR_EL1),/* System Control Register */ 534 VNCR(ACTLR_EL1),/* Auxiliary Control Register */ 535 VNCR(CPACR_EL1),/* Coprocessor Access Control */ 536 VNCR(ZCR_EL1), /* SVE Control */ 537 VNCR(TTBR0_EL1),/* Translation Table Base Register 0 */ 538 VNCR(TTBR1_EL1),/* Translation Table Base Register 1 */ 539 VNCR(TCR_EL1), /* Translation Control Register */ 540 VNCR(TCR2_EL1), /* Extended Translation Control Register */ 541 VNCR(SCTLR2_EL1), /* System Control Register 2 */ 542 VNCR(ESR_EL1), /* Exception Syndrome Register */ 543 VNCR(AFSR0_EL1),/* Auxiliary Fault Status Register 0 */ 544 VNCR(AFSR1_EL1),/* Auxiliary Fault Status Register 1 */ 545 VNCR(FAR_EL1), /* Fault Address Register */ 546 VNCR(MAIR_EL1), /* Memory Attribute Indirection Register */ 547 VNCR(VBAR_EL1), /* Vector Base Address Register */ 548 VNCR(CONTEXTIDR_EL1), /* Context ID Register */ 549 VNCR(AMAIR_EL1),/* Aux Memory Attribute Indirection Register */ 550 VNCR(MDSCR_EL1),/* Monitor Debug System Control Register */ 551 VNCR(ELR_EL1), 552 VNCR(SP_EL1), 553 VNCR(SPSR_EL1), 554 VNCR(TFSR_EL1), /* Tag Fault Status Register (EL1) */ 555 VNCR(VPIDR_EL2),/* Virtualization Processor ID Register */ 556 VNCR(VMPIDR_EL2),/* Virtualization Multiprocessor ID Register */ 557 VNCR(HCR_EL2), /* Hypervisor Configuration Register */ 558 VNCR(HSTR_EL2), /* Hypervisor System Trap Register */ 559 VNCR(VTTBR_EL2),/* Virtualization Translation Table Base Register */ 560 VNCR(VTCR_EL2), /* Virtualization Translation Control Register */ 561 VNCR(TPIDR_EL2),/* EL2 Software Thread ID Register */ 562 VNCR(HCRX_EL2), /* Extended Hypervisor Configuration Register */ 563 564 /* Permission Indirection Extension registers */ 565 VNCR(PIR_EL1), /* Permission Indirection Register 1 (EL1) */ 566 VNCR(PIRE0_EL1), /* Permission Indirection Register 0 (EL1) */ 567 568 VNCR(POR_EL1), /* Permission Overlay Register 1 (EL1) */ 569 570 /* FEAT_RAS registers */ 571 VNCR(VDISR_EL2), 572 VNCR(VSESR_EL2), 573 574 VNCR(HFGRTR_EL2), 575 VNCR(HFGWTR_EL2), 576 VNCR(HFGITR_EL2), 577 VNCR(HDFGRTR_EL2), 578 VNCR(HDFGWTR_EL2), 579 VNCR(HAFGRTR_EL2), 580 VNCR(HFGRTR2_EL2), 581 VNCR(HFGWTR2_EL2), 582 VNCR(HFGITR2_EL2), 583 VNCR(HDFGRTR2_EL2), 584 VNCR(HDFGWTR2_EL2), 585 586 VNCR(VNCR_EL2), 587 588 VNCR(CNTVOFF_EL2), 589 VNCR(CNTV_CVAL_EL0), 590 VNCR(CNTV_CTL_EL0), 591 VNCR(CNTP_CVAL_EL0), 592 VNCR(CNTP_CTL_EL0), 593 594 VNCR(ICH_LR0_EL2), 595 VNCR(ICH_LR1_EL2), 596 VNCR(ICH_LR2_EL2), 597 VNCR(ICH_LR3_EL2), 598 VNCR(ICH_LR4_EL2), 599 VNCR(ICH_LR5_EL2), 600 VNCR(ICH_LR6_EL2), 601 VNCR(ICH_LR7_EL2), 602 VNCR(ICH_LR8_EL2), 603 VNCR(ICH_LR9_EL2), 604 VNCR(ICH_LR10_EL2), 605 VNCR(ICH_LR11_EL2), 606 VNCR(ICH_LR12_EL2), 607 VNCR(ICH_LR13_EL2), 608 VNCR(ICH_LR14_EL2), 609 VNCR(ICH_LR15_EL2), 610 611 VNCR(ICH_AP0R0_EL2), 612 VNCR(ICH_AP0R1_EL2), 613 VNCR(ICH_AP0R2_EL2), 614 VNCR(ICH_AP0R3_EL2), 615 VNCR(ICH_AP1R0_EL2), 616 VNCR(ICH_AP1R1_EL2), 617 VNCR(ICH_AP1R2_EL2), 618 VNCR(ICH_AP1R3_EL2), 619 VNCR(ICH_HCR_EL2), 620 VNCR(ICH_VMCR_EL2), 621 622 NR_SYS_REGS /* Nothing after this line! */ 623 }; 624 625 struct kvm_sysreg_masks { 626 struct { 627 u64 res0; 628 u64 res1; 629 } mask[NR_SYS_REGS - __SANITISED_REG_START__]; 630 }; 631 632 struct fgt_masks { 633 const char *str; 634 u64 mask; 635 u64 nmask; 636 u64 res0; 637 }; 638 639 extern struct fgt_masks hfgrtr_masks; 640 extern struct fgt_masks hfgwtr_masks; 641 extern struct fgt_masks hfgitr_masks; 642 extern struct fgt_masks hdfgrtr_masks; 643 extern struct fgt_masks hdfgwtr_masks; 644 extern struct fgt_masks hafgrtr_masks; 645 extern struct fgt_masks hfgrtr2_masks; 646 extern struct fgt_masks hfgwtr2_masks; 647 extern struct fgt_masks hfgitr2_masks; 648 extern struct fgt_masks hdfgrtr2_masks; 649 extern struct fgt_masks hdfgwtr2_masks; 650 651 extern struct fgt_masks kvm_nvhe_sym(hfgrtr_masks); 652 extern struct fgt_masks kvm_nvhe_sym(hfgwtr_masks); 653 extern struct fgt_masks kvm_nvhe_sym(hfgitr_masks); 654 extern struct fgt_masks kvm_nvhe_sym(hdfgrtr_masks); 655 extern struct fgt_masks kvm_nvhe_sym(hdfgwtr_masks); 656 extern struct fgt_masks kvm_nvhe_sym(hafgrtr_masks); 657 extern struct fgt_masks kvm_nvhe_sym(hfgrtr2_masks); 658 extern struct fgt_masks kvm_nvhe_sym(hfgwtr2_masks); 659 extern struct fgt_masks kvm_nvhe_sym(hfgitr2_masks); 660 extern struct fgt_masks kvm_nvhe_sym(hdfgrtr2_masks); 661 extern struct fgt_masks kvm_nvhe_sym(hdfgwtr2_masks); 662 663 struct kvm_cpu_context { 664 struct user_pt_regs regs; /* sp = sp_el0 */ 665 666 u64 spsr_abt; 667 u64 spsr_und; 668 u64 spsr_irq; 669 u64 spsr_fiq; 670 671 struct user_fpsimd_state fp_regs; 672 673 u64 sys_regs[NR_SYS_REGS]; 674 675 struct kvm_vcpu *__hyp_running_vcpu; 676 677 /* This pointer has to be 4kB aligned. */ 678 u64 *vncr_array; 679 }; 680 681 struct cpu_sve_state { 682 __u64 zcr_el1; 683 684 /* 685 * Ordering is important since __sve_save_state/__sve_restore_state 686 * relies on it. 687 */ 688 __u32 fpsr; 689 __u32 fpcr; 690 691 /* Must be SVE_VQ_BYTES (128 bit) aligned. */ 692 __u8 sve_regs[]; 693 }; 694 695 /* 696 * This structure is instantiated on a per-CPU basis, and contains 697 * data that is: 698 * 699 * - tied to a single physical CPU, and 700 * - either have a lifetime that does not extend past vcpu_put() 701 * - or is an invariant for the lifetime of the system 702 * 703 * Use host_data_ptr(field) as a way to access a pointer to such a 704 * field. 705 */ 706 struct kvm_host_data { 707 #define KVM_HOST_DATA_FLAG_HAS_SPE 0 708 #define KVM_HOST_DATA_FLAG_HAS_TRBE 1 709 #define KVM_HOST_DATA_FLAG_TRBE_ENABLED 4 710 #define KVM_HOST_DATA_FLAG_EL1_TRACING_CONFIGURED 5 711 #define KVM_HOST_DATA_FLAG_VCPU_IN_HYP_CONTEXT 6 712 #define KVM_HOST_DATA_FLAG_L1_VNCR_MAPPED 7 713 #define KVM_HOST_DATA_FLAG_HAS_BRBE 8 714 unsigned long flags; 715 716 struct kvm_cpu_context host_ctxt; 717 718 /* 719 * Hyp VA. 720 * sve_state is only used in pKVM and if system_supports_sve(). 721 */ 722 struct cpu_sve_state *sve_state; 723 724 /* Used by pKVM only. */ 725 u64 fpmr; 726 727 /* Ownership of the FP regs */ 728 enum { 729 FP_STATE_FREE, 730 FP_STATE_HOST_OWNED, 731 FP_STATE_GUEST_OWNED, 732 } fp_owner; 733 734 /* 735 * host_debug_state contains the host registers which are 736 * saved and restored during world switches. 737 */ 738 struct { 739 /* {Break,watch}point registers */ 740 struct kvm_guest_debug_arch regs; 741 /* Statistical profiling extension */ 742 u64 pmscr_el1; 743 /* Self-hosted trace */ 744 u64 trfcr_el1; 745 /* Values of trap registers for the host before guest entry. */ 746 u64 mdcr_el2; 747 u64 brbcr_el1; 748 } host_debug_state; 749 750 /* Guest trace filter value */ 751 u64 trfcr_while_in_guest; 752 753 /* Number of programmable event counters (PMCR_EL0.N) for this CPU */ 754 unsigned int nr_event_counters; 755 756 /* Number of debug breakpoints/watchpoints for this CPU (minus 1) */ 757 unsigned int debug_brps; 758 unsigned int debug_wrps; 759 }; 760 761 struct kvm_host_psci_config { 762 /* PSCI version used by host. */ 763 u32 version; 764 u32 smccc_version; 765 766 /* Function IDs used by host if version is v0.1. */ 767 struct psci_0_1_function_ids function_ids_0_1; 768 769 bool psci_0_1_cpu_suspend_implemented; 770 bool psci_0_1_cpu_on_implemented; 771 bool psci_0_1_cpu_off_implemented; 772 bool psci_0_1_migrate_implemented; 773 }; 774 775 extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config); 776 #define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config) 777 778 extern s64 kvm_nvhe_sym(hyp_physvirt_offset); 779 #define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset) 780 781 extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS]; 782 #define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map) 783 784 struct vcpu_reset_state { 785 unsigned long pc; 786 unsigned long r0; 787 bool be; 788 bool reset; 789 }; 790 791 struct vncr_tlb; 792 793 struct kvm_vcpu_arch { 794 struct kvm_cpu_context ctxt; 795 796 /* 797 * Guest floating point state 798 * 799 * The architecture has two main floating point extensions, 800 * the original FPSIMD and SVE. These have overlapping 801 * register views, with the FPSIMD V registers occupying the 802 * low 128 bits of the SVE Z registers. When the core 803 * floating point code saves the register state of a task it 804 * records which view it saved in fp_type. 805 */ 806 void *sve_state; 807 enum fp_type fp_type; 808 unsigned int sve_max_vl; 809 810 /* Stage 2 paging state used by the hardware on next switch */ 811 struct kvm_s2_mmu *hw_mmu; 812 813 /* Values of trap registers for the guest. */ 814 u64 hcr_el2; 815 u64 hcrx_el2; 816 u64 mdcr_el2; 817 818 /* Exception Information */ 819 struct kvm_vcpu_fault_info fault; 820 821 /* Configuration flags, set once and for all before the vcpu can run */ 822 u8 cflags; 823 824 /* Input flags to the hypervisor code, potentially cleared after use */ 825 u8 iflags; 826 827 /* State flags for kernel bookkeeping, unused by the hypervisor code */ 828 u16 sflags; 829 830 /* 831 * Don't run the guest (internal implementation need). 832 * 833 * Contrary to the flags above, this is set/cleared outside of 834 * a vcpu context, and thus cannot be mixed with the flags 835 * themselves (or the flag accesses need to be made atomic). 836 */ 837 bool pause; 838 839 /* 840 * We maintain more than a single set of debug registers to support 841 * debugging the guest from the host and to maintain separate host and 842 * guest state during world switches. vcpu_debug_state are the debug 843 * registers of the vcpu as the guest sees them. 844 * 845 * external_debug_state contains the debug values we want to debug the 846 * guest. This is set via the KVM_SET_GUEST_DEBUG ioctl. 847 */ 848 struct kvm_guest_debug_arch vcpu_debug_state; 849 struct kvm_guest_debug_arch external_debug_state; 850 u64 external_mdscr_el1; 851 852 enum { 853 VCPU_DEBUG_FREE, 854 VCPU_DEBUG_HOST_OWNED, 855 VCPU_DEBUG_GUEST_OWNED, 856 } debug_owner; 857 858 /* VGIC state */ 859 struct vgic_cpu vgic_cpu; 860 struct arch_timer_cpu timer_cpu; 861 struct kvm_pmu pmu; 862 863 /* vcpu power state */ 864 struct kvm_mp_state mp_state; 865 spinlock_t mp_state_lock; 866 867 /* Cache some mmu pages needed inside spinlock regions */ 868 struct kvm_mmu_memory_cache mmu_page_cache; 869 870 /* Pages to top-up the pKVM/EL2 guest pool */ 871 struct kvm_hyp_memcache pkvm_memcache; 872 873 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */ 874 u64 vsesr_el2; 875 876 /* Additional reset state */ 877 struct vcpu_reset_state reset_state; 878 879 /* Guest PV state */ 880 struct { 881 u64 last_steal; 882 gpa_t base; 883 } steal; 884 885 /* Per-vcpu CCSIDR override or NULL */ 886 u32 *ccsidr; 887 888 /* Per-vcpu TLB for VNCR_EL2 -- NULL when !NV */ 889 struct vncr_tlb *vncr_tlb; 890 }; 891 892 /* 893 * Each 'flag' is composed of a comma-separated triplet: 894 * 895 * - the flag-set it belongs to in the vcpu->arch structure 896 * - the value for that flag 897 * - the mask for that flag 898 * 899 * __vcpu_single_flag() builds such a triplet for a single-bit flag. 900 * unpack_vcpu_flag() extract the flag value from the triplet for 901 * direct use outside of the flag accessors. 902 */ 903 #define __vcpu_single_flag(_set, _f) _set, (_f), (_f) 904 905 #define __unpack_flag(_set, _f, _m) _f 906 #define unpack_vcpu_flag(...) __unpack_flag(__VA_ARGS__) 907 908 #define __build_check_flag(v, flagset, f, m) \ 909 do { \ 910 typeof(v->arch.flagset) *_fset; \ 911 \ 912 /* Check that the flags fit in the mask */ \ 913 BUILD_BUG_ON(HWEIGHT(m) != HWEIGHT((f) | (m))); \ 914 /* Check that the flags fit in the type */ \ 915 BUILD_BUG_ON((sizeof(*_fset) * 8) <= __fls(m)); \ 916 } while (0) 917 918 #define __vcpu_get_flag(v, flagset, f, m) \ 919 ({ \ 920 __build_check_flag(v, flagset, f, m); \ 921 \ 922 READ_ONCE(v->arch.flagset) & (m); \ 923 }) 924 925 /* 926 * Note that the set/clear accessors must be preempt-safe in order to 927 * avoid nesting them with load/put which also manipulate flags... 928 */ 929 #ifdef __KVM_NVHE_HYPERVISOR__ 930 /* the nVHE hypervisor is always non-preemptible */ 931 #define __vcpu_flags_preempt_disable() 932 #define __vcpu_flags_preempt_enable() 933 #else 934 #define __vcpu_flags_preempt_disable() preempt_disable() 935 #define __vcpu_flags_preempt_enable() preempt_enable() 936 #endif 937 938 #define __vcpu_set_flag(v, flagset, f, m) \ 939 do { \ 940 typeof(v->arch.flagset) *fset; \ 941 \ 942 __build_check_flag(v, flagset, f, m); \ 943 \ 944 fset = &v->arch.flagset; \ 945 __vcpu_flags_preempt_disable(); \ 946 if (HWEIGHT(m) > 1) \ 947 *fset &= ~(m); \ 948 *fset |= (f); \ 949 __vcpu_flags_preempt_enable(); \ 950 } while (0) 951 952 #define __vcpu_clear_flag(v, flagset, f, m) \ 953 do { \ 954 typeof(v->arch.flagset) *fset; \ 955 \ 956 __build_check_flag(v, flagset, f, m); \ 957 \ 958 fset = &v->arch.flagset; \ 959 __vcpu_flags_preempt_disable(); \ 960 *fset &= ~(m); \ 961 __vcpu_flags_preempt_enable(); \ 962 } while (0) 963 964 #define __vcpu_test_and_clear_flag(v, flagset, f, m) \ 965 ({ \ 966 typeof(v->arch.flagset) set; \ 967 \ 968 set = __vcpu_get_flag(v, flagset, f, m); \ 969 __vcpu_clear_flag(v, flagset, f, m); \ 970 \ 971 set; \ 972 }) 973 974 #define vcpu_get_flag(v, ...) __vcpu_get_flag((v), __VA_ARGS__) 975 #define vcpu_set_flag(v, ...) __vcpu_set_flag((v), __VA_ARGS__) 976 #define vcpu_clear_flag(v, ...) __vcpu_clear_flag((v), __VA_ARGS__) 977 #define vcpu_test_and_clear_flag(v, ...) \ 978 __vcpu_test_and_clear_flag((v), __VA_ARGS__) 979 980 /* KVM_ARM_VCPU_INIT completed */ 981 #define VCPU_INITIALIZED __vcpu_single_flag(cflags, BIT(0)) 982 /* SVE config completed */ 983 #define VCPU_SVE_FINALIZED __vcpu_single_flag(cflags, BIT(1)) 984 /* pKVM VCPU setup completed */ 985 #define VCPU_PKVM_FINALIZED __vcpu_single_flag(cflags, BIT(2)) 986 987 /* Exception pending */ 988 #define PENDING_EXCEPTION __vcpu_single_flag(iflags, BIT(0)) 989 /* 990 * PC increment. Overlaps with EXCEPT_MASK on purpose so that it can't 991 * be set together with an exception... 992 */ 993 #define INCREMENT_PC __vcpu_single_flag(iflags, BIT(1)) 994 /* Target EL/MODE (not a single flag, but let's abuse the macro) */ 995 #define EXCEPT_MASK __vcpu_single_flag(iflags, GENMASK(3, 1)) 996 997 /* Helpers to encode exceptions with minimum fuss */ 998 #define __EXCEPT_MASK_VAL unpack_vcpu_flag(EXCEPT_MASK) 999 #define __EXCEPT_SHIFT __builtin_ctzl(__EXCEPT_MASK_VAL) 1000 #define __vcpu_except_flags(_f) iflags, (_f << __EXCEPT_SHIFT), __EXCEPT_MASK_VAL 1001 1002 /* 1003 * When PENDING_EXCEPTION is set, EXCEPT_MASK can take the following 1004 * values: 1005 * 1006 * For AArch32 EL1: 1007 */ 1008 #define EXCEPT_AA32_UND __vcpu_except_flags(0) 1009 #define EXCEPT_AA32_IABT __vcpu_except_flags(1) 1010 #define EXCEPT_AA32_DABT __vcpu_except_flags(2) 1011 /* For AArch64: */ 1012 #define EXCEPT_AA64_EL1_SYNC __vcpu_except_flags(0) 1013 #define EXCEPT_AA64_EL1_IRQ __vcpu_except_flags(1) 1014 #define EXCEPT_AA64_EL1_FIQ __vcpu_except_flags(2) 1015 #define EXCEPT_AA64_EL1_SERR __vcpu_except_flags(3) 1016 /* For AArch64 with NV: */ 1017 #define EXCEPT_AA64_EL2_SYNC __vcpu_except_flags(4) 1018 #define EXCEPT_AA64_EL2_IRQ __vcpu_except_flags(5) 1019 #define EXCEPT_AA64_EL2_FIQ __vcpu_except_flags(6) 1020 #define EXCEPT_AA64_EL2_SERR __vcpu_except_flags(7) 1021 1022 /* Physical CPU not in supported_cpus */ 1023 #define ON_UNSUPPORTED_CPU __vcpu_single_flag(sflags, BIT(0)) 1024 /* WFIT instruction trapped */ 1025 #define IN_WFIT __vcpu_single_flag(sflags, BIT(1)) 1026 /* vcpu system registers loaded on physical CPU */ 1027 #define SYSREGS_ON_CPU __vcpu_single_flag(sflags, BIT(2)) 1028 /* Software step state is Active-pending for external debug */ 1029 #define HOST_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(3)) 1030 /* Software step state is Active pending for guest debug */ 1031 #define GUEST_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(4)) 1032 /* PMUSERENR for the guest EL0 is on physical CPU */ 1033 #define PMUSERENR_ON_CPU __vcpu_single_flag(sflags, BIT(5)) 1034 /* WFI instruction trapped */ 1035 #define IN_WFI __vcpu_single_flag(sflags, BIT(6)) 1036 /* KVM is currently emulating a nested ERET */ 1037 #define IN_NESTED_ERET __vcpu_single_flag(sflags, BIT(7)) 1038 /* SError pending for nested guest */ 1039 #define NESTED_SERROR_PENDING __vcpu_single_flag(sflags, BIT(8)) 1040 1041 1042 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */ 1043 #define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) + \ 1044 sve_ffr_offset((vcpu)->arch.sve_max_vl)) 1045 1046 #define vcpu_sve_max_vq(vcpu) sve_vq_from_vl((vcpu)->arch.sve_max_vl) 1047 1048 #define vcpu_sve_zcr_elx(vcpu) \ 1049 (unlikely(is_hyp_ctxt(vcpu)) ? ZCR_EL2 : ZCR_EL1) 1050 1051 #define sve_state_size_from_vl(sve_max_vl) ({ \ 1052 size_t __size_ret; \ 1053 unsigned int __vq; \ 1054 \ 1055 if (WARN_ON(!sve_vl_valid(sve_max_vl))) { \ 1056 __size_ret = 0; \ 1057 } else { \ 1058 __vq = sve_vq_from_vl(sve_max_vl); \ 1059 __size_ret = SVE_SIG_REGS_SIZE(__vq); \ 1060 } \ 1061 \ 1062 __size_ret; \ 1063 }) 1064 1065 #define vcpu_sve_state_size(vcpu) sve_state_size_from_vl((vcpu)->arch.sve_max_vl) 1066 1067 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \ 1068 KVM_GUESTDBG_USE_SW_BP | \ 1069 KVM_GUESTDBG_USE_HW | \ 1070 KVM_GUESTDBG_SINGLESTEP) 1071 1072 #define kvm_has_sve(kvm) (system_supports_sve() && \ 1073 test_bit(KVM_ARCH_FLAG_GUEST_HAS_SVE, &(kvm)->arch.flags)) 1074 1075 #ifdef __KVM_NVHE_HYPERVISOR__ 1076 #define vcpu_has_sve(vcpu) kvm_has_sve(kern_hyp_va((vcpu)->kvm)) 1077 #else 1078 #define vcpu_has_sve(vcpu) kvm_has_sve((vcpu)->kvm) 1079 #endif 1080 1081 #ifdef CONFIG_ARM64_PTR_AUTH 1082 #define vcpu_has_ptrauth(vcpu) \ 1083 ((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) || \ 1084 cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) && \ 1085 (vcpu_has_feature(vcpu, KVM_ARM_VCPU_PTRAUTH_ADDRESS) || \ 1086 vcpu_has_feature(vcpu, KVM_ARM_VCPU_PTRAUTH_GENERIC))) 1087 #else 1088 #define vcpu_has_ptrauth(vcpu) false 1089 #endif 1090 1091 #define vcpu_on_unsupported_cpu(vcpu) \ 1092 vcpu_get_flag(vcpu, ON_UNSUPPORTED_CPU) 1093 1094 #define vcpu_set_on_unsupported_cpu(vcpu) \ 1095 vcpu_set_flag(vcpu, ON_UNSUPPORTED_CPU) 1096 1097 #define vcpu_clear_on_unsupported_cpu(vcpu) \ 1098 vcpu_clear_flag(vcpu, ON_UNSUPPORTED_CPU) 1099 1100 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.regs) 1101 1102 /* 1103 * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the 1104 * memory backed version of a register, and not the one most recently 1105 * accessed by a running VCPU. For example, for userspace access or 1106 * for system registers that are never context switched, but only 1107 * emulated. 1108 * 1109 * Don't bother with VNCR-based accesses in the nVHE code, it has no 1110 * business dealing with NV. 1111 */ 1112 static inline u64 *___ctxt_sys_reg(const struct kvm_cpu_context *ctxt, int r) 1113 { 1114 #if !defined (__KVM_NVHE_HYPERVISOR__) 1115 if (unlikely(cpus_have_final_cap(ARM64_HAS_NESTED_VIRT) && 1116 r >= __VNCR_START__ && ctxt->vncr_array)) 1117 return &ctxt->vncr_array[r - __VNCR_START__]; 1118 #endif 1119 return (u64 *)&ctxt->sys_regs[r]; 1120 } 1121 1122 #define __ctxt_sys_reg(c,r) \ 1123 ({ \ 1124 BUILD_BUG_ON(__builtin_constant_p(r) && \ 1125 (r) >= NR_SYS_REGS); \ 1126 ___ctxt_sys_reg(c, r); \ 1127 }) 1128 1129 #define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r)) 1130 1131 u64 kvm_vcpu_apply_reg_masks(const struct kvm_vcpu *, enum vcpu_sysreg, u64); 1132 1133 #define __vcpu_assign_sys_reg(v, r, val) \ 1134 do { \ 1135 const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \ 1136 u64 __v = (val); \ 1137 if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \ 1138 __v = kvm_vcpu_apply_reg_masks((v), (r), __v); \ 1139 \ 1140 ctxt_sys_reg(ctxt, (r)) = __v; \ 1141 } while (0) 1142 1143 #define __vcpu_rmw_sys_reg(v, r, op, val) \ 1144 do { \ 1145 const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \ 1146 u64 __v = ctxt_sys_reg(ctxt, (r)); \ 1147 __v op (val); \ 1148 if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \ 1149 __v = kvm_vcpu_apply_reg_masks((v), (r), __v); \ 1150 \ 1151 ctxt_sys_reg(ctxt, (r)) = __v; \ 1152 } while (0) 1153 1154 #define __vcpu_sys_reg(v,r) \ 1155 ({ \ 1156 const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \ 1157 u64 __v = ctxt_sys_reg(ctxt, (r)); \ 1158 if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \ 1159 __v = kvm_vcpu_apply_reg_masks((v), (r), __v); \ 1160 __v; \ 1161 }) 1162 1163 u64 vcpu_read_sys_reg(const struct kvm_vcpu *, enum vcpu_sysreg); 1164 void vcpu_write_sys_reg(struct kvm_vcpu *, u64, enum vcpu_sysreg); 1165 1166 struct kvm_vm_stat { 1167 struct kvm_vm_stat_generic generic; 1168 }; 1169 1170 struct kvm_vcpu_stat { 1171 struct kvm_vcpu_stat_generic generic; 1172 u64 hvc_exit_stat; 1173 u64 wfe_exit_stat; 1174 u64 wfi_exit_stat; 1175 u64 mmio_exit_user; 1176 u64 mmio_exit_kernel; 1177 u64 signal_exits; 1178 u64 exits; 1179 }; 1180 1181 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); 1182 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); 1183 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 1184 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 1185 1186 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu); 1187 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices); 1188 1189 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu, 1190 struct kvm_vcpu_events *events); 1191 1192 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu, 1193 struct kvm_vcpu_events *events); 1194 1195 void kvm_arm_halt_guest(struct kvm *kvm); 1196 void kvm_arm_resume_guest(struct kvm *kvm); 1197 1198 #define vcpu_has_run_once(vcpu) (!!READ_ONCE((vcpu)->pid)) 1199 1200 #ifndef __KVM_NVHE_HYPERVISOR__ 1201 #define kvm_call_hyp_nvhe(f, ...) \ 1202 ({ \ 1203 struct arm_smccc_res res; \ 1204 \ 1205 arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f), \ 1206 ##__VA_ARGS__, &res); \ 1207 WARN_ON(res.a0 != SMCCC_RET_SUCCESS); \ 1208 \ 1209 res.a1; \ 1210 }) 1211 1212 /* 1213 * The isb() below is there to guarantee the same behaviour on VHE as on !VHE, 1214 * where the eret to EL1 acts as a context synchronization event. 1215 */ 1216 #define kvm_call_hyp(f, ...) \ 1217 do { \ 1218 if (has_vhe()) { \ 1219 f(__VA_ARGS__); \ 1220 isb(); \ 1221 } else { \ 1222 kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 1223 } \ 1224 } while(0) 1225 1226 #define kvm_call_hyp_ret(f, ...) \ 1227 ({ \ 1228 typeof(f(__VA_ARGS__)) ret; \ 1229 \ 1230 if (has_vhe()) { \ 1231 ret = f(__VA_ARGS__); \ 1232 } else { \ 1233 ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 1234 } \ 1235 \ 1236 ret; \ 1237 }) 1238 #else /* __KVM_NVHE_HYPERVISOR__ */ 1239 #define kvm_call_hyp(f, ...) f(__VA_ARGS__) 1240 #define kvm_call_hyp_ret(f, ...) f(__VA_ARGS__) 1241 #define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__) 1242 #endif /* __KVM_NVHE_HYPERVISOR__ */ 1243 1244 int handle_exit(struct kvm_vcpu *vcpu, int exception_index); 1245 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index); 1246 1247 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu); 1248 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu); 1249 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu); 1250 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu); 1251 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu); 1252 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu); 1253 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu); 1254 1255 void kvm_sys_regs_create_debugfs(struct kvm *kvm); 1256 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu); 1257 1258 int __init kvm_sys_reg_table_init(void); 1259 struct sys_reg_desc; 1260 int __init populate_sysreg_config(const struct sys_reg_desc *sr, 1261 unsigned int idx); 1262 int __init populate_nv_trap_config(void); 1263 1264 void kvm_calculate_traps(struct kvm_vcpu *vcpu); 1265 1266 /* MMIO helpers */ 1267 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data); 1268 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len); 1269 1270 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu); 1271 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa); 1272 1273 /* 1274 * Returns true if a Performance Monitoring Interrupt (PMI), a.k.a. perf event, 1275 * arrived in guest context. For arm64, any event that arrives while a vCPU is 1276 * loaded is considered to be "in guest". 1277 */ 1278 static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu) 1279 { 1280 return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu; 1281 } 1282 1283 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu); 1284 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu); 1285 void kvm_update_stolen_time(struct kvm_vcpu *vcpu); 1286 1287 bool kvm_arm_pvtime_supported(void); 1288 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu, 1289 struct kvm_device_attr *attr); 1290 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu, 1291 struct kvm_device_attr *attr); 1292 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu, 1293 struct kvm_device_attr *attr); 1294 1295 extern unsigned int __ro_after_init kvm_arm_vmid_bits; 1296 int __init kvm_arm_vmid_alloc_init(void); 1297 void __init kvm_arm_vmid_alloc_free(void); 1298 void kvm_arm_vmid_update(struct kvm_vmid *kvm_vmid); 1299 void kvm_arm_vmid_clear_active(void); 1300 1301 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch) 1302 { 1303 vcpu_arch->steal.base = INVALID_GPA; 1304 } 1305 1306 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch) 1307 { 1308 return (vcpu_arch->steal.base != INVALID_GPA); 1309 } 1310 1311 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); 1312 1313 DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data); 1314 1315 /* 1316 * How we access per-CPU host data depends on the where we access it from, 1317 * and the mode we're in: 1318 * 1319 * - VHE and nVHE hypervisor bits use their locally defined instance 1320 * 1321 * - the rest of the kernel use either the VHE or nVHE one, depending on 1322 * the mode we're running in. 1323 * 1324 * Unless we're in protected mode, fully deprivileged, and the nVHE 1325 * per-CPU stuff is exclusively accessible to the protected EL2 code. 1326 * In this case, the EL1 code uses the *VHE* data as its private state 1327 * (which makes sense in a way as there shouldn't be any shared state 1328 * between the host and the hypervisor). 1329 * 1330 * Yes, this is all totally trivial. Shoot me now. 1331 */ 1332 #if defined(__KVM_NVHE_HYPERVISOR__) || defined(__KVM_VHE_HYPERVISOR__) 1333 #define host_data_ptr(f) (&this_cpu_ptr(&kvm_host_data)->f) 1334 #else 1335 #define host_data_ptr(f) \ 1336 (static_branch_unlikely(&kvm_protected_mode_initialized) ? \ 1337 &this_cpu_ptr(&kvm_host_data)->f : \ 1338 &this_cpu_ptr_hyp_sym(kvm_host_data)->f) 1339 #endif 1340 1341 #define host_data_test_flag(flag) \ 1342 (test_bit(KVM_HOST_DATA_FLAG_##flag, host_data_ptr(flags))) 1343 #define host_data_set_flag(flag) \ 1344 set_bit(KVM_HOST_DATA_FLAG_##flag, host_data_ptr(flags)) 1345 #define host_data_clear_flag(flag) \ 1346 clear_bit(KVM_HOST_DATA_FLAG_##flag, host_data_ptr(flags)) 1347 1348 /* Check whether the FP regs are owned by the guest */ 1349 static inline bool guest_owns_fp_regs(void) 1350 { 1351 return *host_data_ptr(fp_owner) == FP_STATE_GUEST_OWNED; 1352 } 1353 1354 /* Check whether the FP regs are owned by the host */ 1355 static inline bool host_owns_fp_regs(void) 1356 { 1357 return *host_data_ptr(fp_owner) == FP_STATE_HOST_OWNED; 1358 } 1359 1360 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt) 1361 { 1362 /* The host's MPIDR is immutable, so let's set it up at boot time */ 1363 ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr(); 1364 } 1365 1366 static inline bool kvm_system_needs_idmapped_vectors(void) 1367 { 1368 return cpus_have_final_cap(ARM64_SPECTRE_V3A); 1369 } 1370 1371 void kvm_init_host_debug_data(void); 1372 void kvm_vcpu_load_debug(struct kvm_vcpu *vcpu); 1373 void kvm_vcpu_put_debug(struct kvm_vcpu *vcpu); 1374 void kvm_debug_set_guest_ownership(struct kvm_vcpu *vcpu); 1375 void kvm_debug_handle_oslar(struct kvm_vcpu *vcpu, u64 val); 1376 1377 #define kvm_vcpu_os_lock_enabled(vcpu) \ 1378 (!!(__vcpu_sys_reg(vcpu, OSLSR_EL1) & OSLSR_EL1_OSLK)) 1379 1380 #define kvm_debug_regs_in_use(vcpu) \ 1381 ((vcpu)->arch.debug_owner != VCPU_DEBUG_FREE) 1382 #define kvm_host_owns_debug_regs(vcpu) \ 1383 ((vcpu)->arch.debug_owner == VCPU_DEBUG_HOST_OWNED) 1384 #define kvm_guest_owns_debug_regs(vcpu) \ 1385 ((vcpu)->arch.debug_owner == VCPU_DEBUG_GUEST_OWNED) 1386 1387 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, 1388 struct kvm_device_attr *attr); 1389 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, 1390 struct kvm_device_attr *attr); 1391 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, 1392 struct kvm_device_attr *attr); 1393 1394 int kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm, 1395 struct kvm_arm_copy_mte_tags *copy_tags); 1396 int kvm_vm_ioctl_set_counter_offset(struct kvm *kvm, 1397 struct kvm_arm_counter_offset *offset); 1398 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, 1399 struct reg_mask_range *range); 1400 1401 /* Guest/host FPSIMD coordination helpers */ 1402 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu); 1403 void kvm_arch_vcpu_ctxflush_fp(struct kvm_vcpu *vcpu); 1404 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu); 1405 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu); 1406 1407 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr) 1408 { 1409 return (!has_vhe() && attr->exclude_host); 1410 } 1411 1412 #ifdef CONFIG_KVM 1413 void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr); 1414 void kvm_clr_pmu_events(u64 clr); 1415 bool kvm_set_pmuserenr(u64 val); 1416 void kvm_enable_trbe(void); 1417 void kvm_disable_trbe(void); 1418 void kvm_tracing_set_el1_configuration(u64 trfcr_while_in_guest); 1419 #else 1420 static inline void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr) {} 1421 static inline void kvm_clr_pmu_events(u64 clr) {} 1422 static inline bool kvm_set_pmuserenr(u64 val) 1423 { 1424 return false; 1425 } 1426 static inline void kvm_enable_trbe(void) {} 1427 static inline void kvm_disable_trbe(void) {} 1428 static inline void kvm_tracing_set_el1_configuration(u64 trfcr_while_in_guest) {} 1429 #endif 1430 1431 void kvm_vcpu_load_vhe(struct kvm_vcpu *vcpu); 1432 void kvm_vcpu_put_vhe(struct kvm_vcpu *vcpu); 1433 1434 int __init kvm_set_ipa_limit(void); 1435 u32 kvm_get_pa_bits(struct kvm *kvm); 1436 1437 #define __KVM_HAVE_ARCH_VM_ALLOC 1438 struct kvm *kvm_arch_alloc_vm(void); 1439 1440 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS 1441 1442 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS_RANGE 1443 1444 #define kvm_vm_is_protected(kvm) (is_protected_kvm_enabled() && (kvm)->arch.pkvm.enabled) 1445 1446 #define vcpu_is_protected(vcpu) kvm_vm_is_protected((vcpu)->kvm) 1447 1448 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature); 1449 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu); 1450 1451 #define kvm_arm_vcpu_sve_finalized(vcpu) vcpu_get_flag(vcpu, VCPU_SVE_FINALIZED) 1452 1453 #define kvm_has_mte(kvm) \ 1454 (system_supports_mte() && \ 1455 test_bit(KVM_ARCH_FLAG_MTE_ENABLED, &(kvm)->arch.flags)) 1456 1457 #define kvm_supports_32bit_el0() \ 1458 (system_supports_32bit_el0() && \ 1459 !static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1460 1461 #define kvm_vm_has_ran_once(kvm) \ 1462 (test_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &(kvm)->arch.flags)) 1463 1464 static inline bool __vcpu_has_feature(const struct kvm_arch *ka, int feature) 1465 { 1466 return test_bit(feature, ka->vcpu_features); 1467 } 1468 1469 #define kvm_vcpu_has_feature(k, f) __vcpu_has_feature(&(k)->arch, (f)) 1470 #define vcpu_has_feature(v, f) __vcpu_has_feature(&(v)->kvm->arch, (f)) 1471 1472 #define kvm_vcpu_initialized(v) vcpu_get_flag(vcpu, VCPU_INITIALIZED) 1473 1474 int kvm_trng_call(struct kvm_vcpu *vcpu); 1475 #ifdef CONFIG_KVM 1476 extern phys_addr_t hyp_mem_base; 1477 extern phys_addr_t hyp_mem_size; 1478 void __init kvm_hyp_reserve(void); 1479 #else 1480 static inline void kvm_hyp_reserve(void) { } 1481 #endif 1482 1483 void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu); 1484 bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu); 1485 1486 static inline u64 *__vm_id_reg(struct kvm_arch *ka, u32 reg) 1487 { 1488 switch (reg) { 1489 case sys_reg(3, 0, 0, 1, 0) ... sys_reg(3, 0, 0, 7, 7): 1490 return &ka->id_regs[IDREG_IDX(reg)]; 1491 case SYS_CTR_EL0: 1492 return &ka->ctr_el0; 1493 case SYS_MIDR_EL1: 1494 return &ka->midr_el1; 1495 case SYS_REVIDR_EL1: 1496 return &ka->revidr_el1; 1497 case SYS_AIDR_EL1: 1498 return &ka->aidr_el1; 1499 default: 1500 WARN_ON_ONCE(1); 1501 return NULL; 1502 } 1503 } 1504 1505 #define kvm_read_vm_id_reg(kvm, reg) \ 1506 ({ u64 __val = *__vm_id_reg(&(kvm)->arch, reg); __val; }) 1507 1508 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val); 1509 1510 #define __expand_field_sign_unsigned(id, fld, val) \ 1511 ((u64)SYS_FIELD_VALUE(id, fld, val)) 1512 1513 #define __expand_field_sign_signed(id, fld, val) \ 1514 ({ \ 1515 u64 __val = SYS_FIELD_VALUE(id, fld, val); \ 1516 sign_extend64(__val, id##_##fld##_WIDTH - 1); \ 1517 }) 1518 1519 #define get_idreg_field_unsigned(kvm, id, fld) \ 1520 ({ \ 1521 u64 __val = kvm_read_vm_id_reg((kvm), SYS_##id); \ 1522 FIELD_GET(id##_##fld##_MASK, __val); \ 1523 }) 1524 1525 #define get_idreg_field_signed(kvm, id, fld) \ 1526 ({ \ 1527 u64 __val = get_idreg_field_unsigned(kvm, id, fld); \ 1528 sign_extend64(__val, id##_##fld##_WIDTH - 1); \ 1529 }) 1530 1531 #define get_idreg_field_enum(kvm, id, fld) \ 1532 get_idreg_field_unsigned(kvm, id, fld) 1533 1534 #define kvm_cmp_feat_signed(kvm, id, fld, op, limit) \ 1535 (get_idreg_field_signed((kvm), id, fld) op __expand_field_sign_signed(id, fld, limit)) 1536 1537 #define kvm_cmp_feat_unsigned(kvm, id, fld, op, limit) \ 1538 (get_idreg_field_unsigned((kvm), id, fld) op __expand_field_sign_unsigned(id, fld, limit)) 1539 1540 #define kvm_cmp_feat(kvm, id, fld, op, limit) \ 1541 (id##_##fld##_SIGNED ? \ 1542 kvm_cmp_feat_signed(kvm, id, fld, op, limit) : \ 1543 kvm_cmp_feat_unsigned(kvm, id, fld, op, limit)) 1544 1545 #define __kvm_has_feat(kvm, id, fld, limit) \ 1546 kvm_cmp_feat(kvm, id, fld, >=, limit) 1547 1548 #define kvm_has_feat(kvm, ...) __kvm_has_feat(kvm, __VA_ARGS__) 1549 1550 #define __kvm_has_feat_enum(kvm, id, fld, val) \ 1551 kvm_cmp_feat_unsigned(kvm, id, fld, ==, val) 1552 1553 #define kvm_has_feat_enum(kvm, ...) __kvm_has_feat_enum(kvm, __VA_ARGS__) 1554 1555 #define kvm_has_feat_range(kvm, id, fld, min, max) \ 1556 (kvm_cmp_feat(kvm, id, fld, >=, min) && \ 1557 kvm_cmp_feat(kvm, id, fld, <=, max)) 1558 1559 /* Check for a given level of PAuth support */ 1560 #define kvm_has_pauth(k, l) \ 1561 ({ \ 1562 bool pa, pi, pa3; \ 1563 \ 1564 pa = kvm_has_feat((k), ID_AA64ISAR1_EL1, APA, l); \ 1565 pa &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPA, IMP); \ 1566 pi = kvm_has_feat((k), ID_AA64ISAR1_EL1, API, l); \ 1567 pi &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPI, IMP); \ 1568 pa3 = kvm_has_feat((k), ID_AA64ISAR2_EL1, APA3, l); \ 1569 pa3 &= kvm_has_feat((k), ID_AA64ISAR2_EL1, GPA3, IMP); \ 1570 \ 1571 (pa + pi + pa3) == 1; \ 1572 }) 1573 1574 #define kvm_has_fpmr(k) \ 1575 (system_supports_fpmr() && \ 1576 kvm_has_feat((k), ID_AA64PFR2_EL1, FPMR, IMP)) 1577 1578 #define kvm_has_tcr2(k) \ 1579 (kvm_has_feat((k), ID_AA64MMFR3_EL1, TCRX, IMP)) 1580 1581 #define kvm_has_s1pie(k) \ 1582 (kvm_has_feat((k), ID_AA64MMFR3_EL1, S1PIE, IMP)) 1583 1584 #define kvm_has_s1poe(k) \ 1585 (kvm_has_feat((k), ID_AA64MMFR3_EL1, S1POE, IMP)) 1586 1587 #define kvm_has_ras(k) \ 1588 (kvm_has_feat((k), ID_AA64PFR0_EL1, RAS, IMP)) 1589 1590 #define kvm_has_sctlr2(k) \ 1591 (kvm_has_feat((k), ID_AA64MMFR3_EL1, SCTLRX, IMP)) 1592 1593 static inline bool kvm_arch_has_irq_bypass(void) 1594 { 1595 return true; 1596 } 1597 1598 void compute_fgu(struct kvm *kvm, enum fgt_group_id fgt); 1599 void get_reg_fixed_bits(struct kvm *kvm, enum vcpu_sysreg reg, u64 *res0, u64 *res1); 1600 void check_feature_map(void); 1601 1602 1603 #endif /* __ARM64_KVM_HOST_H__ */ 1604