1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/kvm_emulate.h 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 */ 10 11 #ifndef __ARM64_KVM_EMULATE_H__ 12 #define __ARM64_KVM_EMULATE_H__ 13 14 #include <linux/bitfield.h> 15 #include <linux/kvm_host.h> 16 17 #include <asm/debug-monitors.h> 18 #include <asm/esr.h> 19 #include <asm/kvm_arm.h> 20 #include <asm/kvm_hyp.h> 21 #include <asm/kvm_nested.h> 22 #include <asm/ptrace.h> 23 #include <asm/cputype.h> 24 #include <asm/virt.h> 25 26 #define CURRENT_EL_SP_EL0_VECTOR 0x0 27 #define CURRENT_EL_SP_ELx_VECTOR 0x200 28 #define LOWER_EL_AArch64_VECTOR 0x400 29 #define LOWER_EL_AArch32_VECTOR 0x600 30 31 enum exception_type { 32 except_type_sync = 0, 33 except_type_irq = 0x80, 34 except_type_fiq = 0x100, 35 except_type_serror = 0x180, 36 }; 37 38 #define kvm_exception_type_names \ 39 { except_type_sync, "SYNC" }, \ 40 { except_type_irq, "IRQ" }, \ 41 { except_type_fiq, "FIQ" }, \ 42 { except_type_serror, "SERROR" } 43 44 bool kvm_condition_valid32(const struct kvm_vcpu *vcpu); 45 void kvm_skip_instr32(struct kvm_vcpu *vcpu); 46 47 void kvm_inject_undefined(struct kvm_vcpu *vcpu); 48 int kvm_inject_serror_esr(struct kvm_vcpu *vcpu, u64 esr); 49 int kvm_inject_sea(struct kvm_vcpu *vcpu, bool iabt, u64 addr); 50 void kvm_inject_size_fault(struct kvm_vcpu *vcpu); 51 52 static inline int kvm_inject_sea_dabt(struct kvm_vcpu *vcpu, u64 addr) 53 { 54 return kvm_inject_sea(vcpu, false, addr); 55 } 56 57 static inline int kvm_inject_sea_iabt(struct kvm_vcpu *vcpu, u64 addr) 58 { 59 return kvm_inject_sea(vcpu, true, addr); 60 } 61 62 static inline int kvm_inject_serror(struct kvm_vcpu *vcpu) 63 { 64 /* 65 * ESR_ELx.ISV (later renamed to IDS) indicates whether or not 66 * ESR_ELx.ISS contains IMPLEMENTATION DEFINED syndrome information. 67 * 68 * Set the bit when injecting an SError w/o an ESR to indicate ISS 69 * does not follow the architected format. 70 */ 71 return kvm_inject_serror_esr(vcpu, ESR_ELx_ISV); 72 } 73 74 void kvm_vcpu_wfi(struct kvm_vcpu *vcpu); 75 76 void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu); 77 int kvm_inject_nested_sync(struct kvm_vcpu *vcpu, u64 esr_el2); 78 int kvm_inject_nested_irq(struct kvm_vcpu *vcpu); 79 int kvm_inject_nested_sea(struct kvm_vcpu *vcpu, bool iabt, u64 addr); 80 int kvm_inject_nested_serror(struct kvm_vcpu *vcpu, u64 esr); 81 82 static inline void kvm_inject_nested_sve_trap(struct kvm_vcpu *vcpu) 83 { 84 u64 esr = FIELD_PREP(ESR_ELx_EC_MASK, ESR_ELx_EC_SVE) | 85 ESR_ELx_IL; 86 87 kvm_inject_nested_sync(vcpu, esr); 88 } 89 90 #if defined(__KVM_VHE_HYPERVISOR__) || defined(__KVM_NVHE_HYPERVISOR__) 91 static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu) 92 { 93 return !(vcpu->arch.hcr_el2 & HCR_RW); 94 } 95 #else 96 static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu) 97 { 98 return vcpu_has_feature(vcpu, KVM_ARM_VCPU_EL1_32BIT); 99 } 100 #endif 101 102 static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu) 103 { 104 if (!vcpu_has_run_once(vcpu)) 105 vcpu->arch.hcr_el2 = HCR_GUEST_FLAGS; 106 107 /* 108 * For non-FWB CPUs, we trap VM ops (HCR_EL2.TVM) until M+C 109 * get set in SCTLR_EL1 such that we can detect when the guest 110 * MMU gets turned on and do the necessary cache maintenance 111 * then. 112 */ 113 if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 114 vcpu->arch.hcr_el2 |= HCR_TVM; 115 } 116 117 static inline unsigned long *vcpu_hcr(struct kvm_vcpu *vcpu) 118 { 119 return (unsigned long *)&vcpu->arch.hcr_el2; 120 } 121 122 static inline void vcpu_clear_wfx_traps(struct kvm_vcpu *vcpu) 123 { 124 vcpu->arch.hcr_el2 &= ~HCR_TWE; 125 if (atomic_read(&vcpu->arch.vgic_cpu.vgic_v3.its_vpe.vlpi_count) || 126 vcpu->kvm->arch.vgic.nassgireq) 127 vcpu->arch.hcr_el2 &= ~HCR_TWI; 128 else 129 vcpu->arch.hcr_el2 |= HCR_TWI; 130 } 131 132 static inline void vcpu_set_wfx_traps(struct kvm_vcpu *vcpu) 133 { 134 vcpu->arch.hcr_el2 |= HCR_TWE; 135 vcpu->arch.hcr_el2 |= HCR_TWI; 136 } 137 138 static inline unsigned long vcpu_get_vsesr(struct kvm_vcpu *vcpu) 139 { 140 return vcpu->arch.vsesr_el2; 141 } 142 143 static inline void vcpu_set_vsesr(struct kvm_vcpu *vcpu, u64 vsesr) 144 { 145 vcpu->arch.vsesr_el2 = vsesr; 146 } 147 148 static __always_inline unsigned long *vcpu_pc(const struct kvm_vcpu *vcpu) 149 { 150 return (unsigned long *)&vcpu_gp_regs(vcpu)->pc; 151 } 152 153 static __always_inline unsigned long *vcpu_cpsr(const struct kvm_vcpu *vcpu) 154 { 155 return (unsigned long *)&vcpu_gp_regs(vcpu)->pstate; 156 } 157 158 static __always_inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu) 159 { 160 return !!(*vcpu_cpsr(vcpu) & PSR_MODE32_BIT); 161 } 162 163 static __always_inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu) 164 { 165 if (vcpu_mode_is_32bit(vcpu)) 166 return kvm_condition_valid32(vcpu); 167 168 return true; 169 } 170 171 static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu) 172 { 173 *vcpu_cpsr(vcpu) |= PSR_AA32_T_BIT; 174 } 175 176 /* 177 * vcpu_get_reg and vcpu_set_reg should always be passed a register number 178 * coming from a read of ESR_EL2. Otherwise, it may give the wrong result on 179 * AArch32 with banked registers. 180 */ 181 static __always_inline unsigned long vcpu_get_reg(const struct kvm_vcpu *vcpu, 182 u8 reg_num) 183 { 184 return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num]; 185 } 186 187 static __always_inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num, 188 unsigned long val) 189 { 190 if (reg_num != 31) 191 vcpu_gp_regs(vcpu)->regs[reg_num] = val; 192 } 193 194 static inline bool vcpu_is_el2_ctxt(const struct kvm_cpu_context *ctxt) 195 { 196 switch (ctxt->regs.pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) { 197 case PSR_MODE_EL2h: 198 case PSR_MODE_EL2t: 199 return true; 200 default: 201 return false; 202 } 203 } 204 205 static inline bool vcpu_is_el2(const struct kvm_vcpu *vcpu) 206 { 207 return vcpu_is_el2_ctxt(&vcpu->arch.ctxt); 208 } 209 210 static inline bool vcpu_el2_e2h_is_set(const struct kvm_vcpu *vcpu) 211 { 212 return (!cpus_have_final_cap(ARM64_HAS_HCR_NV1) || 213 (__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_E2H)); 214 } 215 216 static inline bool vcpu_el2_tge_is_set(const struct kvm_vcpu *vcpu) 217 { 218 return ctxt_sys_reg(&vcpu->arch.ctxt, HCR_EL2) & HCR_TGE; 219 } 220 221 static inline bool vcpu_el2_amo_is_set(const struct kvm_vcpu *vcpu) 222 { 223 /* 224 * DDI0487L.b Known Issue D22105 225 * 226 * When executing at EL2 and HCR_EL2.{E2H,TGE} = {1, 0} it is 227 * IMPLEMENTATION DEFINED whether the effective value of HCR_EL2.AMO 228 * is the value programmed or 1. 229 * 230 * Make the implementation choice of treating the effective value as 1 as 231 * we cannot subsequently catch changes to TGE or AMO that would 232 * otherwise lead to the SError becoming deliverable. 233 */ 234 if (vcpu_is_el2(vcpu) && vcpu_el2_e2h_is_set(vcpu) && !vcpu_el2_tge_is_set(vcpu)) 235 return true; 236 237 return ctxt_sys_reg(&vcpu->arch.ctxt, HCR_EL2) & HCR_AMO; 238 } 239 240 static inline bool is_hyp_ctxt(const struct kvm_vcpu *vcpu) 241 { 242 bool e2h, tge; 243 u64 hcr; 244 245 if (!vcpu_has_nv(vcpu)) 246 return false; 247 248 hcr = __vcpu_sys_reg(vcpu, HCR_EL2); 249 250 e2h = (hcr & HCR_E2H); 251 tge = (hcr & HCR_TGE); 252 253 /* 254 * We are in a hypervisor context if the vcpu mode is EL2 or 255 * E2H and TGE bits are set. The latter means we are in the user space 256 * of the VHE kernel. ARMv8.1 ARM describes this as 'InHost' 257 * 258 * Note that the HCR_EL2.{E2H,TGE}={0,1} isn't really handled in the 259 * rest of the KVM code, and will result in a misbehaving guest. 260 */ 261 return vcpu_is_el2(vcpu) || (e2h && tge) || tge; 262 } 263 264 static inline bool vcpu_is_host_el0(const struct kvm_vcpu *vcpu) 265 { 266 return is_hyp_ctxt(vcpu) && !vcpu_is_el2(vcpu); 267 } 268 269 static inline bool is_nested_ctxt(struct kvm_vcpu *vcpu) 270 { 271 return vcpu_has_nv(vcpu) && !is_hyp_ctxt(vcpu); 272 } 273 274 static inline bool vserror_state_is_nested(struct kvm_vcpu *vcpu) 275 { 276 if (!is_nested_ctxt(vcpu)) 277 return false; 278 279 return vcpu_el2_amo_is_set(vcpu) || 280 (__vcpu_sys_reg(vcpu, HCRX_EL2) & HCRX_EL2_TMEA); 281 } 282 283 /* 284 * The layout of SPSR for an AArch32 state is different when observed from an 285 * AArch64 SPSR_ELx or an AArch32 SPSR_*. This function generates the AArch32 286 * view given an AArch64 view. 287 * 288 * In ARM DDI 0487E.a see: 289 * 290 * - The AArch64 view (SPSR_EL2) in section C5.2.18, page C5-426 291 * - The AArch32 view (SPSR_abt) in section G8.2.126, page G8-6256 292 * - The AArch32 view (SPSR_und) in section G8.2.132, page G8-6280 293 * 294 * Which show the following differences: 295 * 296 * | Bit | AA64 | AA32 | Notes | 297 * +-----+------+------+-----------------------------| 298 * | 24 | DIT | J | J is RES0 in ARMv8 | 299 * | 21 | SS | DIT | SS doesn't exist in AArch32 | 300 * 301 * ... and all other bits are (currently) common. 302 */ 303 static inline unsigned long host_spsr_to_spsr32(unsigned long spsr) 304 { 305 const unsigned long overlap = BIT(24) | BIT(21); 306 unsigned long dit = !!(spsr & PSR_AA32_DIT_BIT); 307 308 spsr &= ~overlap; 309 310 spsr |= dit << 21; 311 312 return spsr; 313 } 314 315 static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu) 316 { 317 u32 mode; 318 319 if (vcpu_mode_is_32bit(vcpu)) { 320 mode = *vcpu_cpsr(vcpu) & PSR_AA32_MODE_MASK; 321 return mode > PSR_AA32_MODE_USR; 322 } 323 324 mode = *vcpu_cpsr(vcpu) & PSR_MODE_MASK; 325 326 return mode != PSR_MODE_EL0t; 327 } 328 329 static __always_inline u64 kvm_vcpu_get_esr(const struct kvm_vcpu *vcpu) 330 { 331 return vcpu->arch.fault.esr_el2; 332 } 333 334 static inline bool guest_hyp_wfx_traps_enabled(const struct kvm_vcpu *vcpu) 335 { 336 u64 esr = kvm_vcpu_get_esr(vcpu); 337 bool is_wfe = !!(esr & ESR_ELx_WFx_ISS_WFE); 338 u64 hcr_el2 = __vcpu_sys_reg(vcpu, HCR_EL2); 339 340 if (!vcpu_has_nv(vcpu) || vcpu_is_el2(vcpu)) 341 return false; 342 343 return ((is_wfe && (hcr_el2 & HCR_TWE)) || 344 (!is_wfe && (hcr_el2 & HCR_TWI))); 345 } 346 347 static __always_inline int kvm_vcpu_get_condition(const struct kvm_vcpu *vcpu) 348 { 349 u64 esr = kvm_vcpu_get_esr(vcpu); 350 351 if (esr & ESR_ELx_CV) 352 return (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT; 353 354 return -1; 355 } 356 357 static __always_inline unsigned long kvm_vcpu_get_hfar(const struct kvm_vcpu *vcpu) 358 { 359 return vcpu->arch.fault.far_el2; 360 } 361 362 static __always_inline phys_addr_t kvm_vcpu_get_fault_ipa(const struct kvm_vcpu *vcpu) 363 { 364 u64 hpfar = vcpu->arch.fault.hpfar_el2; 365 366 if (unlikely(!(hpfar & HPFAR_EL2_NS))) 367 return INVALID_GPA; 368 369 return FIELD_GET(HPFAR_EL2_FIPA, hpfar) << 12; 370 } 371 372 static inline u64 kvm_vcpu_get_disr(const struct kvm_vcpu *vcpu) 373 { 374 return vcpu->arch.fault.disr_el1; 375 } 376 377 static inline u32 kvm_vcpu_hvc_get_imm(const struct kvm_vcpu *vcpu) 378 { 379 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_xVC_IMM_MASK; 380 } 381 382 static __always_inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu) 383 { 384 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_ISV); 385 } 386 387 static inline unsigned long kvm_vcpu_dabt_iss_nisv_sanitized(const struct kvm_vcpu *vcpu) 388 { 389 return kvm_vcpu_get_esr(vcpu) & (ESR_ELx_CM | ESR_ELx_WNR | ESR_ELx_FSC); 390 } 391 392 static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu) 393 { 394 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_SSE); 395 } 396 397 static inline bool kvm_vcpu_dabt_issf(const struct kvm_vcpu *vcpu) 398 { 399 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_SF); 400 } 401 402 static __always_inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu) 403 { 404 return (kvm_vcpu_get_esr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT; 405 } 406 407 static __always_inline bool kvm_vcpu_abt_iss1tw(const struct kvm_vcpu *vcpu) 408 { 409 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_S1PTW); 410 } 411 412 /* Always check for S1PTW *before* using this. */ 413 static __always_inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu) 414 { 415 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_WNR; 416 } 417 418 static inline bool kvm_vcpu_dabt_is_cm(const struct kvm_vcpu *vcpu) 419 { 420 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_CM); 421 } 422 423 static __always_inline unsigned int kvm_vcpu_dabt_get_as(const struct kvm_vcpu *vcpu) 424 { 425 return 1 << ((kvm_vcpu_get_esr(vcpu) & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT); 426 } 427 428 /* This one is not specific to Data Abort */ 429 static __always_inline bool kvm_vcpu_trap_il_is32bit(const struct kvm_vcpu *vcpu) 430 { 431 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_IL); 432 } 433 434 static __always_inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu) 435 { 436 return ESR_ELx_EC(kvm_vcpu_get_esr(vcpu)); 437 } 438 439 static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu) 440 { 441 return kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_IABT_LOW; 442 } 443 444 static inline bool kvm_vcpu_trap_is_exec_fault(const struct kvm_vcpu *vcpu) 445 { 446 return kvm_vcpu_trap_is_iabt(vcpu) && !kvm_vcpu_abt_iss1tw(vcpu); 447 } 448 449 static __always_inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu) 450 { 451 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC; 452 } 453 454 static inline 455 bool kvm_vcpu_trap_is_permission_fault(const struct kvm_vcpu *vcpu) 456 { 457 return esr_fsc_is_permission_fault(kvm_vcpu_get_esr(vcpu)); 458 } 459 460 static inline 461 bool kvm_vcpu_trap_is_translation_fault(const struct kvm_vcpu *vcpu) 462 { 463 return esr_fsc_is_translation_fault(kvm_vcpu_get_esr(vcpu)); 464 } 465 466 static inline 467 u64 kvm_vcpu_trap_get_perm_fault_granule(const struct kvm_vcpu *vcpu) 468 { 469 unsigned long esr = kvm_vcpu_get_esr(vcpu); 470 471 BUG_ON(!esr_fsc_is_permission_fault(esr)); 472 return BIT(ARM64_HW_PGTABLE_LEVEL_SHIFT(esr & ESR_ELx_FSC_LEVEL)); 473 } 474 475 static __always_inline bool kvm_vcpu_abt_issea(const struct kvm_vcpu *vcpu) 476 { 477 switch (kvm_vcpu_trap_get_fault(vcpu)) { 478 case ESR_ELx_FSC_EXTABT: 479 case ESR_ELx_FSC_SEA_TTW(-1) ... ESR_ELx_FSC_SEA_TTW(3): 480 case ESR_ELx_FSC_SECC: 481 case ESR_ELx_FSC_SECC_TTW(-1) ... ESR_ELx_FSC_SECC_TTW(3): 482 return true; 483 default: 484 return false; 485 } 486 } 487 488 static __always_inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu) 489 { 490 u64 esr = kvm_vcpu_get_esr(vcpu); 491 return ESR_ELx_SYS64_ISS_RT(esr); 492 } 493 494 static inline bool kvm_is_write_fault(struct kvm_vcpu *vcpu) 495 { 496 if (kvm_vcpu_abt_iss1tw(vcpu)) { 497 /* 498 * Only a permission fault on a S1PTW should be 499 * considered as a write. Otherwise, page tables baked 500 * in a read-only memslot will result in an exception 501 * being delivered in the guest. 502 * 503 * The drawback is that we end-up faulting twice if the 504 * guest is using any of HW AF/DB: a translation fault 505 * to map the page containing the PT (read only at 506 * first), then a permission fault to allow the flags 507 * to be set. 508 */ 509 return kvm_vcpu_trap_is_permission_fault(vcpu); 510 } 511 512 if (kvm_vcpu_trap_is_iabt(vcpu)) 513 return false; 514 515 return kvm_vcpu_dabt_iswrite(vcpu); 516 } 517 518 static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu) 519 { 520 return __vcpu_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK; 521 } 522 523 static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu) 524 { 525 if (vcpu_mode_is_32bit(vcpu)) { 526 *vcpu_cpsr(vcpu) |= PSR_AA32_E_BIT; 527 } else { 528 enum vcpu_sysreg r; 529 u64 sctlr; 530 531 r = vcpu_has_nv(vcpu) ? SCTLR_EL2 : SCTLR_EL1; 532 533 sctlr = vcpu_read_sys_reg(vcpu, r); 534 sctlr |= SCTLR_ELx_EE; 535 vcpu_write_sys_reg(vcpu, sctlr, r); 536 } 537 } 538 539 static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu) 540 { 541 enum vcpu_sysreg r; 542 u64 bit; 543 544 if (vcpu_mode_is_32bit(vcpu)) 545 return !!(*vcpu_cpsr(vcpu) & PSR_AA32_E_BIT); 546 547 r = is_hyp_ctxt(vcpu) ? SCTLR_EL2 : SCTLR_EL1; 548 bit = vcpu_mode_priv(vcpu) ? SCTLR_ELx_EE : SCTLR_EL1_E0E; 549 550 return vcpu_read_sys_reg(vcpu, r) & bit; 551 } 552 553 static inline unsigned long vcpu_data_guest_to_host(struct kvm_vcpu *vcpu, 554 unsigned long data, 555 unsigned int len) 556 { 557 if (kvm_vcpu_is_be(vcpu)) { 558 switch (len) { 559 case 1: 560 return data & 0xff; 561 case 2: 562 return be16_to_cpu(data & 0xffff); 563 case 4: 564 return be32_to_cpu(data & 0xffffffff); 565 default: 566 return be64_to_cpu(data); 567 } 568 } else { 569 switch (len) { 570 case 1: 571 return data & 0xff; 572 case 2: 573 return le16_to_cpu(data & 0xffff); 574 case 4: 575 return le32_to_cpu(data & 0xffffffff); 576 default: 577 return le64_to_cpu(data); 578 } 579 } 580 581 return data; /* Leave LE untouched */ 582 } 583 584 static inline unsigned long vcpu_data_host_to_guest(struct kvm_vcpu *vcpu, 585 unsigned long data, 586 unsigned int len) 587 { 588 if (kvm_vcpu_is_be(vcpu)) { 589 switch (len) { 590 case 1: 591 return data & 0xff; 592 case 2: 593 return cpu_to_be16(data & 0xffff); 594 case 4: 595 return cpu_to_be32(data & 0xffffffff); 596 default: 597 return cpu_to_be64(data); 598 } 599 } else { 600 switch (len) { 601 case 1: 602 return data & 0xff; 603 case 2: 604 return cpu_to_le16(data & 0xffff); 605 case 4: 606 return cpu_to_le32(data & 0xffffffff); 607 default: 608 return cpu_to_le64(data); 609 } 610 } 611 612 return data; /* Leave LE untouched */ 613 } 614 615 static __always_inline void kvm_incr_pc(struct kvm_vcpu *vcpu) 616 { 617 WARN_ON(vcpu_get_flag(vcpu, PENDING_EXCEPTION)); 618 vcpu_set_flag(vcpu, INCREMENT_PC); 619 } 620 621 #define kvm_pend_exception(v, e) \ 622 do { \ 623 WARN_ON(vcpu_get_flag((v), INCREMENT_PC)); \ 624 vcpu_set_flag((v), PENDING_EXCEPTION); \ 625 vcpu_set_flag((v), e); \ 626 } while (0) 627 628 /* 629 * Returns a 'sanitised' view of CPTR_EL2, translating from nVHE to the VHE 630 * format if E2H isn't set. 631 */ 632 static inline u64 vcpu_sanitised_cptr_el2(const struct kvm_vcpu *vcpu) 633 { 634 u64 cptr = __vcpu_sys_reg(vcpu, CPTR_EL2); 635 636 if (!vcpu_el2_e2h_is_set(vcpu)) 637 cptr = translate_cptr_el2_to_cpacr_el1(cptr); 638 639 return cptr; 640 } 641 642 static inline bool ____cptr_xen_trap_enabled(const struct kvm_vcpu *vcpu, 643 unsigned int xen) 644 { 645 switch (xen) { 646 case 0b00: 647 case 0b10: 648 return true; 649 case 0b01: 650 return vcpu_el2_tge_is_set(vcpu) && !vcpu_is_el2(vcpu); 651 case 0b11: 652 default: 653 return false; 654 } 655 } 656 657 #define __guest_hyp_cptr_xen_trap_enabled(vcpu, xen) \ 658 (!vcpu_has_nv(vcpu) ? false : \ 659 ____cptr_xen_trap_enabled(vcpu, \ 660 SYS_FIELD_GET(CPACR_EL1, xen, \ 661 vcpu_sanitised_cptr_el2(vcpu)))) 662 663 static inline bool guest_hyp_fpsimd_traps_enabled(const struct kvm_vcpu *vcpu) 664 { 665 return __guest_hyp_cptr_xen_trap_enabled(vcpu, FPEN); 666 } 667 668 static inline bool guest_hyp_sve_traps_enabled(const struct kvm_vcpu *vcpu) 669 { 670 return __guest_hyp_cptr_xen_trap_enabled(vcpu, ZEN); 671 } 672 673 static inline void vcpu_set_hcrx(struct kvm_vcpu *vcpu) 674 { 675 struct kvm *kvm = vcpu->kvm; 676 677 if (cpus_have_final_cap(ARM64_HAS_HCX)) { 678 /* 679 * In general, all HCRX_EL2 bits are gated by a feature. 680 * The only reason we can set SMPME without checking any 681 * feature is that its effects are not directly observable 682 * from the guest. 683 */ 684 vcpu->arch.hcrx_el2 = HCRX_EL2_SMPME; 685 686 if (kvm_has_feat(kvm, ID_AA64ISAR2_EL1, MOPS, IMP)) 687 vcpu->arch.hcrx_el2 |= (HCRX_EL2_MSCEn | HCRX_EL2_MCE2); 688 689 if (kvm_has_tcr2(kvm)) 690 vcpu->arch.hcrx_el2 |= HCRX_EL2_TCR2En; 691 692 if (kvm_has_fpmr(kvm)) 693 vcpu->arch.hcrx_el2 |= HCRX_EL2_EnFPM; 694 695 if (kvm_has_sctlr2(kvm)) 696 vcpu->arch.hcrx_el2 |= HCRX_EL2_SCTLR2En; 697 } 698 } 699 #endif /* __ARM64_KVM_EMULATE_H__ */ 700