1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/kvm_emulate.h 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 */ 10 11 #ifndef __ARM64_KVM_EMULATE_H__ 12 #define __ARM64_KVM_EMULATE_H__ 13 14 #include <linux/kvm_host.h> 15 16 #include <asm/debug-monitors.h> 17 #include <asm/esr.h> 18 #include <asm/kvm_arm.h> 19 #include <asm/kvm_hyp.h> 20 #include <asm/ptrace.h> 21 #include <asm/cputype.h> 22 #include <asm/virt.h> 23 24 #define CURRENT_EL_SP_EL0_VECTOR 0x0 25 #define CURRENT_EL_SP_ELx_VECTOR 0x200 26 #define LOWER_EL_AArch64_VECTOR 0x400 27 #define LOWER_EL_AArch32_VECTOR 0x600 28 29 enum exception_type { 30 except_type_sync = 0, 31 except_type_irq = 0x80, 32 except_type_fiq = 0x100, 33 except_type_serror = 0x180, 34 }; 35 36 #define kvm_exception_type_names \ 37 { except_type_sync, "SYNC" }, \ 38 { except_type_irq, "IRQ" }, \ 39 { except_type_fiq, "FIQ" }, \ 40 { except_type_serror, "SERROR" } 41 42 bool kvm_condition_valid32(const struct kvm_vcpu *vcpu); 43 void kvm_skip_instr32(struct kvm_vcpu *vcpu); 44 45 void kvm_inject_undefined(struct kvm_vcpu *vcpu); 46 void kvm_inject_vabt(struct kvm_vcpu *vcpu); 47 void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr); 48 void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr); 49 void kvm_inject_size_fault(struct kvm_vcpu *vcpu); 50 51 void kvm_vcpu_wfi(struct kvm_vcpu *vcpu); 52 53 void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu); 54 int kvm_inject_nested_sync(struct kvm_vcpu *vcpu, u64 esr_el2); 55 int kvm_inject_nested_irq(struct kvm_vcpu *vcpu); 56 57 static inline bool vcpu_has_feature(const struct kvm_vcpu *vcpu, int feature) 58 { 59 return test_bit(feature, vcpu->kvm->arch.vcpu_features); 60 } 61 62 #if defined(__KVM_VHE_HYPERVISOR__) || defined(__KVM_NVHE_HYPERVISOR__) 63 static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu) 64 { 65 return !(vcpu->arch.hcr_el2 & HCR_RW); 66 } 67 #else 68 static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu) 69 { 70 return vcpu_has_feature(vcpu, KVM_ARM_VCPU_EL1_32BIT); 71 } 72 #endif 73 74 static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu) 75 { 76 vcpu->arch.hcr_el2 = HCR_GUEST_FLAGS; 77 if (has_vhe() || has_hvhe()) 78 vcpu->arch.hcr_el2 |= HCR_E2H; 79 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) { 80 /* route synchronous external abort exceptions to EL2 */ 81 vcpu->arch.hcr_el2 |= HCR_TEA; 82 /* trap error record accesses */ 83 vcpu->arch.hcr_el2 |= HCR_TERR; 84 } 85 86 if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) { 87 vcpu->arch.hcr_el2 |= HCR_FWB; 88 } else { 89 /* 90 * For non-FWB CPUs, we trap VM ops (HCR_EL2.TVM) until M+C 91 * get set in SCTLR_EL1 such that we can detect when the guest 92 * MMU gets turned on and do the necessary cache maintenance 93 * then. 94 */ 95 vcpu->arch.hcr_el2 |= HCR_TVM; 96 } 97 98 if (cpus_have_final_cap(ARM64_HAS_EVT) && 99 !cpus_have_final_cap(ARM64_MISMATCHED_CACHE_TYPE)) 100 vcpu->arch.hcr_el2 |= HCR_TID4; 101 else 102 vcpu->arch.hcr_el2 |= HCR_TID2; 103 104 if (vcpu_el1_is_32bit(vcpu)) 105 vcpu->arch.hcr_el2 &= ~HCR_RW; 106 107 if (kvm_has_mte(vcpu->kvm)) 108 vcpu->arch.hcr_el2 |= HCR_ATA; 109 } 110 111 static inline unsigned long *vcpu_hcr(struct kvm_vcpu *vcpu) 112 { 113 return (unsigned long *)&vcpu->arch.hcr_el2; 114 } 115 116 static inline void vcpu_clear_wfx_traps(struct kvm_vcpu *vcpu) 117 { 118 vcpu->arch.hcr_el2 &= ~HCR_TWE; 119 if (atomic_read(&vcpu->arch.vgic_cpu.vgic_v3.its_vpe.vlpi_count) || 120 vcpu->kvm->arch.vgic.nassgireq) 121 vcpu->arch.hcr_el2 &= ~HCR_TWI; 122 else 123 vcpu->arch.hcr_el2 |= HCR_TWI; 124 } 125 126 static inline void vcpu_set_wfx_traps(struct kvm_vcpu *vcpu) 127 { 128 vcpu->arch.hcr_el2 |= HCR_TWE; 129 vcpu->arch.hcr_el2 |= HCR_TWI; 130 } 131 132 static inline void vcpu_ptrauth_enable(struct kvm_vcpu *vcpu) 133 { 134 vcpu->arch.hcr_el2 |= (HCR_API | HCR_APK); 135 } 136 137 static inline void vcpu_ptrauth_disable(struct kvm_vcpu *vcpu) 138 { 139 vcpu->arch.hcr_el2 &= ~(HCR_API | HCR_APK); 140 } 141 142 static inline unsigned long vcpu_get_vsesr(struct kvm_vcpu *vcpu) 143 { 144 return vcpu->arch.vsesr_el2; 145 } 146 147 static inline void vcpu_set_vsesr(struct kvm_vcpu *vcpu, u64 vsesr) 148 { 149 vcpu->arch.vsesr_el2 = vsesr; 150 } 151 152 static __always_inline unsigned long *vcpu_pc(const struct kvm_vcpu *vcpu) 153 { 154 return (unsigned long *)&vcpu_gp_regs(vcpu)->pc; 155 } 156 157 static __always_inline unsigned long *vcpu_cpsr(const struct kvm_vcpu *vcpu) 158 { 159 return (unsigned long *)&vcpu_gp_regs(vcpu)->pstate; 160 } 161 162 static __always_inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu) 163 { 164 return !!(*vcpu_cpsr(vcpu) & PSR_MODE32_BIT); 165 } 166 167 static __always_inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu) 168 { 169 if (vcpu_mode_is_32bit(vcpu)) 170 return kvm_condition_valid32(vcpu); 171 172 return true; 173 } 174 175 static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu) 176 { 177 *vcpu_cpsr(vcpu) |= PSR_AA32_T_BIT; 178 } 179 180 /* 181 * vcpu_get_reg and vcpu_set_reg should always be passed a register number 182 * coming from a read of ESR_EL2. Otherwise, it may give the wrong result on 183 * AArch32 with banked registers. 184 */ 185 static __always_inline unsigned long vcpu_get_reg(const struct kvm_vcpu *vcpu, 186 u8 reg_num) 187 { 188 return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num]; 189 } 190 191 static __always_inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num, 192 unsigned long val) 193 { 194 if (reg_num != 31) 195 vcpu_gp_regs(vcpu)->regs[reg_num] = val; 196 } 197 198 static inline bool vcpu_is_el2_ctxt(const struct kvm_cpu_context *ctxt) 199 { 200 switch (ctxt->regs.pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) { 201 case PSR_MODE_EL2h: 202 case PSR_MODE_EL2t: 203 return true; 204 default: 205 return false; 206 } 207 } 208 209 static inline bool vcpu_is_el2(const struct kvm_vcpu *vcpu) 210 { 211 return vcpu_is_el2_ctxt(&vcpu->arch.ctxt); 212 } 213 214 static inline bool __vcpu_el2_e2h_is_set(const struct kvm_cpu_context *ctxt) 215 { 216 return ctxt_sys_reg(ctxt, HCR_EL2) & HCR_E2H; 217 } 218 219 static inline bool vcpu_el2_e2h_is_set(const struct kvm_vcpu *vcpu) 220 { 221 return __vcpu_el2_e2h_is_set(&vcpu->arch.ctxt); 222 } 223 224 static inline bool __vcpu_el2_tge_is_set(const struct kvm_cpu_context *ctxt) 225 { 226 return ctxt_sys_reg(ctxt, HCR_EL2) & HCR_TGE; 227 } 228 229 static inline bool vcpu_el2_tge_is_set(const struct kvm_vcpu *vcpu) 230 { 231 return __vcpu_el2_tge_is_set(&vcpu->arch.ctxt); 232 } 233 234 static inline bool __is_hyp_ctxt(const struct kvm_cpu_context *ctxt) 235 { 236 /* 237 * We are in a hypervisor context if the vcpu mode is EL2 or 238 * E2H and TGE bits are set. The latter means we are in the user space 239 * of the VHE kernel. ARMv8.1 ARM describes this as 'InHost' 240 * 241 * Note that the HCR_EL2.{E2H,TGE}={0,1} isn't really handled in the 242 * rest of the KVM code, and will result in a misbehaving guest. 243 */ 244 return vcpu_is_el2_ctxt(ctxt) || 245 (__vcpu_el2_e2h_is_set(ctxt) && __vcpu_el2_tge_is_set(ctxt)) || 246 __vcpu_el2_tge_is_set(ctxt); 247 } 248 249 static inline bool is_hyp_ctxt(const struct kvm_vcpu *vcpu) 250 { 251 return __is_hyp_ctxt(&vcpu->arch.ctxt); 252 } 253 254 /* 255 * The layout of SPSR for an AArch32 state is different when observed from an 256 * AArch64 SPSR_ELx or an AArch32 SPSR_*. This function generates the AArch32 257 * view given an AArch64 view. 258 * 259 * In ARM DDI 0487E.a see: 260 * 261 * - The AArch64 view (SPSR_EL2) in section C5.2.18, page C5-426 262 * - The AArch32 view (SPSR_abt) in section G8.2.126, page G8-6256 263 * - The AArch32 view (SPSR_und) in section G8.2.132, page G8-6280 264 * 265 * Which show the following differences: 266 * 267 * | Bit | AA64 | AA32 | Notes | 268 * +-----+------+------+-----------------------------| 269 * | 24 | DIT | J | J is RES0 in ARMv8 | 270 * | 21 | SS | DIT | SS doesn't exist in AArch32 | 271 * 272 * ... and all other bits are (currently) common. 273 */ 274 static inline unsigned long host_spsr_to_spsr32(unsigned long spsr) 275 { 276 const unsigned long overlap = BIT(24) | BIT(21); 277 unsigned long dit = !!(spsr & PSR_AA32_DIT_BIT); 278 279 spsr &= ~overlap; 280 281 spsr |= dit << 21; 282 283 return spsr; 284 } 285 286 static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu) 287 { 288 u32 mode; 289 290 if (vcpu_mode_is_32bit(vcpu)) { 291 mode = *vcpu_cpsr(vcpu) & PSR_AA32_MODE_MASK; 292 return mode > PSR_AA32_MODE_USR; 293 } 294 295 mode = *vcpu_cpsr(vcpu) & PSR_MODE_MASK; 296 297 return mode != PSR_MODE_EL0t; 298 } 299 300 static __always_inline u64 kvm_vcpu_get_esr(const struct kvm_vcpu *vcpu) 301 { 302 return vcpu->arch.fault.esr_el2; 303 } 304 305 static __always_inline int kvm_vcpu_get_condition(const struct kvm_vcpu *vcpu) 306 { 307 u64 esr = kvm_vcpu_get_esr(vcpu); 308 309 if (esr & ESR_ELx_CV) 310 return (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT; 311 312 return -1; 313 } 314 315 static __always_inline unsigned long kvm_vcpu_get_hfar(const struct kvm_vcpu *vcpu) 316 { 317 return vcpu->arch.fault.far_el2; 318 } 319 320 static __always_inline phys_addr_t kvm_vcpu_get_fault_ipa(const struct kvm_vcpu *vcpu) 321 { 322 return ((phys_addr_t)vcpu->arch.fault.hpfar_el2 & HPFAR_MASK) << 8; 323 } 324 325 static inline u64 kvm_vcpu_get_disr(const struct kvm_vcpu *vcpu) 326 { 327 return vcpu->arch.fault.disr_el1; 328 } 329 330 static inline u32 kvm_vcpu_hvc_get_imm(const struct kvm_vcpu *vcpu) 331 { 332 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_xVC_IMM_MASK; 333 } 334 335 static __always_inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu) 336 { 337 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_ISV); 338 } 339 340 static inline unsigned long kvm_vcpu_dabt_iss_nisv_sanitized(const struct kvm_vcpu *vcpu) 341 { 342 return kvm_vcpu_get_esr(vcpu) & (ESR_ELx_CM | ESR_ELx_WNR | ESR_ELx_FSC); 343 } 344 345 static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu) 346 { 347 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_SSE); 348 } 349 350 static inline bool kvm_vcpu_dabt_issf(const struct kvm_vcpu *vcpu) 351 { 352 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_SF); 353 } 354 355 static __always_inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu) 356 { 357 return (kvm_vcpu_get_esr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT; 358 } 359 360 static __always_inline bool kvm_vcpu_abt_iss1tw(const struct kvm_vcpu *vcpu) 361 { 362 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_S1PTW); 363 } 364 365 /* Always check for S1PTW *before* using this. */ 366 static __always_inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu) 367 { 368 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_WNR; 369 } 370 371 static inline bool kvm_vcpu_dabt_is_cm(const struct kvm_vcpu *vcpu) 372 { 373 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_CM); 374 } 375 376 static __always_inline unsigned int kvm_vcpu_dabt_get_as(const struct kvm_vcpu *vcpu) 377 { 378 return 1 << ((kvm_vcpu_get_esr(vcpu) & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT); 379 } 380 381 /* This one is not specific to Data Abort */ 382 static __always_inline bool kvm_vcpu_trap_il_is32bit(const struct kvm_vcpu *vcpu) 383 { 384 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_IL); 385 } 386 387 static __always_inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu) 388 { 389 return ESR_ELx_EC(kvm_vcpu_get_esr(vcpu)); 390 } 391 392 static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu) 393 { 394 return kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_IABT_LOW; 395 } 396 397 static inline bool kvm_vcpu_trap_is_exec_fault(const struct kvm_vcpu *vcpu) 398 { 399 return kvm_vcpu_trap_is_iabt(vcpu) && !kvm_vcpu_abt_iss1tw(vcpu); 400 } 401 402 static __always_inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu) 403 { 404 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC; 405 } 406 407 static __always_inline u8 kvm_vcpu_trap_get_fault_type(const struct kvm_vcpu *vcpu) 408 { 409 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC_TYPE; 410 } 411 412 static __always_inline u8 kvm_vcpu_trap_get_fault_level(const struct kvm_vcpu *vcpu) 413 { 414 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC_LEVEL; 415 } 416 417 static __always_inline bool kvm_vcpu_abt_issea(const struct kvm_vcpu *vcpu) 418 { 419 switch (kvm_vcpu_trap_get_fault(vcpu)) { 420 case ESR_ELx_FSC_EXTABT: 421 case ESR_ELx_FSC_SEA_TTW0: 422 case ESR_ELx_FSC_SEA_TTW1: 423 case ESR_ELx_FSC_SEA_TTW2: 424 case ESR_ELx_FSC_SEA_TTW3: 425 case ESR_ELx_FSC_SECC: 426 case ESR_ELx_FSC_SECC_TTW0: 427 case ESR_ELx_FSC_SECC_TTW1: 428 case ESR_ELx_FSC_SECC_TTW2: 429 case ESR_ELx_FSC_SECC_TTW3: 430 return true; 431 default: 432 return false; 433 } 434 } 435 436 static __always_inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu) 437 { 438 u64 esr = kvm_vcpu_get_esr(vcpu); 439 return ESR_ELx_SYS64_ISS_RT(esr); 440 } 441 442 static inline bool kvm_is_write_fault(struct kvm_vcpu *vcpu) 443 { 444 if (kvm_vcpu_abt_iss1tw(vcpu)) { 445 /* 446 * Only a permission fault on a S1PTW should be 447 * considered as a write. Otherwise, page tables baked 448 * in a read-only memslot will result in an exception 449 * being delivered in the guest. 450 * 451 * The drawback is that we end-up faulting twice if the 452 * guest is using any of HW AF/DB: a translation fault 453 * to map the page containing the PT (read only at 454 * first), then a permission fault to allow the flags 455 * to be set. 456 */ 457 switch (kvm_vcpu_trap_get_fault_type(vcpu)) { 458 case ESR_ELx_FSC_PERM: 459 return true; 460 default: 461 return false; 462 } 463 } 464 465 if (kvm_vcpu_trap_is_iabt(vcpu)) 466 return false; 467 468 return kvm_vcpu_dabt_iswrite(vcpu); 469 } 470 471 static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu) 472 { 473 return __vcpu_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK; 474 } 475 476 static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu) 477 { 478 if (vcpu_mode_is_32bit(vcpu)) { 479 *vcpu_cpsr(vcpu) |= PSR_AA32_E_BIT; 480 } else { 481 u64 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1); 482 sctlr |= SCTLR_ELx_EE; 483 vcpu_write_sys_reg(vcpu, sctlr, SCTLR_EL1); 484 } 485 } 486 487 static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu) 488 { 489 if (vcpu_mode_is_32bit(vcpu)) 490 return !!(*vcpu_cpsr(vcpu) & PSR_AA32_E_BIT); 491 492 if (vcpu_mode_priv(vcpu)) 493 return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & SCTLR_ELx_EE); 494 else 495 return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & SCTLR_EL1_E0E); 496 } 497 498 static inline unsigned long vcpu_data_guest_to_host(struct kvm_vcpu *vcpu, 499 unsigned long data, 500 unsigned int len) 501 { 502 if (kvm_vcpu_is_be(vcpu)) { 503 switch (len) { 504 case 1: 505 return data & 0xff; 506 case 2: 507 return be16_to_cpu(data & 0xffff); 508 case 4: 509 return be32_to_cpu(data & 0xffffffff); 510 default: 511 return be64_to_cpu(data); 512 } 513 } else { 514 switch (len) { 515 case 1: 516 return data & 0xff; 517 case 2: 518 return le16_to_cpu(data & 0xffff); 519 case 4: 520 return le32_to_cpu(data & 0xffffffff); 521 default: 522 return le64_to_cpu(data); 523 } 524 } 525 526 return data; /* Leave LE untouched */ 527 } 528 529 static inline unsigned long vcpu_data_host_to_guest(struct kvm_vcpu *vcpu, 530 unsigned long data, 531 unsigned int len) 532 { 533 if (kvm_vcpu_is_be(vcpu)) { 534 switch (len) { 535 case 1: 536 return data & 0xff; 537 case 2: 538 return cpu_to_be16(data & 0xffff); 539 case 4: 540 return cpu_to_be32(data & 0xffffffff); 541 default: 542 return cpu_to_be64(data); 543 } 544 } else { 545 switch (len) { 546 case 1: 547 return data & 0xff; 548 case 2: 549 return cpu_to_le16(data & 0xffff); 550 case 4: 551 return cpu_to_le32(data & 0xffffffff); 552 default: 553 return cpu_to_le64(data); 554 } 555 } 556 557 return data; /* Leave LE untouched */ 558 } 559 560 static __always_inline void kvm_incr_pc(struct kvm_vcpu *vcpu) 561 { 562 WARN_ON(vcpu_get_flag(vcpu, PENDING_EXCEPTION)); 563 vcpu_set_flag(vcpu, INCREMENT_PC); 564 } 565 566 #define kvm_pend_exception(v, e) \ 567 do { \ 568 WARN_ON(vcpu_get_flag((v), INCREMENT_PC)); \ 569 vcpu_set_flag((v), PENDING_EXCEPTION); \ 570 vcpu_set_flag((v), e); \ 571 } while (0) 572 573 static __always_inline void kvm_write_cptr_el2(u64 val) 574 { 575 if (has_vhe() || has_hvhe()) 576 write_sysreg(val, cpacr_el1); 577 else 578 write_sysreg(val, cptr_el2); 579 } 580 581 static __always_inline u64 kvm_get_reset_cptr_el2(struct kvm_vcpu *vcpu) 582 { 583 u64 val; 584 585 if (has_vhe()) { 586 val = (CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN | 587 CPACR_EL1_ZEN_EL1EN); 588 if (cpus_have_final_cap(ARM64_SME)) 589 val |= CPACR_EL1_SMEN_EL1EN; 590 } else if (has_hvhe()) { 591 val = (CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN); 592 593 if (!vcpu_has_sve(vcpu) || 594 (vcpu->arch.fp_state != FP_STATE_GUEST_OWNED)) 595 val |= CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN; 596 if (cpus_have_final_cap(ARM64_SME)) 597 val |= CPACR_EL1_SMEN_EL1EN | CPACR_EL1_SMEN_EL0EN; 598 } else { 599 val = CPTR_NVHE_EL2_RES1; 600 601 if (vcpu_has_sve(vcpu) && 602 (vcpu->arch.fp_state == FP_STATE_GUEST_OWNED)) 603 val |= CPTR_EL2_TZ; 604 if (cpus_have_final_cap(ARM64_SME)) 605 val &= ~CPTR_EL2_TSM; 606 } 607 608 return val; 609 } 610 611 static __always_inline void kvm_reset_cptr_el2(struct kvm_vcpu *vcpu) 612 { 613 u64 val = kvm_get_reset_cptr_el2(vcpu); 614 615 kvm_write_cptr_el2(val); 616 } 617 #endif /* __ARM64_KVM_EMULATE_H__ */ 618