1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/kvm_emulate.h 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 */ 10 11 #ifndef __ARM64_KVM_EMULATE_H__ 12 #define __ARM64_KVM_EMULATE_H__ 13 14 #include <linux/bitfield.h> 15 #include <linux/kvm_host.h> 16 17 #include <asm/debug-monitors.h> 18 #include <asm/esr.h> 19 #include <asm/kvm_arm.h> 20 #include <asm/kvm_hyp.h> 21 #include <asm/kvm_nested.h> 22 #include <asm/ptrace.h> 23 #include <asm/cputype.h> 24 #include <asm/virt.h> 25 26 #define CURRENT_EL_SP_EL0_VECTOR 0x0 27 #define CURRENT_EL_SP_ELx_VECTOR 0x200 28 #define LOWER_EL_AArch64_VECTOR 0x400 29 #define LOWER_EL_AArch32_VECTOR 0x600 30 31 enum exception_type { 32 except_type_sync = 0, 33 except_type_irq = 0x80, 34 except_type_fiq = 0x100, 35 except_type_serror = 0x180, 36 }; 37 38 #define kvm_exception_type_names \ 39 { except_type_sync, "SYNC" }, \ 40 { except_type_irq, "IRQ" }, \ 41 { except_type_fiq, "FIQ" }, \ 42 { except_type_serror, "SERROR" } 43 44 bool kvm_condition_valid32(const struct kvm_vcpu *vcpu); 45 void kvm_skip_instr32(struct kvm_vcpu *vcpu); 46 47 void kvm_inject_undefined(struct kvm_vcpu *vcpu); 48 void kvm_inject_vabt(struct kvm_vcpu *vcpu); 49 void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr); 50 void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr); 51 void kvm_inject_size_fault(struct kvm_vcpu *vcpu); 52 53 void kvm_vcpu_wfi(struct kvm_vcpu *vcpu); 54 55 void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu); 56 int kvm_inject_nested_sync(struct kvm_vcpu *vcpu, u64 esr_el2); 57 int kvm_inject_nested_irq(struct kvm_vcpu *vcpu); 58 59 static inline void kvm_inject_nested_sve_trap(struct kvm_vcpu *vcpu) 60 { 61 u64 esr = FIELD_PREP(ESR_ELx_EC_MASK, ESR_ELx_EC_SVE) | 62 ESR_ELx_IL; 63 64 kvm_inject_nested_sync(vcpu, esr); 65 } 66 67 #if defined(__KVM_VHE_HYPERVISOR__) || defined(__KVM_NVHE_HYPERVISOR__) 68 static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu) 69 { 70 return !(vcpu->arch.hcr_el2 & HCR_RW); 71 } 72 #else 73 static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu) 74 { 75 return vcpu_has_feature(vcpu, KVM_ARM_VCPU_EL1_32BIT); 76 } 77 #endif 78 79 static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu) 80 { 81 vcpu->arch.hcr_el2 = HCR_GUEST_FLAGS; 82 if (has_vhe() || has_hvhe()) 83 vcpu->arch.hcr_el2 |= HCR_E2H; 84 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) { 85 /* route synchronous external abort exceptions to EL2 */ 86 vcpu->arch.hcr_el2 |= HCR_TEA; 87 /* trap error record accesses */ 88 vcpu->arch.hcr_el2 |= HCR_TERR; 89 } 90 91 if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) { 92 vcpu->arch.hcr_el2 |= HCR_FWB; 93 } else { 94 /* 95 * For non-FWB CPUs, we trap VM ops (HCR_EL2.TVM) until M+C 96 * get set in SCTLR_EL1 such that we can detect when the guest 97 * MMU gets turned on and do the necessary cache maintenance 98 * then. 99 */ 100 vcpu->arch.hcr_el2 |= HCR_TVM; 101 } 102 103 if (cpus_have_final_cap(ARM64_HAS_EVT) && 104 !cpus_have_final_cap(ARM64_MISMATCHED_CACHE_TYPE)) 105 vcpu->arch.hcr_el2 |= HCR_TID4; 106 else 107 vcpu->arch.hcr_el2 |= HCR_TID2; 108 109 if (vcpu_el1_is_32bit(vcpu)) 110 vcpu->arch.hcr_el2 &= ~HCR_RW; 111 112 if (kvm_has_mte(vcpu->kvm)) 113 vcpu->arch.hcr_el2 |= HCR_ATA; 114 } 115 116 static inline unsigned long *vcpu_hcr(struct kvm_vcpu *vcpu) 117 { 118 return (unsigned long *)&vcpu->arch.hcr_el2; 119 } 120 121 static inline void vcpu_clear_wfx_traps(struct kvm_vcpu *vcpu) 122 { 123 vcpu->arch.hcr_el2 &= ~HCR_TWE; 124 if (atomic_read(&vcpu->arch.vgic_cpu.vgic_v3.its_vpe.vlpi_count) || 125 vcpu->kvm->arch.vgic.nassgireq) 126 vcpu->arch.hcr_el2 &= ~HCR_TWI; 127 else 128 vcpu->arch.hcr_el2 |= HCR_TWI; 129 } 130 131 static inline void vcpu_set_wfx_traps(struct kvm_vcpu *vcpu) 132 { 133 vcpu->arch.hcr_el2 |= HCR_TWE; 134 vcpu->arch.hcr_el2 |= HCR_TWI; 135 } 136 137 static inline unsigned long vcpu_get_vsesr(struct kvm_vcpu *vcpu) 138 { 139 return vcpu->arch.vsesr_el2; 140 } 141 142 static inline void vcpu_set_vsesr(struct kvm_vcpu *vcpu, u64 vsesr) 143 { 144 vcpu->arch.vsesr_el2 = vsesr; 145 } 146 147 static __always_inline unsigned long *vcpu_pc(const struct kvm_vcpu *vcpu) 148 { 149 return (unsigned long *)&vcpu_gp_regs(vcpu)->pc; 150 } 151 152 static __always_inline unsigned long *vcpu_cpsr(const struct kvm_vcpu *vcpu) 153 { 154 return (unsigned long *)&vcpu_gp_regs(vcpu)->pstate; 155 } 156 157 static __always_inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu) 158 { 159 return !!(*vcpu_cpsr(vcpu) & PSR_MODE32_BIT); 160 } 161 162 static __always_inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu) 163 { 164 if (vcpu_mode_is_32bit(vcpu)) 165 return kvm_condition_valid32(vcpu); 166 167 return true; 168 } 169 170 static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu) 171 { 172 *vcpu_cpsr(vcpu) |= PSR_AA32_T_BIT; 173 } 174 175 /* 176 * vcpu_get_reg and vcpu_set_reg should always be passed a register number 177 * coming from a read of ESR_EL2. Otherwise, it may give the wrong result on 178 * AArch32 with banked registers. 179 */ 180 static __always_inline unsigned long vcpu_get_reg(const struct kvm_vcpu *vcpu, 181 u8 reg_num) 182 { 183 return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num]; 184 } 185 186 static __always_inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num, 187 unsigned long val) 188 { 189 if (reg_num != 31) 190 vcpu_gp_regs(vcpu)->regs[reg_num] = val; 191 } 192 193 static inline bool vcpu_is_el2_ctxt(const struct kvm_cpu_context *ctxt) 194 { 195 switch (ctxt->regs.pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) { 196 case PSR_MODE_EL2h: 197 case PSR_MODE_EL2t: 198 return true; 199 default: 200 return false; 201 } 202 } 203 204 static inline bool vcpu_is_el2(const struct kvm_vcpu *vcpu) 205 { 206 return vcpu_is_el2_ctxt(&vcpu->arch.ctxt); 207 } 208 209 static inline bool __vcpu_el2_e2h_is_set(const struct kvm_cpu_context *ctxt) 210 { 211 return (!cpus_have_final_cap(ARM64_HAS_HCR_NV1) || 212 (ctxt_sys_reg(ctxt, HCR_EL2) & HCR_E2H)); 213 } 214 215 static inline bool vcpu_el2_e2h_is_set(const struct kvm_vcpu *vcpu) 216 { 217 return __vcpu_el2_e2h_is_set(&vcpu->arch.ctxt); 218 } 219 220 static inline bool __vcpu_el2_tge_is_set(const struct kvm_cpu_context *ctxt) 221 { 222 return ctxt_sys_reg(ctxt, HCR_EL2) & HCR_TGE; 223 } 224 225 static inline bool vcpu_el2_tge_is_set(const struct kvm_vcpu *vcpu) 226 { 227 return __vcpu_el2_tge_is_set(&vcpu->arch.ctxt); 228 } 229 230 static inline bool __is_hyp_ctxt(const struct kvm_cpu_context *ctxt) 231 { 232 /* 233 * We are in a hypervisor context if the vcpu mode is EL2 or 234 * E2H and TGE bits are set. The latter means we are in the user space 235 * of the VHE kernel. ARMv8.1 ARM describes this as 'InHost' 236 * 237 * Note that the HCR_EL2.{E2H,TGE}={0,1} isn't really handled in the 238 * rest of the KVM code, and will result in a misbehaving guest. 239 */ 240 return vcpu_is_el2_ctxt(ctxt) || 241 (__vcpu_el2_e2h_is_set(ctxt) && __vcpu_el2_tge_is_set(ctxt)) || 242 __vcpu_el2_tge_is_set(ctxt); 243 } 244 245 static inline bool is_hyp_ctxt(const struct kvm_vcpu *vcpu) 246 { 247 return vcpu_has_nv(vcpu) && __is_hyp_ctxt(&vcpu->arch.ctxt); 248 } 249 250 /* 251 * The layout of SPSR for an AArch32 state is different when observed from an 252 * AArch64 SPSR_ELx or an AArch32 SPSR_*. This function generates the AArch32 253 * view given an AArch64 view. 254 * 255 * In ARM DDI 0487E.a see: 256 * 257 * - The AArch64 view (SPSR_EL2) in section C5.2.18, page C5-426 258 * - The AArch32 view (SPSR_abt) in section G8.2.126, page G8-6256 259 * - The AArch32 view (SPSR_und) in section G8.2.132, page G8-6280 260 * 261 * Which show the following differences: 262 * 263 * | Bit | AA64 | AA32 | Notes | 264 * +-----+------+------+-----------------------------| 265 * | 24 | DIT | J | J is RES0 in ARMv8 | 266 * | 21 | SS | DIT | SS doesn't exist in AArch32 | 267 * 268 * ... and all other bits are (currently) common. 269 */ 270 static inline unsigned long host_spsr_to_spsr32(unsigned long spsr) 271 { 272 const unsigned long overlap = BIT(24) | BIT(21); 273 unsigned long dit = !!(spsr & PSR_AA32_DIT_BIT); 274 275 spsr &= ~overlap; 276 277 spsr |= dit << 21; 278 279 return spsr; 280 } 281 282 static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu) 283 { 284 u32 mode; 285 286 if (vcpu_mode_is_32bit(vcpu)) { 287 mode = *vcpu_cpsr(vcpu) & PSR_AA32_MODE_MASK; 288 return mode > PSR_AA32_MODE_USR; 289 } 290 291 mode = *vcpu_cpsr(vcpu) & PSR_MODE_MASK; 292 293 return mode != PSR_MODE_EL0t; 294 } 295 296 static __always_inline u64 kvm_vcpu_get_esr(const struct kvm_vcpu *vcpu) 297 { 298 return vcpu->arch.fault.esr_el2; 299 } 300 301 static __always_inline int kvm_vcpu_get_condition(const struct kvm_vcpu *vcpu) 302 { 303 u64 esr = kvm_vcpu_get_esr(vcpu); 304 305 if (esr & ESR_ELx_CV) 306 return (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT; 307 308 return -1; 309 } 310 311 static __always_inline unsigned long kvm_vcpu_get_hfar(const struct kvm_vcpu *vcpu) 312 { 313 return vcpu->arch.fault.far_el2; 314 } 315 316 static __always_inline phys_addr_t kvm_vcpu_get_fault_ipa(const struct kvm_vcpu *vcpu) 317 { 318 return ((phys_addr_t)vcpu->arch.fault.hpfar_el2 & HPFAR_MASK) << 8; 319 } 320 321 static inline u64 kvm_vcpu_get_disr(const struct kvm_vcpu *vcpu) 322 { 323 return vcpu->arch.fault.disr_el1; 324 } 325 326 static inline u32 kvm_vcpu_hvc_get_imm(const struct kvm_vcpu *vcpu) 327 { 328 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_xVC_IMM_MASK; 329 } 330 331 static __always_inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu) 332 { 333 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_ISV); 334 } 335 336 static inline unsigned long kvm_vcpu_dabt_iss_nisv_sanitized(const struct kvm_vcpu *vcpu) 337 { 338 return kvm_vcpu_get_esr(vcpu) & (ESR_ELx_CM | ESR_ELx_WNR | ESR_ELx_FSC); 339 } 340 341 static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu) 342 { 343 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_SSE); 344 } 345 346 static inline bool kvm_vcpu_dabt_issf(const struct kvm_vcpu *vcpu) 347 { 348 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_SF); 349 } 350 351 static __always_inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu) 352 { 353 return (kvm_vcpu_get_esr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT; 354 } 355 356 static __always_inline bool kvm_vcpu_abt_iss1tw(const struct kvm_vcpu *vcpu) 357 { 358 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_S1PTW); 359 } 360 361 /* Always check for S1PTW *before* using this. */ 362 static __always_inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu) 363 { 364 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_WNR; 365 } 366 367 static inline bool kvm_vcpu_dabt_is_cm(const struct kvm_vcpu *vcpu) 368 { 369 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_CM); 370 } 371 372 static __always_inline unsigned int kvm_vcpu_dabt_get_as(const struct kvm_vcpu *vcpu) 373 { 374 return 1 << ((kvm_vcpu_get_esr(vcpu) & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT); 375 } 376 377 /* This one is not specific to Data Abort */ 378 static __always_inline bool kvm_vcpu_trap_il_is32bit(const struct kvm_vcpu *vcpu) 379 { 380 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_IL); 381 } 382 383 static __always_inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu) 384 { 385 return ESR_ELx_EC(kvm_vcpu_get_esr(vcpu)); 386 } 387 388 static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu) 389 { 390 return kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_IABT_LOW; 391 } 392 393 static inline bool kvm_vcpu_trap_is_exec_fault(const struct kvm_vcpu *vcpu) 394 { 395 return kvm_vcpu_trap_is_iabt(vcpu) && !kvm_vcpu_abt_iss1tw(vcpu); 396 } 397 398 static __always_inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu) 399 { 400 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC; 401 } 402 403 static inline 404 bool kvm_vcpu_trap_is_permission_fault(const struct kvm_vcpu *vcpu) 405 { 406 return esr_fsc_is_permission_fault(kvm_vcpu_get_esr(vcpu)); 407 } 408 409 static inline 410 bool kvm_vcpu_trap_is_translation_fault(const struct kvm_vcpu *vcpu) 411 { 412 return esr_fsc_is_translation_fault(kvm_vcpu_get_esr(vcpu)); 413 } 414 415 static inline 416 u64 kvm_vcpu_trap_get_perm_fault_granule(const struct kvm_vcpu *vcpu) 417 { 418 unsigned long esr = kvm_vcpu_get_esr(vcpu); 419 420 BUG_ON(!esr_fsc_is_permission_fault(esr)); 421 return BIT(ARM64_HW_PGTABLE_LEVEL_SHIFT(esr & ESR_ELx_FSC_LEVEL)); 422 } 423 424 static __always_inline bool kvm_vcpu_abt_issea(const struct kvm_vcpu *vcpu) 425 { 426 switch (kvm_vcpu_trap_get_fault(vcpu)) { 427 case ESR_ELx_FSC_EXTABT: 428 case ESR_ELx_FSC_SEA_TTW(-1) ... ESR_ELx_FSC_SEA_TTW(3): 429 case ESR_ELx_FSC_SECC: 430 case ESR_ELx_FSC_SECC_TTW(-1) ... ESR_ELx_FSC_SECC_TTW(3): 431 return true; 432 default: 433 return false; 434 } 435 } 436 437 static __always_inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu) 438 { 439 u64 esr = kvm_vcpu_get_esr(vcpu); 440 return ESR_ELx_SYS64_ISS_RT(esr); 441 } 442 443 static inline bool kvm_is_write_fault(struct kvm_vcpu *vcpu) 444 { 445 if (kvm_vcpu_abt_iss1tw(vcpu)) { 446 /* 447 * Only a permission fault on a S1PTW should be 448 * considered as a write. Otherwise, page tables baked 449 * in a read-only memslot will result in an exception 450 * being delivered in the guest. 451 * 452 * The drawback is that we end-up faulting twice if the 453 * guest is using any of HW AF/DB: a translation fault 454 * to map the page containing the PT (read only at 455 * first), then a permission fault to allow the flags 456 * to be set. 457 */ 458 return kvm_vcpu_trap_is_permission_fault(vcpu); 459 } 460 461 if (kvm_vcpu_trap_is_iabt(vcpu)) 462 return false; 463 464 return kvm_vcpu_dabt_iswrite(vcpu); 465 } 466 467 static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu) 468 { 469 return __vcpu_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK; 470 } 471 472 static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu) 473 { 474 if (vcpu_mode_is_32bit(vcpu)) { 475 *vcpu_cpsr(vcpu) |= PSR_AA32_E_BIT; 476 } else { 477 u64 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1); 478 sctlr |= SCTLR_ELx_EE; 479 vcpu_write_sys_reg(vcpu, sctlr, SCTLR_EL1); 480 } 481 } 482 483 static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu) 484 { 485 if (vcpu_mode_is_32bit(vcpu)) 486 return !!(*vcpu_cpsr(vcpu) & PSR_AA32_E_BIT); 487 488 if (vcpu_mode_priv(vcpu)) 489 return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & SCTLR_ELx_EE); 490 else 491 return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & SCTLR_EL1_E0E); 492 } 493 494 static inline unsigned long vcpu_data_guest_to_host(struct kvm_vcpu *vcpu, 495 unsigned long data, 496 unsigned int len) 497 { 498 if (kvm_vcpu_is_be(vcpu)) { 499 switch (len) { 500 case 1: 501 return data & 0xff; 502 case 2: 503 return be16_to_cpu(data & 0xffff); 504 case 4: 505 return be32_to_cpu(data & 0xffffffff); 506 default: 507 return be64_to_cpu(data); 508 } 509 } else { 510 switch (len) { 511 case 1: 512 return data & 0xff; 513 case 2: 514 return le16_to_cpu(data & 0xffff); 515 case 4: 516 return le32_to_cpu(data & 0xffffffff); 517 default: 518 return le64_to_cpu(data); 519 } 520 } 521 522 return data; /* Leave LE untouched */ 523 } 524 525 static inline unsigned long vcpu_data_host_to_guest(struct kvm_vcpu *vcpu, 526 unsigned long data, 527 unsigned int len) 528 { 529 if (kvm_vcpu_is_be(vcpu)) { 530 switch (len) { 531 case 1: 532 return data & 0xff; 533 case 2: 534 return cpu_to_be16(data & 0xffff); 535 case 4: 536 return cpu_to_be32(data & 0xffffffff); 537 default: 538 return cpu_to_be64(data); 539 } 540 } else { 541 switch (len) { 542 case 1: 543 return data & 0xff; 544 case 2: 545 return cpu_to_le16(data & 0xffff); 546 case 4: 547 return cpu_to_le32(data & 0xffffffff); 548 default: 549 return cpu_to_le64(data); 550 } 551 } 552 553 return data; /* Leave LE untouched */ 554 } 555 556 static __always_inline void kvm_incr_pc(struct kvm_vcpu *vcpu) 557 { 558 WARN_ON(vcpu_get_flag(vcpu, PENDING_EXCEPTION)); 559 vcpu_set_flag(vcpu, INCREMENT_PC); 560 } 561 562 #define kvm_pend_exception(v, e) \ 563 do { \ 564 WARN_ON(vcpu_get_flag((v), INCREMENT_PC)); \ 565 vcpu_set_flag((v), PENDING_EXCEPTION); \ 566 vcpu_set_flag((v), e); \ 567 } while (0) 568 569 #define __build_check_all_or_none(r, bits) \ 570 BUILD_BUG_ON(((r) & (bits)) && ((r) & (bits)) != (bits)) 571 572 #define __cpacr_to_cptr_clr(clr, set) \ 573 ({ \ 574 u64 cptr = 0; \ 575 \ 576 if ((set) & CPACR_ELx_FPEN) \ 577 cptr |= CPTR_EL2_TFP; \ 578 if ((set) & CPACR_ELx_ZEN) \ 579 cptr |= CPTR_EL2_TZ; \ 580 if ((set) & CPACR_ELx_SMEN) \ 581 cptr |= CPTR_EL2_TSM; \ 582 if ((clr) & CPACR_ELx_TTA) \ 583 cptr |= CPTR_EL2_TTA; \ 584 if ((clr) & CPTR_EL2_TAM) \ 585 cptr |= CPTR_EL2_TAM; \ 586 if ((clr) & CPTR_EL2_TCPAC) \ 587 cptr |= CPTR_EL2_TCPAC; \ 588 \ 589 cptr; \ 590 }) 591 592 #define __cpacr_to_cptr_set(clr, set) \ 593 ({ \ 594 u64 cptr = 0; \ 595 \ 596 if ((clr) & CPACR_ELx_FPEN) \ 597 cptr |= CPTR_EL2_TFP; \ 598 if ((clr) & CPACR_ELx_ZEN) \ 599 cptr |= CPTR_EL2_TZ; \ 600 if ((clr) & CPACR_ELx_SMEN) \ 601 cptr |= CPTR_EL2_TSM; \ 602 if ((set) & CPACR_ELx_TTA) \ 603 cptr |= CPTR_EL2_TTA; \ 604 if ((set) & CPTR_EL2_TAM) \ 605 cptr |= CPTR_EL2_TAM; \ 606 if ((set) & CPTR_EL2_TCPAC) \ 607 cptr |= CPTR_EL2_TCPAC; \ 608 \ 609 cptr; \ 610 }) 611 612 #define cpacr_clear_set(clr, set) \ 613 do { \ 614 BUILD_BUG_ON((set) & CPTR_VHE_EL2_RES0); \ 615 BUILD_BUG_ON((clr) & CPACR_ELx_E0POE); \ 616 __build_check_all_or_none((clr), CPACR_ELx_FPEN); \ 617 __build_check_all_or_none((set), CPACR_ELx_FPEN); \ 618 __build_check_all_or_none((clr), CPACR_ELx_ZEN); \ 619 __build_check_all_or_none((set), CPACR_ELx_ZEN); \ 620 __build_check_all_or_none((clr), CPACR_ELx_SMEN); \ 621 __build_check_all_or_none((set), CPACR_ELx_SMEN); \ 622 \ 623 if (has_vhe() || has_hvhe()) \ 624 sysreg_clear_set(cpacr_el1, clr, set); \ 625 else \ 626 sysreg_clear_set(cptr_el2, \ 627 __cpacr_to_cptr_clr(clr, set), \ 628 __cpacr_to_cptr_set(clr, set));\ 629 } while (0) 630 631 static __always_inline void kvm_write_cptr_el2(u64 val) 632 { 633 if (has_vhe() || has_hvhe()) 634 write_sysreg(val, cpacr_el1); 635 else 636 write_sysreg(val, cptr_el2); 637 } 638 639 static __always_inline u64 kvm_get_reset_cptr_el2(struct kvm_vcpu *vcpu) 640 { 641 u64 val; 642 643 if (has_vhe()) { 644 val = (CPACR_ELx_FPEN | CPACR_EL1_ZEN_EL1EN); 645 if (cpus_have_final_cap(ARM64_SME)) 646 val |= CPACR_EL1_SMEN_EL1EN; 647 } else if (has_hvhe()) { 648 val = CPACR_ELx_FPEN; 649 650 if (!vcpu_has_sve(vcpu) || !guest_owns_fp_regs()) 651 val |= CPACR_ELx_ZEN; 652 if (cpus_have_final_cap(ARM64_SME)) 653 val |= CPACR_ELx_SMEN; 654 } else { 655 val = CPTR_NVHE_EL2_RES1; 656 657 if (vcpu_has_sve(vcpu) && guest_owns_fp_regs()) 658 val |= CPTR_EL2_TZ; 659 if (cpus_have_final_cap(ARM64_SME)) 660 val &= ~CPTR_EL2_TSM; 661 } 662 663 return val; 664 } 665 666 static __always_inline void kvm_reset_cptr_el2(struct kvm_vcpu *vcpu) 667 { 668 u64 val = kvm_get_reset_cptr_el2(vcpu); 669 670 kvm_write_cptr_el2(val); 671 } 672 673 /* 674 * Returns a 'sanitised' view of CPTR_EL2, translating from nVHE to the VHE 675 * format if E2H isn't set. 676 */ 677 static inline u64 vcpu_sanitised_cptr_el2(const struct kvm_vcpu *vcpu) 678 { 679 u64 cptr = __vcpu_sys_reg(vcpu, CPTR_EL2); 680 681 if (!vcpu_el2_e2h_is_set(vcpu)) 682 cptr = translate_cptr_el2_to_cpacr_el1(cptr); 683 684 return cptr; 685 } 686 687 static inline bool ____cptr_xen_trap_enabled(const struct kvm_vcpu *vcpu, 688 unsigned int xen) 689 { 690 switch (xen) { 691 case 0b00: 692 case 0b10: 693 return true; 694 case 0b01: 695 return vcpu_el2_tge_is_set(vcpu) && !vcpu_is_el2(vcpu); 696 case 0b11: 697 default: 698 return false; 699 } 700 } 701 702 #define __guest_hyp_cptr_xen_trap_enabled(vcpu, xen) \ 703 (!vcpu_has_nv(vcpu) ? false : \ 704 ____cptr_xen_trap_enabled(vcpu, \ 705 SYS_FIELD_GET(CPACR_ELx, xen, \ 706 vcpu_sanitised_cptr_el2(vcpu)))) 707 708 static inline bool guest_hyp_fpsimd_traps_enabled(const struct kvm_vcpu *vcpu) 709 { 710 return __guest_hyp_cptr_xen_trap_enabled(vcpu, FPEN); 711 } 712 713 static inline bool guest_hyp_sve_traps_enabled(const struct kvm_vcpu *vcpu) 714 { 715 return __guest_hyp_cptr_xen_trap_enabled(vcpu, ZEN); 716 } 717 718 #endif /* __ARM64_KVM_EMULATE_H__ */ 719