1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/kvm_emulate.h 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 */ 10 11 #ifndef __ARM64_KVM_EMULATE_H__ 12 #define __ARM64_KVM_EMULATE_H__ 13 14 #include <linux/kvm_host.h> 15 16 #include <asm/debug-monitors.h> 17 #include <asm/esr.h> 18 #include <asm/kvm_arm.h> 19 #include <asm/kvm_hyp.h> 20 #include <asm/kvm_nested.h> 21 #include <asm/ptrace.h> 22 #include <asm/cputype.h> 23 #include <asm/virt.h> 24 25 #define CURRENT_EL_SP_EL0_VECTOR 0x0 26 #define CURRENT_EL_SP_ELx_VECTOR 0x200 27 #define LOWER_EL_AArch64_VECTOR 0x400 28 #define LOWER_EL_AArch32_VECTOR 0x600 29 30 enum exception_type { 31 except_type_sync = 0, 32 except_type_irq = 0x80, 33 except_type_fiq = 0x100, 34 except_type_serror = 0x180, 35 }; 36 37 #define kvm_exception_type_names \ 38 { except_type_sync, "SYNC" }, \ 39 { except_type_irq, "IRQ" }, \ 40 { except_type_fiq, "FIQ" }, \ 41 { except_type_serror, "SERROR" } 42 43 bool kvm_condition_valid32(const struct kvm_vcpu *vcpu); 44 void kvm_skip_instr32(struct kvm_vcpu *vcpu); 45 46 void kvm_inject_undefined(struct kvm_vcpu *vcpu); 47 void kvm_inject_vabt(struct kvm_vcpu *vcpu); 48 void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr); 49 void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr); 50 void kvm_inject_size_fault(struct kvm_vcpu *vcpu); 51 52 void kvm_vcpu_wfi(struct kvm_vcpu *vcpu); 53 54 void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu); 55 int kvm_inject_nested_sync(struct kvm_vcpu *vcpu, u64 esr_el2); 56 int kvm_inject_nested_irq(struct kvm_vcpu *vcpu); 57 58 #if defined(__KVM_VHE_HYPERVISOR__) || defined(__KVM_NVHE_HYPERVISOR__) 59 static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu) 60 { 61 return !(vcpu->arch.hcr_el2 & HCR_RW); 62 } 63 #else 64 static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu) 65 { 66 return vcpu_has_feature(vcpu, KVM_ARM_VCPU_EL1_32BIT); 67 } 68 #endif 69 70 static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu) 71 { 72 if (!vcpu_has_run_once(vcpu)) 73 vcpu->arch.hcr_el2 = HCR_GUEST_FLAGS; 74 75 /* 76 * For non-FWB CPUs, we trap VM ops (HCR_EL2.TVM) until M+C 77 * get set in SCTLR_EL1 such that we can detect when the guest 78 * MMU gets turned on and do the necessary cache maintenance 79 * then. 80 */ 81 if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 82 vcpu->arch.hcr_el2 |= HCR_TVM; 83 } 84 85 static inline unsigned long *vcpu_hcr(struct kvm_vcpu *vcpu) 86 { 87 return (unsigned long *)&vcpu->arch.hcr_el2; 88 } 89 90 static inline void vcpu_clear_wfx_traps(struct kvm_vcpu *vcpu) 91 { 92 vcpu->arch.hcr_el2 &= ~HCR_TWE; 93 if (atomic_read(&vcpu->arch.vgic_cpu.vgic_v3.its_vpe.vlpi_count) || 94 vcpu->kvm->arch.vgic.nassgireq) 95 vcpu->arch.hcr_el2 &= ~HCR_TWI; 96 else 97 vcpu->arch.hcr_el2 |= HCR_TWI; 98 } 99 100 static inline void vcpu_set_wfx_traps(struct kvm_vcpu *vcpu) 101 { 102 vcpu->arch.hcr_el2 |= HCR_TWE; 103 vcpu->arch.hcr_el2 |= HCR_TWI; 104 } 105 106 static inline unsigned long vcpu_get_vsesr(struct kvm_vcpu *vcpu) 107 { 108 return vcpu->arch.vsesr_el2; 109 } 110 111 static inline void vcpu_set_vsesr(struct kvm_vcpu *vcpu, u64 vsesr) 112 { 113 vcpu->arch.vsesr_el2 = vsesr; 114 } 115 116 static __always_inline unsigned long *vcpu_pc(const struct kvm_vcpu *vcpu) 117 { 118 return (unsigned long *)&vcpu_gp_regs(vcpu)->pc; 119 } 120 121 static __always_inline unsigned long *vcpu_cpsr(const struct kvm_vcpu *vcpu) 122 { 123 return (unsigned long *)&vcpu_gp_regs(vcpu)->pstate; 124 } 125 126 static __always_inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu) 127 { 128 return !!(*vcpu_cpsr(vcpu) & PSR_MODE32_BIT); 129 } 130 131 static __always_inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu) 132 { 133 if (vcpu_mode_is_32bit(vcpu)) 134 return kvm_condition_valid32(vcpu); 135 136 return true; 137 } 138 139 static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu) 140 { 141 *vcpu_cpsr(vcpu) |= PSR_AA32_T_BIT; 142 } 143 144 /* 145 * vcpu_get_reg and vcpu_set_reg should always be passed a register number 146 * coming from a read of ESR_EL2. Otherwise, it may give the wrong result on 147 * AArch32 with banked registers. 148 */ 149 static __always_inline unsigned long vcpu_get_reg(const struct kvm_vcpu *vcpu, 150 u8 reg_num) 151 { 152 return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num]; 153 } 154 155 static __always_inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num, 156 unsigned long val) 157 { 158 if (reg_num != 31) 159 vcpu_gp_regs(vcpu)->regs[reg_num] = val; 160 } 161 162 static inline bool vcpu_is_el2_ctxt(const struct kvm_cpu_context *ctxt) 163 { 164 switch (ctxt->regs.pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) { 165 case PSR_MODE_EL2h: 166 case PSR_MODE_EL2t: 167 return true; 168 default: 169 return false; 170 } 171 } 172 173 static inline bool vcpu_is_el2(const struct kvm_vcpu *vcpu) 174 { 175 return vcpu_is_el2_ctxt(&vcpu->arch.ctxt); 176 } 177 178 static inline bool __vcpu_el2_e2h_is_set(const struct kvm_cpu_context *ctxt) 179 { 180 return (!cpus_have_final_cap(ARM64_HAS_HCR_NV1) || 181 (ctxt_sys_reg(ctxt, HCR_EL2) & HCR_E2H)); 182 } 183 184 static inline bool vcpu_el2_e2h_is_set(const struct kvm_vcpu *vcpu) 185 { 186 return __vcpu_el2_e2h_is_set(&vcpu->arch.ctxt); 187 } 188 189 static inline bool __vcpu_el2_tge_is_set(const struct kvm_cpu_context *ctxt) 190 { 191 return ctxt_sys_reg(ctxt, HCR_EL2) & HCR_TGE; 192 } 193 194 static inline bool vcpu_el2_tge_is_set(const struct kvm_vcpu *vcpu) 195 { 196 return __vcpu_el2_tge_is_set(&vcpu->arch.ctxt); 197 } 198 199 static inline bool __is_hyp_ctxt(const struct kvm_cpu_context *ctxt) 200 { 201 /* 202 * We are in a hypervisor context if the vcpu mode is EL2 or 203 * E2H and TGE bits are set. The latter means we are in the user space 204 * of the VHE kernel. ARMv8.1 ARM describes this as 'InHost' 205 * 206 * Note that the HCR_EL2.{E2H,TGE}={0,1} isn't really handled in the 207 * rest of the KVM code, and will result in a misbehaving guest. 208 */ 209 return vcpu_is_el2_ctxt(ctxt) || 210 (__vcpu_el2_e2h_is_set(ctxt) && __vcpu_el2_tge_is_set(ctxt)) || 211 __vcpu_el2_tge_is_set(ctxt); 212 } 213 214 static inline bool is_hyp_ctxt(const struct kvm_vcpu *vcpu) 215 { 216 return vcpu_has_nv(vcpu) && __is_hyp_ctxt(&vcpu->arch.ctxt); 217 } 218 219 /* 220 * The layout of SPSR for an AArch32 state is different when observed from an 221 * AArch64 SPSR_ELx or an AArch32 SPSR_*. This function generates the AArch32 222 * view given an AArch64 view. 223 * 224 * In ARM DDI 0487E.a see: 225 * 226 * - The AArch64 view (SPSR_EL2) in section C5.2.18, page C5-426 227 * - The AArch32 view (SPSR_abt) in section G8.2.126, page G8-6256 228 * - The AArch32 view (SPSR_und) in section G8.2.132, page G8-6280 229 * 230 * Which show the following differences: 231 * 232 * | Bit | AA64 | AA32 | Notes | 233 * +-----+------+------+-----------------------------| 234 * | 24 | DIT | J | J is RES0 in ARMv8 | 235 * | 21 | SS | DIT | SS doesn't exist in AArch32 | 236 * 237 * ... and all other bits are (currently) common. 238 */ 239 static inline unsigned long host_spsr_to_spsr32(unsigned long spsr) 240 { 241 const unsigned long overlap = BIT(24) | BIT(21); 242 unsigned long dit = !!(spsr & PSR_AA32_DIT_BIT); 243 244 spsr &= ~overlap; 245 246 spsr |= dit << 21; 247 248 return spsr; 249 } 250 251 static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu) 252 { 253 u32 mode; 254 255 if (vcpu_mode_is_32bit(vcpu)) { 256 mode = *vcpu_cpsr(vcpu) & PSR_AA32_MODE_MASK; 257 return mode > PSR_AA32_MODE_USR; 258 } 259 260 mode = *vcpu_cpsr(vcpu) & PSR_MODE_MASK; 261 262 return mode != PSR_MODE_EL0t; 263 } 264 265 static __always_inline u64 kvm_vcpu_get_esr(const struct kvm_vcpu *vcpu) 266 { 267 return vcpu->arch.fault.esr_el2; 268 } 269 270 static __always_inline int kvm_vcpu_get_condition(const struct kvm_vcpu *vcpu) 271 { 272 u64 esr = kvm_vcpu_get_esr(vcpu); 273 274 if (esr & ESR_ELx_CV) 275 return (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT; 276 277 return -1; 278 } 279 280 static __always_inline unsigned long kvm_vcpu_get_hfar(const struct kvm_vcpu *vcpu) 281 { 282 return vcpu->arch.fault.far_el2; 283 } 284 285 static __always_inline phys_addr_t kvm_vcpu_get_fault_ipa(const struct kvm_vcpu *vcpu) 286 { 287 return ((phys_addr_t)vcpu->arch.fault.hpfar_el2 & HPFAR_MASK) << 8; 288 } 289 290 static inline u64 kvm_vcpu_get_disr(const struct kvm_vcpu *vcpu) 291 { 292 return vcpu->arch.fault.disr_el1; 293 } 294 295 static inline u32 kvm_vcpu_hvc_get_imm(const struct kvm_vcpu *vcpu) 296 { 297 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_xVC_IMM_MASK; 298 } 299 300 static __always_inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu) 301 { 302 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_ISV); 303 } 304 305 static inline unsigned long kvm_vcpu_dabt_iss_nisv_sanitized(const struct kvm_vcpu *vcpu) 306 { 307 return kvm_vcpu_get_esr(vcpu) & (ESR_ELx_CM | ESR_ELx_WNR | ESR_ELx_FSC); 308 } 309 310 static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu) 311 { 312 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_SSE); 313 } 314 315 static inline bool kvm_vcpu_dabt_issf(const struct kvm_vcpu *vcpu) 316 { 317 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_SF); 318 } 319 320 static __always_inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu) 321 { 322 return (kvm_vcpu_get_esr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT; 323 } 324 325 static __always_inline bool kvm_vcpu_abt_iss1tw(const struct kvm_vcpu *vcpu) 326 { 327 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_S1PTW); 328 } 329 330 /* Always check for S1PTW *before* using this. */ 331 static __always_inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu) 332 { 333 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_WNR; 334 } 335 336 static inline bool kvm_vcpu_dabt_is_cm(const struct kvm_vcpu *vcpu) 337 { 338 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_CM); 339 } 340 341 static __always_inline unsigned int kvm_vcpu_dabt_get_as(const struct kvm_vcpu *vcpu) 342 { 343 return 1 << ((kvm_vcpu_get_esr(vcpu) & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT); 344 } 345 346 /* This one is not specific to Data Abort */ 347 static __always_inline bool kvm_vcpu_trap_il_is32bit(const struct kvm_vcpu *vcpu) 348 { 349 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_IL); 350 } 351 352 static __always_inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu) 353 { 354 return ESR_ELx_EC(kvm_vcpu_get_esr(vcpu)); 355 } 356 357 static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu) 358 { 359 return kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_IABT_LOW; 360 } 361 362 static inline bool kvm_vcpu_trap_is_exec_fault(const struct kvm_vcpu *vcpu) 363 { 364 return kvm_vcpu_trap_is_iabt(vcpu) && !kvm_vcpu_abt_iss1tw(vcpu); 365 } 366 367 static __always_inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu) 368 { 369 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC; 370 } 371 372 static inline 373 bool kvm_vcpu_trap_is_permission_fault(const struct kvm_vcpu *vcpu) 374 { 375 return esr_fsc_is_permission_fault(kvm_vcpu_get_esr(vcpu)); 376 } 377 378 static inline 379 bool kvm_vcpu_trap_is_translation_fault(const struct kvm_vcpu *vcpu) 380 { 381 return esr_fsc_is_translation_fault(kvm_vcpu_get_esr(vcpu)); 382 } 383 384 static inline 385 u64 kvm_vcpu_trap_get_perm_fault_granule(const struct kvm_vcpu *vcpu) 386 { 387 unsigned long esr = kvm_vcpu_get_esr(vcpu); 388 389 BUG_ON(!esr_fsc_is_permission_fault(esr)); 390 return BIT(ARM64_HW_PGTABLE_LEVEL_SHIFT(esr & ESR_ELx_FSC_LEVEL)); 391 } 392 393 static __always_inline bool kvm_vcpu_abt_issea(const struct kvm_vcpu *vcpu) 394 { 395 switch (kvm_vcpu_trap_get_fault(vcpu)) { 396 case ESR_ELx_FSC_EXTABT: 397 case ESR_ELx_FSC_SEA_TTW(-1) ... ESR_ELx_FSC_SEA_TTW(3): 398 case ESR_ELx_FSC_SECC: 399 case ESR_ELx_FSC_SECC_TTW(-1) ... ESR_ELx_FSC_SECC_TTW(3): 400 return true; 401 default: 402 return false; 403 } 404 } 405 406 static __always_inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu) 407 { 408 u64 esr = kvm_vcpu_get_esr(vcpu); 409 return ESR_ELx_SYS64_ISS_RT(esr); 410 } 411 412 static inline bool kvm_is_write_fault(struct kvm_vcpu *vcpu) 413 { 414 if (kvm_vcpu_abt_iss1tw(vcpu)) { 415 /* 416 * Only a permission fault on a S1PTW should be 417 * considered as a write. Otherwise, page tables baked 418 * in a read-only memslot will result in an exception 419 * being delivered in the guest. 420 * 421 * The drawback is that we end-up faulting twice if the 422 * guest is using any of HW AF/DB: a translation fault 423 * to map the page containing the PT (read only at 424 * first), then a permission fault to allow the flags 425 * to be set. 426 */ 427 return kvm_vcpu_trap_is_permission_fault(vcpu); 428 } 429 430 if (kvm_vcpu_trap_is_iabt(vcpu)) 431 return false; 432 433 return kvm_vcpu_dabt_iswrite(vcpu); 434 } 435 436 static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu) 437 { 438 return __vcpu_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK; 439 } 440 441 static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu) 442 { 443 if (vcpu_mode_is_32bit(vcpu)) { 444 *vcpu_cpsr(vcpu) |= PSR_AA32_E_BIT; 445 } else { 446 u64 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1); 447 sctlr |= SCTLR_ELx_EE; 448 vcpu_write_sys_reg(vcpu, sctlr, SCTLR_EL1); 449 } 450 } 451 452 static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu) 453 { 454 if (vcpu_mode_is_32bit(vcpu)) 455 return !!(*vcpu_cpsr(vcpu) & PSR_AA32_E_BIT); 456 457 if (vcpu_mode_priv(vcpu)) 458 return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & SCTLR_ELx_EE); 459 else 460 return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & SCTLR_EL1_E0E); 461 } 462 463 static inline unsigned long vcpu_data_guest_to_host(struct kvm_vcpu *vcpu, 464 unsigned long data, 465 unsigned int len) 466 { 467 if (kvm_vcpu_is_be(vcpu)) { 468 switch (len) { 469 case 1: 470 return data & 0xff; 471 case 2: 472 return be16_to_cpu(data & 0xffff); 473 case 4: 474 return be32_to_cpu(data & 0xffffffff); 475 default: 476 return be64_to_cpu(data); 477 } 478 } else { 479 switch (len) { 480 case 1: 481 return data & 0xff; 482 case 2: 483 return le16_to_cpu(data & 0xffff); 484 case 4: 485 return le32_to_cpu(data & 0xffffffff); 486 default: 487 return le64_to_cpu(data); 488 } 489 } 490 491 return data; /* Leave LE untouched */ 492 } 493 494 static inline unsigned long vcpu_data_host_to_guest(struct kvm_vcpu *vcpu, 495 unsigned long data, 496 unsigned int len) 497 { 498 if (kvm_vcpu_is_be(vcpu)) { 499 switch (len) { 500 case 1: 501 return data & 0xff; 502 case 2: 503 return cpu_to_be16(data & 0xffff); 504 case 4: 505 return cpu_to_be32(data & 0xffffffff); 506 default: 507 return cpu_to_be64(data); 508 } 509 } else { 510 switch (len) { 511 case 1: 512 return data & 0xff; 513 case 2: 514 return cpu_to_le16(data & 0xffff); 515 case 4: 516 return cpu_to_le32(data & 0xffffffff); 517 default: 518 return cpu_to_le64(data); 519 } 520 } 521 522 return data; /* Leave LE untouched */ 523 } 524 525 static __always_inline void kvm_incr_pc(struct kvm_vcpu *vcpu) 526 { 527 WARN_ON(vcpu_get_flag(vcpu, PENDING_EXCEPTION)); 528 vcpu_set_flag(vcpu, INCREMENT_PC); 529 } 530 531 #define kvm_pend_exception(v, e) \ 532 do { \ 533 WARN_ON(vcpu_get_flag((v), INCREMENT_PC)); \ 534 vcpu_set_flag((v), PENDING_EXCEPTION); \ 535 vcpu_set_flag((v), e); \ 536 } while (0) 537 538 #define __build_check_all_or_none(r, bits) \ 539 BUILD_BUG_ON(((r) & (bits)) && ((r) & (bits)) != (bits)) 540 541 #define __cpacr_to_cptr_clr(clr, set) \ 542 ({ \ 543 u64 cptr = 0; \ 544 \ 545 if ((set) & CPACR_ELx_FPEN) \ 546 cptr |= CPTR_EL2_TFP; \ 547 if ((set) & CPACR_ELx_ZEN) \ 548 cptr |= CPTR_EL2_TZ; \ 549 if ((set) & CPACR_ELx_SMEN) \ 550 cptr |= CPTR_EL2_TSM; \ 551 if ((clr) & CPACR_ELx_TTA) \ 552 cptr |= CPTR_EL2_TTA; \ 553 if ((clr) & CPTR_EL2_TAM) \ 554 cptr |= CPTR_EL2_TAM; \ 555 if ((clr) & CPTR_EL2_TCPAC) \ 556 cptr |= CPTR_EL2_TCPAC; \ 557 \ 558 cptr; \ 559 }) 560 561 #define __cpacr_to_cptr_set(clr, set) \ 562 ({ \ 563 u64 cptr = 0; \ 564 \ 565 if ((clr) & CPACR_ELx_FPEN) \ 566 cptr |= CPTR_EL2_TFP; \ 567 if ((clr) & CPACR_ELx_ZEN) \ 568 cptr |= CPTR_EL2_TZ; \ 569 if ((clr) & CPACR_ELx_SMEN) \ 570 cptr |= CPTR_EL2_TSM; \ 571 if ((set) & CPACR_ELx_TTA) \ 572 cptr |= CPTR_EL2_TTA; \ 573 if ((set) & CPTR_EL2_TAM) \ 574 cptr |= CPTR_EL2_TAM; \ 575 if ((set) & CPTR_EL2_TCPAC) \ 576 cptr |= CPTR_EL2_TCPAC; \ 577 \ 578 cptr; \ 579 }) 580 581 #define cpacr_clear_set(clr, set) \ 582 do { \ 583 BUILD_BUG_ON((set) & CPTR_VHE_EL2_RES0); \ 584 BUILD_BUG_ON((clr) & CPACR_ELx_E0POE); \ 585 __build_check_all_or_none((clr), CPACR_ELx_FPEN); \ 586 __build_check_all_or_none((set), CPACR_ELx_FPEN); \ 587 __build_check_all_or_none((clr), CPACR_ELx_ZEN); \ 588 __build_check_all_or_none((set), CPACR_ELx_ZEN); \ 589 __build_check_all_or_none((clr), CPACR_ELx_SMEN); \ 590 __build_check_all_or_none((set), CPACR_ELx_SMEN); \ 591 \ 592 if (has_vhe() || has_hvhe()) \ 593 sysreg_clear_set(cpacr_el1, clr, set); \ 594 else \ 595 sysreg_clear_set(cptr_el2, \ 596 __cpacr_to_cptr_clr(clr, set), \ 597 __cpacr_to_cptr_set(clr, set));\ 598 } while (0) 599 600 static __always_inline void kvm_write_cptr_el2(u64 val) 601 { 602 if (has_vhe() || has_hvhe()) 603 write_sysreg(val, cpacr_el1); 604 else 605 write_sysreg(val, cptr_el2); 606 } 607 608 static __always_inline u64 kvm_get_reset_cptr_el2(struct kvm_vcpu *vcpu) 609 { 610 u64 val; 611 612 if (has_vhe()) { 613 val = (CPACR_ELx_FPEN | CPACR_EL1_ZEN_EL1EN); 614 if (cpus_have_final_cap(ARM64_SME)) 615 val |= CPACR_EL1_SMEN_EL1EN; 616 } else if (has_hvhe()) { 617 val = CPACR_ELx_FPEN; 618 619 if (!vcpu_has_sve(vcpu) || !guest_owns_fp_regs()) 620 val |= CPACR_ELx_ZEN; 621 if (cpus_have_final_cap(ARM64_SME)) 622 val |= CPACR_ELx_SMEN; 623 } else { 624 val = CPTR_NVHE_EL2_RES1; 625 626 if (vcpu_has_sve(vcpu) && guest_owns_fp_regs()) 627 val |= CPTR_EL2_TZ; 628 if (cpus_have_final_cap(ARM64_SME)) 629 val &= ~CPTR_EL2_TSM; 630 } 631 632 return val; 633 } 634 635 static __always_inline void kvm_reset_cptr_el2(struct kvm_vcpu *vcpu) 636 { 637 u64 val = kvm_get_reset_cptr_el2(vcpu); 638 639 kvm_write_cptr_el2(val); 640 } 641 #endif /* __ARM64_KVM_EMULATE_H__ */ 642