1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/kvm_emulate.h 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 */ 10 11 #ifndef __ARM64_KVM_EMULATE_H__ 12 #define __ARM64_KVM_EMULATE_H__ 13 14 #include <linux/kvm_host.h> 15 16 #include <asm/debug-monitors.h> 17 #include <asm/esr.h> 18 #include <asm/kvm_arm.h> 19 #include <asm/kvm_hyp.h> 20 #include <asm/kvm_nested.h> 21 #include <asm/ptrace.h> 22 #include <asm/cputype.h> 23 #include <asm/virt.h> 24 25 #define CURRENT_EL_SP_EL0_VECTOR 0x0 26 #define CURRENT_EL_SP_ELx_VECTOR 0x200 27 #define LOWER_EL_AArch64_VECTOR 0x400 28 #define LOWER_EL_AArch32_VECTOR 0x600 29 30 enum exception_type { 31 except_type_sync = 0, 32 except_type_irq = 0x80, 33 except_type_fiq = 0x100, 34 except_type_serror = 0x180, 35 }; 36 37 #define kvm_exception_type_names \ 38 { except_type_sync, "SYNC" }, \ 39 { except_type_irq, "IRQ" }, \ 40 { except_type_fiq, "FIQ" }, \ 41 { except_type_serror, "SERROR" } 42 43 bool kvm_condition_valid32(const struct kvm_vcpu *vcpu); 44 void kvm_skip_instr32(struct kvm_vcpu *vcpu); 45 46 void kvm_inject_undefined(struct kvm_vcpu *vcpu); 47 void kvm_inject_vabt(struct kvm_vcpu *vcpu); 48 void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr); 49 void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr); 50 void kvm_inject_size_fault(struct kvm_vcpu *vcpu); 51 52 void kvm_vcpu_wfi(struct kvm_vcpu *vcpu); 53 54 void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu); 55 int kvm_inject_nested_sync(struct kvm_vcpu *vcpu, u64 esr_el2); 56 int kvm_inject_nested_irq(struct kvm_vcpu *vcpu); 57 58 #if defined(__KVM_VHE_HYPERVISOR__) || defined(__KVM_NVHE_HYPERVISOR__) 59 static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu) 60 { 61 return !(vcpu->arch.hcr_el2 & HCR_RW); 62 } 63 #else 64 static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu) 65 { 66 return vcpu_has_feature(vcpu, KVM_ARM_VCPU_EL1_32BIT); 67 } 68 #endif 69 70 static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu) 71 { 72 vcpu->arch.hcr_el2 = HCR_GUEST_FLAGS; 73 if (has_vhe() || has_hvhe()) 74 vcpu->arch.hcr_el2 |= HCR_E2H; 75 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) { 76 /* route synchronous external abort exceptions to EL2 */ 77 vcpu->arch.hcr_el2 |= HCR_TEA; 78 /* trap error record accesses */ 79 vcpu->arch.hcr_el2 |= HCR_TERR; 80 } 81 82 if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) { 83 vcpu->arch.hcr_el2 |= HCR_FWB; 84 } else { 85 /* 86 * For non-FWB CPUs, we trap VM ops (HCR_EL2.TVM) until M+C 87 * get set in SCTLR_EL1 such that we can detect when the guest 88 * MMU gets turned on and do the necessary cache maintenance 89 * then. 90 */ 91 vcpu->arch.hcr_el2 |= HCR_TVM; 92 } 93 94 if (cpus_have_final_cap(ARM64_HAS_EVT) && 95 !cpus_have_final_cap(ARM64_MISMATCHED_CACHE_TYPE)) 96 vcpu->arch.hcr_el2 |= HCR_TID4; 97 else 98 vcpu->arch.hcr_el2 |= HCR_TID2; 99 100 if (vcpu_el1_is_32bit(vcpu)) 101 vcpu->arch.hcr_el2 &= ~HCR_RW; 102 103 if (kvm_has_mte(vcpu->kvm)) 104 vcpu->arch.hcr_el2 |= HCR_ATA; 105 } 106 107 static inline unsigned long *vcpu_hcr(struct kvm_vcpu *vcpu) 108 { 109 return (unsigned long *)&vcpu->arch.hcr_el2; 110 } 111 112 static inline void vcpu_clear_wfx_traps(struct kvm_vcpu *vcpu) 113 { 114 vcpu->arch.hcr_el2 &= ~HCR_TWE; 115 if (atomic_read(&vcpu->arch.vgic_cpu.vgic_v3.its_vpe.vlpi_count) || 116 vcpu->kvm->arch.vgic.nassgireq) 117 vcpu->arch.hcr_el2 &= ~HCR_TWI; 118 else 119 vcpu->arch.hcr_el2 |= HCR_TWI; 120 } 121 122 static inline void vcpu_set_wfx_traps(struct kvm_vcpu *vcpu) 123 { 124 vcpu->arch.hcr_el2 |= HCR_TWE; 125 vcpu->arch.hcr_el2 |= HCR_TWI; 126 } 127 128 static inline unsigned long vcpu_get_vsesr(struct kvm_vcpu *vcpu) 129 { 130 return vcpu->arch.vsesr_el2; 131 } 132 133 static inline void vcpu_set_vsesr(struct kvm_vcpu *vcpu, u64 vsesr) 134 { 135 vcpu->arch.vsesr_el2 = vsesr; 136 } 137 138 static __always_inline unsigned long *vcpu_pc(const struct kvm_vcpu *vcpu) 139 { 140 return (unsigned long *)&vcpu_gp_regs(vcpu)->pc; 141 } 142 143 static __always_inline unsigned long *vcpu_cpsr(const struct kvm_vcpu *vcpu) 144 { 145 return (unsigned long *)&vcpu_gp_regs(vcpu)->pstate; 146 } 147 148 static __always_inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu) 149 { 150 return !!(*vcpu_cpsr(vcpu) & PSR_MODE32_BIT); 151 } 152 153 static __always_inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu) 154 { 155 if (vcpu_mode_is_32bit(vcpu)) 156 return kvm_condition_valid32(vcpu); 157 158 return true; 159 } 160 161 static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu) 162 { 163 *vcpu_cpsr(vcpu) |= PSR_AA32_T_BIT; 164 } 165 166 /* 167 * vcpu_get_reg and vcpu_set_reg should always be passed a register number 168 * coming from a read of ESR_EL2. Otherwise, it may give the wrong result on 169 * AArch32 with banked registers. 170 */ 171 static __always_inline unsigned long vcpu_get_reg(const struct kvm_vcpu *vcpu, 172 u8 reg_num) 173 { 174 return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num]; 175 } 176 177 static __always_inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num, 178 unsigned long val) 179 { 180 if (reg_num != 31) 181 vcpu_gp_regs(vcpu)->regs[reg_num] = val; 182 } 183 184 static inline bool vcpu_is_el2_ctxt(const struct kvm_cpu_context *ctxt) 185 { 186 switch (ctxt->regs.pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) { 187 case PSR_MODE_EL2h: 188 case PSR_MODE_EL2t: 189 return true; 190 default: 191 return false; 192 } 193 } 194 195 static inline bool vcpu_is_el2(const struct kvm_vcpu *vcpu) 196 { 197 return vcpu_is_el2_ctxt(&vcpu->arch.ctxt); 198 } 199 200 static inline bool __vcpu_el2_e2h_is_set(const struct kvm_cpu_context *ctxt) 201 { 202 return (!cpus_have_final_cap(ARM64_HAS_HCR_NV1) || 203 (ctxt_sys_reg(ctxt, HCR_EL2) & HCR_E2H)); 204 } 205 206 static inline bool vcpu_el2_e2h_is_set(const struct kvm_vcpu *vcpu) 207 { 208 return __vcpu_el2_e2h_is_set(&vcpu->arch.ctxt); 209 } 210 211 static inline bool __vcpu_el2_tge_is_set(const struct kvm_cpu_context *ctxt) 212 { 213 return ctxt_sys_reg(ctxt, HCR_EL2) & HCR_TGE; 214 } 215 216 static inline bool vcpu_el2_tge_is_set(const struct kvm_vcpu *vcpu) 217 { 218 return __vcpu_el2_tge_is_set(&vcpu->arch.ctxt); 219 } 220 221 static inline bool __is_hyp_ctxt(const struct kvm_cpu_context *ctxt) 222 { 223 /* 224 * We are in a hypervisor context if the vcpu mode is EL2 or 225 * E2H and TGE bits are set. The latter means we are in the user space 226 * of the VHE kernel. ARMv8.1 ARM describes this as 'InHost' 227 * 228 * Note that the HCR_EL2.{E2H,TGE}={0,1} isn't really handled in the 229 * rest of the KVM code, and will result in a misbehaving guest. 230 */ 231 return vcpu_is_el2_ctxt(ctxt) || 232 (__vcpu_el2_e2h_is_set(ctxt) && __vcpu_el2_tge_is_set(ctxt)) || 233 __vcpu_el2_tge_is_set(ctxt); 234 } 235 236 static inline bool is_hyp_ctxt(const struct kvm_vcpu *vcpu) 237 { 238 return vcpu_has_nv(vcpu) && __is_hyp_ctxt(&vcpu->arch.ctxt); 239 } 240 241 /* 242 * The layout of SPSR for an AArch32 state is different when observed from an 243 * AArch64 SPSR_ELx or an AArch32 SPSR_*. This function generates the AArch32 244 * view given an AArch64 view. 245 * 246 * In ARM DDI 0487E.a see: 247 * 248 * - The AArch64 view (SPSR_EL2) in section C5.2.18, page C5-426 249 * - The AArch32 view (SPSR_abt) in section G8.2.126, page G8-6256 250 * - The AArch32 view (SPSR_und) in section G8.2.132, page G8-6280 251 * 252 * Which show the following differences: 253 * 254 * | Bit | AA64 | AA32 | Notes | 255 * +-----+------+------+-----------------------------| 256 * | 24 | DIT | J | J is RES0 in ARMv8 | 257 * | 21 | SS | DIT | SS doesn't exist in AArch32 | 258 * 259 * ... and all other bits are (currently) common. 260 */ 261 static inline unsigned long host_spsr_to_spsr32(unsigned long spsr) 262 { 263 const unsigned long overlap = BIT(24) | BIT(21); 264 unsigned long dit = !!(spsr & PSR_AA32_DIT_BIT); 265 266 spsr &= ~overlap; 267 268 spsr |= dit << 21; 269 270 return spsr; 271 } 272 273 static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu) 274 { 275 u32 mode; 276 277 if (vcpu_mode_is_32bit(vcpu)) { 278 mode = *vcpu_cpsr(vcpu) & PSR_AA32_MODE_MASK; 279 return mode > PSR_AA32_MODE_USR; 280 } 281 282 mode = *vcpu_cpsr(vcpu) & PSR_MODE_MASK; 283 284 return mode != PSR_MODE_EL0t; 285 } 286 287 static __always_inline u64 kvm_vcpu_get_esr(const struct kvm_vcpu *vcpu) 288 { 289 return vcpu->arch.fault.esr_el2; 290 } 291 292 static __always_inline int kvm_vcpu_get_condition(const struct kvm_vcpu *vcpu) 293 { 294 u64 esr = kvm_vcpu_get_esr(vcpu); 295 296 if (esr & ESR_ELx_CV) 297 return (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT; 298 299 return -1; 300 } 301 302 static __always_inline unsigned long kvm_vcpu_get_hfar(const struct kvm_vcpu *vcpu) 303 { 304 return vcpu->arch.fault.far_el2; 305 } 306 307 static __always_inline phys_addr_t kvm_vcpu_get_fault_ipa(const struct kvm_vcpu *vcpu) 308 { 309 return ((phys_addr_t)vcpu->arch.fault.hpfar_el2 & HPFAR_MASK) << 8; 310 } 311 312 static inline u64 kvm_vcpu_get_disr(const struct kvm_vcpu *vcpu) 313 { 314 return vcpu->arch.fault.disr_el1; 315 } 316 317 static inline u32 kvm_vcpu_hvc_get_imm(const struct kvm_vcpu *vcpu) 318 { 319 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_xVC_IMM_MASK; 320 } 321 322 static __always_inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu) 323 { 324 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_ISV); 325 } 326 327 static inline unsigned long kvm_vcpu_dabt_iss_nisv_sanitized(const struct kvm_vcpu *vcpu) 328 { 329 return kvm_vcpu_get_esr(vcpu) & (ESR_ELx_CM | ESR_ELx_WNR | ESR_ELx_FSC); 330 } 331 332 static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu) 333 { 334 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_SSE); 335 } 336 337 static inline bool kvm_vcpu_dabt_issf(const struct kvm_vcpu *vcpu) 338 { 339 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_SF); 340 } 341 342 static __always_inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu) 343 { 344 return (kvm_vcpu_get_esr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT; 345 } 346 347 static __always_inline bool kvm_vcpu_abt_iss1tw(const struct kvm_vcpu *vcpu) 348 { 349 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_S1PTW); 350 } 351 352 /* Always check for S1PTW *before* using this. */ 353 static __always_inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu) 354 { 355 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_WNR; 356 } 357 358 static inline bool kvm_vcpu_dabt_is_cm(const struct kvm_vcpu *vcpu) 359 { 360 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_CM); 361 } 362 363 static __always_inline unsigned int kvm_vcpu_dabt_get_as(const struct kvm_vcpu *vcpu) 364 { 365 return 1 << ((kvm_vcpu_get_esr(vcpu) & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT); 366 } 367 368 /* This one is not specific to Data Abort */ 369 static __always_inline bool kvm_vcpu_trap_il_is32bit(const struct kvm_vcpu *vcpu) 370 { 371 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_IL); 372 } 373 374 static __always_inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu) 375 { 376 return ESR_ELx_EC(kvm_vcpu_get_esr(vcpu)); 377 } 378 379 static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu) 380 { 381 return kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_IABT_LOW; 382 } 383 384 static inline bool kvm_vcpu_trap_is_exec_fault(const struct kvm_vcpu *vcpu) 385 { 386 return kvm_vcpu_trap_is_iabt(vcpu) && !kvm_vcpu_abt_iss1tw(vcpu); 387 } 388 389 static __always_inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu) 390 { 391 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC; 392 } 393 394 static inline 395 bool kvm_vcpu_trap_is_permission_fault(const struct kvm_vcpu *vcpu) 396 { 397 return esr_fsc_is_permission_fault(kvm_vcpu_get_esr(vcpu)); 398 } 399 400 static inline 401 bool kvm_vcpu_trap_is_translation_fault(const struct kvm_vcpu *vcpu) 402 { 403 return esr_fsc_is_translation_fault(kvm_vcpu_get_esr(vcpu)); 404 } 405 406 static inline 407 u64 kvm_vcpu_trap_get_perm_fault_granule(const struct kvm_vcpu *vcpu) 408 { 409 unsigned long esr = kvm_vcpu_get_esr(vcpu); 410 411 BUG_ON(!esr_fsc_is_permission_fault(esr)); 412 return BIT(ARM64_HW_PGTABLE_LEVEL_SHIFT(esr & ESR_ELx_FSC_LEVEL)); 413 } 414 415 static __always_inline bool kvm_vcpu_abt_issea(const struct kvm_vcpu *vcpu) 416 { 417 switch (kvm_vcpu_trap_get_fault(vcpu)) { 418 case ESR_ELx_FSC_EXTABT: 419 case ESR_ELx_FSC_SEA_TTW(-1) ... ESR_ELx_FSC_SEA_TTW(3): 420 case ESR_ELx_FSC_SECC: 421 case ESR_ELx_FSC_SECC_TTW(-1) ... ESR_ELx_FSC_SECC_TTW(3): 422 return true; 423 default: 424 return false; 425 } 426 } 427 428 static __always_inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu) 429 { 430 u64 esr = kvm_vcpu_get_esr(vcpu); 431 return ESR_ELx_SYS64_ISS_RT(esr); 432 } 433 434 static inline bool kvm_is_write_fault(struct kvm_vcpu *vcpu) 435 { 436 if (kvm_vcpu_abt_iss1tw(vcpu)) { 437 /* 438 * Only a permission fault on a S1PTW should be 439 * considered as a write. Otherwise, page tables baked 440 * in a read-only memslot will result in an exception 441 * being delivered in the guest. 442 * 443 * The drawback is that we end-up faulting twice if the 444 * guest is using any of HW AF/DB: a translation fault 445 * to map the page containing the PT (read only at 446 * first), then a permission fault to allow the flags 447 * to be set. 448 */ 449 return kvm_vcpu_trap_is_permission_fault(vcpu); 450 } 451 452 if (kvm_vcpu_trap_is_iabt(vcpu)) 453 return false; 454 455 return kvm_vcpu_dabt_iswrite(vcpu); 456 } 457 458 static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu) 459 { 460 return __vcpu_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK; 461 } 462 463 static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu) 464 { 465 if (vcpu_mode_is_32bit(vcpu)) { 466 *vcpu_cpsr(vcpu) |= PSR_AA32_E_BIT; 467 } else { 468 u64 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1); 469 sctlr |= SCTLR_ELx_EE; 470 vcpu_write_sys_reg(vcpu, sctlr, SCTLR_EL1); 471 } 472 } 473 474 static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu) 475 { 476 if (vcpu_mode_is_32bit(vcpu)) 477 return !!(*vcpu_cpsr(vcpu) & PSR_AA32_E_BIT); 478 479 if (vcpu_mode_priv(vcpu)) 480 return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & SCTLR_ELx_EE); 481 else 482 return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & SCTLR_EL1_E0E); 483 } 484 485 static inline unsigned long vcpu_data_guest_to_host(struct kvm_vcpu *vcpu, 486 unsigned long data, 487 unsigned int len) 488 { 489 if (kvm_vcpu_is_be(vcpu)) { 490 switch (len) { 491 case 1: 492 return data & 0xff; 493 case 2: 494 return be16_to_cpu(data & 0xffff); 495 case 4: 496 return be32_to_cpu(data & 0xffffffff); 497 default: 498 return be64_to_cpu(data); 499 } 500 } else { 501 switch (len) { 502 case 1: 503 return data & 0xff; 504 case 2: 505 return le16_to_cpu(data & 0xffff); 506 case 4: 507 return le32_to_cpu(data & 0xffffffff); 508 default: 509 return le64_to_cpu(data); 510 } 511 } 512 513 return data; /* Leave LE untouched */ 514 } 515 516 static inline unsigned long vcpu_data_host_to_guest(struct kvm_vcpu *vcpu, 517 unsigned long data, 518 unsigned int len) 519 { 520 if (kvm_vcpu_is_be(vcpu)) { 521 switch (len) { 522 case 1: 523 return data & 0xff; 524 case 2: 525 return cpu_to_be16(data & 0xffff); 526 case 4: 527 return cpu_to_be32(data & 0xffffffff); 528 default: 529 return cpu_to_be64(data); 530 } 531 } else { 532 switch (len) { 533 case 1: 534 return data & 0xff; 535 case 2: 536 return cpu_to_le16(data & 0xffff); 537 case 4: 538 return cpu_to_le32(data & 0xffffffff); 539 default: 540 return cpu_to_le64(data); 541 } 542 } 543 544 return data; /* Leave LE untouched */ 545 } 546 547 static __always_inline void kvm_incr_pc(struct kvm_vcpu *vcpu) 548 { 549 WARN_ON(vcpu_get_flag(vcpu, PENDING_EXCEPTION)); 550 vcpu_set_flag(vcpu, INCREMENT_PC); 551 } 552 553 #define kvm_pend_exception(v, e) \ 554 do { \ 555 WARN_ON(vcpu_get_flag((v), INCREMENT_PC)); \ 556 vcpu_set_flag((v), PENDING_EXCEPTION); \ 557 vcpu_set_flag((v), e); \ 558 } while (0) 559 560 static __always_inline void kvm_write_cptr_el2(u64 val) 561 { 562 if (has_vhe() || has_hvhe()) 563 write_sysreg(val, cpacr_el1); 564 else 565 write_sysreg(val, cptr_el2); 566 } 567 568 static __always_inline u64 kvm_get_reset_cptr_el2(struct kvm_vcpu *vcpu) 569 { 570 u64 val; 571 572 if (has_vhe()) { 573 val = (CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN | 574 CPACR_EL1_ZEN_EL1EN); 575 if (cpus_have_final_cap(ARM64_SME)) 576 val |= CPACR_EL1_SMEN_EL1EN; 577 } else if (has_hvhe()) { 578 val = (CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN); 579 580 if (!vcpu_has_sve(vcpu) || !guest_owns_fp_regs()) 581 val |= CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN; 582 if (cpus_have_final_cap(ARM64_SME)) 583 val |= CPACR_EL1_SMEN_EL1EN | CPACR_EL1_SMEN_EL0EN; 584 } else { 585 val = CPTR_NVHE_EL2_RES1; 586 587 if (vcpu_has_sve(vcpu) && guest_owns_fp_regs()) 588 val |= CPTR_EL2_TZ; 589 if (cpus_have_final_cap(ARM64_SME)) 590 val &= ~CPTR_EL2_TSM; 591 } 592 593 return val; 594 } 595 596 static __always_inline void kvm_reset_cptr_el2(struct kvm_vcpu *vcpu) 597 { 598 u64 val = kvm_get_reset_cptr_el2(vcpu); 599 600 kvm_write_cptr_el2(val); 601 } 602 #endif /* __ARM64_KVM_EMULATE_H__ */ 603