1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Based on arch/arm/include/asm/io.h 4 * 5 * Copyright (C) 1996-2000 Russell King 6 * Copyright (C) 2012 ARM Ltd. 7 */ 8 #ifndef __ASM_IO_H 9 #define __ASM_IO_H 10 11 #include <linux/types.h> 12 #include <linux/pgtable.h> 13 14 #include <asm/byteorder.h> 15 #include <asm/barrier.h> 16 #include <asm/memory.h> 17 #include <asm/early_ioremap.h> 18 #include <asm/alternative.h> 19 #include <asm/cpufeature.h> 20 #include <asm/rsi.h> 21 22 /* 23 * Generic IO read/write. These perform native-endian accesses. 24 */ 25 #define __raw_writeb __raw_writeb 26 static __always_inline void __raw_writeb(u8 val, volatile void __iomem *addr) 27 { 28 volatile u8 __iomem *ptr = addr; 29 asm volatile("strb %w0, %1" : : "rZ" (val), "Qo" (*ptr)); 30 } 31 32 #define __raw_writew __raw_writew 33 static __always_inline void __raw_writew(u16 val, volatile void __iomem *addr) 34 { 35 volatile u16 __iomem *ptr = addr; 36 asm volatile("strh %w0, %1" : : "rZ" (val), "Qo" (*ptr)); 37 } 38 39 #define __raw_writel __raw_writel 40 static __always_inline void __raw_writel(u32 val, volatile void __iomem *addr) 41 { 42 volatile u32 __iomem *ptr = addr; 43 asm volatile("str %w0, %1" : : "rZ" (val), "Qo" (*ptr)); 44 } 45 46 #define __raw_writeq __raw_writeq 47 static __always_inline void __raw_writeq(u64 val, volatile void __iomem *addr) 48 { 49 volatile u64 __iomem *ptr = addr; 50 asm volatile("str %x0, %1" : : "rZ" (val), "Qo" (*ptr)); 51 } 52 53 #define __raw_readb __raw_readb 54 static __always_inline u8 __raw_readb(const volatile void __iomem *addr) 55 { 56 u8 val; 57 asm volatile(ALTERNATIVE("nop", "dmb osh", 58 ARM64_WORKAROUND_NVIDIA_OLYMPUS_1027) 59 ALTERNATIVE("ldrb %w0, [%1]", 60 "ldarb %w0, [%1]", 61 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) 62 : "=r" (val) : "r" (addr)); 63 return val; 64 } 65 66 #define __raw_readw __raw_readw 67 static __always_inline u16 __raw_readw(const volatile void __iomem *addr) 68 { 69 u16 val; 70 71 asm volatile(ALTERNATIVE("nop", "dmb osh", 72 ARM64_WORKAROUND_NVIDIA_OLYMPUS_1027) 73 ALTERNATIVE("ldrh %w0, [%1]", 74 "ldarh %w0, [%1]", 75 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) 76 : "=r" (val) : "r" (addr)); 77 return val; 78 } 79 80 #define __raw_readl __raw_readl 81 static __always_inline u32 __raw_readl(const volatile void __iomem *addr) 82 { 83 u32 val; 84 asm volatile(ALTERNATIVE("nop", "dmb osh", 85 ARM64_WORKAROUND_NVIDIA_OLYMPUS_1027) 86 ALTERNATIVE("ldr %w0, [%1]", 87 "ldar %w0, [%1]", 88 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) 89 : "=r" (val) : "r" (addr)); 90 return val; 91 } 92 93 #define __raw_readq __raw_readq 94 static __always_inline u64 __raw_readq(const volatile void __iomem *addr) 95 { 96 u64 val; 97 asm volatile(ALTERNATIVE("nop", "dmb osh", 98 ARM64_WORKAROUND_NVIDIA_OLYMPUS_1027) 99 ALTERNATIVE("ldr %0, [%1]", 100 "ldar %0, [%1]", 101 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) 102 : "=r" (val) : "r" (addr)); 103 return val; 104 } 105 106 /* IO barriers */ 107 #define __io_ar(v) \ 108 ({ \ 109 unsigned long tmp; \ 110 \ 111 dma_rmb(); \ 112 \ 113 /* \ 114 * Create a dummy control dependency from the IO read to any \ 115 * later instructions. This ensures that a subsequent call to \ 116 * udelay() will be ordered due to the ISB in get_cycles(). \ 117 */ \ 118 asm volatile("eor %0, %1, %1\n" \ 119 "cbnz %0, ." \ 120 : "=r" (tmp) : "r" ((unsigned long)(v)) \ 121 : "memory"); \ 122 }) 123 124 #define __io_bw() dma_wmb() 125 #define __io_br(v) 126 #define __io_aw(v) 127 128 /* arm64-specific, don't use in portable drivers */ 129 #define __iormb(v) __io_ar(v) 130 #define __iowmb() __io_bw() 131 #define __iomb() dma_mb() 132 133 /* 134 * I/O port access primitives. 135 */ 136 #define arch_has_dev_port() (1) 137 #define IO_SPACE_LIMIT (PCI_IO_SIZE - 1) 138 #define PCI_IOBASE ((void __iomem *)PCI_IO_START) 139 140 /* 141 * The ARM64 iowrite implementation is intended to support drivers that want to 142 * use write combining. For instance PCI drivers using write combining with a 64 143 * byte __iowrite64_copy() expect to get a 64 byte MemWr TLP on the PCIe bus. 144 * 145 * Newer ARM core have sensitive write combining buffers, it is important that 146 * the stores be contiguous blocks of store instructions. Normal memcpy 147 * approaches have a very low chance to generate write combining. 148 * 149 * Since this is the only API on ARM64 that should be used with write combining 150 * it also integrates the DGH hint which is supposed to lower the latency to 151 * emit the large TLP from the CPU. 152 */ 153 154 static __always_inline void 155 __const_memcpy_toio_aligned32(volatile u32 __iomem *to, const u32 *from, 156 size_t count) 157 { 158 switch (count) { 159 case 8: 160 asm volatile("str %w0, [%8, #4 * 0]\n" 161 "str %w1, [%8, #4 * 1]\n" 162 "str %w2, [%8, #4 * 2]\n" 163 "str %w3, [%8, #4 * 3]\n" 164 "str %w4, [%8, #4 * 4]\n" 165 "str %w5, [%8, #4 * 5]\n" 166 "str %w6, [%8, #4 * 6]\n" 167 "str %w7, [%8, #4 * 7]\n" 168 : 169 : "rZ"(from[0]), "rZ"(from[1]), "rZ"(from[2]), 170 "rZ"(from[3]), "rZ"(from[4]), "rZ"(from[5]), 171 "rZ"(from[6]), "rZ"(from[7]), "r"(to)); 172 break; 173 case 4: 174 asm volatile("str %w0, [%4, #4 * 0]\n" 175 "str %w1, [%4, #4 * 1]\n" 176 "str %w2, [%4, #4 * 2]\n" 177 "str %w3, [%4, #4 * 3]\n" 178 : 179 : "rZ"(from[0]), "rZ"(from[1]), "rZ"(from[2]), 180 "rZ"(from[3]), "r"(to)); 181 break; 182 case 2: 183 asm volatile("str %w0, [%2, #4 * 0]\n" 184 "str %w1, [%2, #4 * 1]\n" 185 : 186 : "rZ"(from[0]), "rZ"(from[1]), "r"(to)); 187 break; 188 case 1: 189 __raw_writel(*from, to); 190 break; 191 default: 192 BUILD_BUG(); 193 } 194 } 195 196 void __iowrite32_copy_full(void __iomem *to, const void *from, size_t count); 197 198 static __always_inline void 199 __iowrite32_copy(void __iomem *to, const void *from, size_t count) 200 { 201 if (__builtin_constant_p(count) && 202 (count == 8 || count == 4 || count == 2 || count == 1)) { 203 __const_memcpy_toio_aligned32(to, from, count); 204 dgh(); 205 } else { 206 __iowrite32_copy_full(to, from, count); 207 } 208 } 209 #define __iowrite32_copy __iowrite32_copy 210 211 static __always_inline void 212 __const_memcpy_toio_aligned64(volatile u64 __iomem *to, const u64 *from, 213 size_t count) 214 { 215 switch (count) { 216 case 8: 217 asm volatile("str %x0, [%8, #8 * 0]\n" 218 "str %x1, [%8, #8 * 1]\n" 219 "str %x2, [%8, #8 * 2]\n" 220 "str %x3, [%8, #8 * 3]\n" 221 "str %x4, [%8, #8 * 4]\n" 222 "str %x5, [%8, #8 * 5]\n" 223 "str %x6, [%8, #8 * 6]\n" 224 "str %x7, [%8, #8 * 7]\n" 225 : 226 : "rZ"(from[0]), "rZ"(from[1]), "rZ"(from[2]), 227 "rZ"(from[3]), "rZ"(from[4]), "rZ"(from[5]), 228 "rZ"(from[6]), "rZ"(from[7]), "r"(to)); 229 break; 230 case 4: 231 asm volatile("str %x0, [%4, #8 * 0]\n" 232 "str %x1, [%4, #8 * 1]\n" 233 "str %x2, [%4, #8 * 2]\n" 234 "str %x3, [%4, #8 * 3]\n" 235 : 236 : "rZ"(from[0]), "rZ"(from[1]), "rZ"(from[2]), 237 "rZ"(from[3]), "r"(to)); 238 break; 239 case 2: 240 asm volatile("str %x0, [%2, #8 * 0]\n" 241 "str %x1, [%2, #8 * 1]\n" 242 : 243 : "rZ"(from[0]), "rZ"(from[1]), "r"(to)); 244 break; 245 case 1: 246 __raw_writeq(*from, to); 247 break; 248 default: 249 BUILD_BUG(); 250 } 251 } 252 253 void __iowrite64_copy_full(void __iomem *to, const void *from, size_t count); 254 255 static __always_inline void 256 __iowrite64_copy(void __iomem *to, const void *from, size_t count) 257 { 258 if (__builtin_constant_p(count) && 259 (count == 8 || count == 4 || count == 2 || count == 1)) { 260 __const_memcpy_toio_aligned64(to, from, count); 261 dgh(); 262 } else { 263 __iowrite64_copy_full(to, from, count); 264 } 265 } 266 #define __iowrite64_copy __iowrite64_copy 267 268 /* 269 * I/O memory mapping functions. 270 */ 271 272 typedef int (*ioremap_prot_hook_t)(phys_addr_t phys_addr, size_t size, 273 pgprot_t *prot); 274 int arm64_ioremap_prot_hook_register(const ioremap_prot_hook_t hook); 275 void __iomem *__ioremap_prot(phys_addr_t phys, size_t size, pgprot_t prot); 276 277 static inline void __iomem *ioremap_prot(phys_addr_t phys, size_t size, 278 pgprot_t user_prot) 279 { 280 pgprot_t prot; 281 ptval_t user_prot_val = pgprot_val(user_prot); 282 283 if (WARN_ON_ONCE(!(user_prot_val & PTE_USER))) 284 return NULL; 285 286 prot = __pgprot_modify(PAGE_KERNEL, PTE_ATTRINDX_MASK, 287 user_prot_val & PTE_ATTRINDX_MASK); 288 return __ioremap_prot(phys, size, prot); 289 } 290 #define ioremap_prot ioremap_prot 291 292 #define ioremap(addr, size) \ 293 __ioremap_prot((addr), (size), __pgprot(PROT_DEVICE_nGnRE)) 294 #define ioremap_wc(addr, size) \ 295 __ioremap_prot((addr), (size), __pgprot(PROT_NORMAL_NC)) 296 #define ioremap_np(addr, size) \ 297 __ioremap_prot((addr), (size), __pgprot(PROT_DEVICE_nGnRnE)) 298 299 300 #define ioremap_encrypted(addr, size) \ 301 __ioremap_prot((addr), (size), PAGE_KERNEL) 302 303 /* 304 * io{read,write}{16,32,64}be() macros 305 */ 306 #define ioread16be(p) ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(__v); __v; }) 307 #define ioread32be(p) ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(__v); __v; }) 308 #define ioread64be(p) ({ __u64 __v = be64_to_cpu((__force __be64)__raw_readq(p)); __iormb(__v); __v; }) 309 310 #define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); }) 311 #define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); }) 312 #define iowrite64be(v,p) ({ __iowmb(); __raw_writeq((__force __u64)cpu_to_be64(v), p); }) 313 314 #include <asm-generic/io.h> 315 316 #define ioremap_cache ioremap_cache 317 static inline void __iomem *ioremap_cache(phys_addr_t addr, size_t size) 318 { 319 if (pfn_is_map_memory(__phys_to_pfn(addr))) 320 return (void __iomem *)__phys_to_virt(addr); 321 322 return __ioremap_prot(addr, size, __pgprot(PROT_NORMAL)); 323 } 324 325 /* 326 * More restrictive address range checking than the default implementation 327 * (PHYS_OFFSET and PHYS_MASK taken into account). 328 */ 329 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE 330 extern int valid_phys_addr_range(phys_addr_t addr, size_t size); 331 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); 332 333 extern bool arch_memremap_can_ram_remap(resource_size_t offset, size_t size, 334 unsigned long flags); 335 #define arch_memremap_can_ram_remap arch_memremap_can_ram_remap 336 337 static inline bool arm64_is_protected_mmio(phys_addr_t phys_addr, size_t size) 338 { 339 if (unlikely(is_realm_world())) 340 return arm64_rsi_is_protected(phys_addr, size); 341 return false; 342 } 343 344 #endif /* __ASM_IO_H */ 345