1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Based on arch/arm/include/asm/io.h 4 * 5 * Copyright (C) 1996-2000 Russell King 6 * Copyright (C) 2012 ARM Ltd. 7 */ 8 #ifndef __ASM_IO_H 9 #define __ASM_IO_H 10 11 #include <linux/types.h> 12 #include <linux/pgtable.h> 13 14 #include <asm/byteorder.h> 15 #include <asm/barrier.h> 16 #include <asm/memory.h> 17 #include <asm/early_ioremap.h> 18 #include <asm/alternative.h> 19 #include <asm/cpufeature.h> 20 21 /* 22 * Generic IO read/write. These perform native-endian accesses. 23 */ 24 #define __raw_writeb __raw_writeb 25 static inline void __raw_writeb(u8 val, volatile void __iomem *addr) 26 { 27 asm volatile("strb %w0, [%1]" : : "rZ" (val), "r" (addr)); 28 } 29 30 #define __raw_writew __raw_writew 31 static inline void __raw_writew(u16 val, volatile void __iomem *addr) 32 { 33 asm volatile("strh %w0, [%1]" : : "rZ" (val), "r" (addr)); 34 } 35 36 #define __raw_writel __raw_writel 37 static __always_inline void __raw_writel(u32 val, volatile void __iomem *addr) 38 { 39 asm volatile("str %w0, [%1]" : : "rZ" (val), "r" (addr)); 40 } 41 42 #define __raw_writeq __raw_writeq 43 static inline void __raw_writeq(u64 val, volatile void __iomem *addr) 44 { 45 asm volatile("str %x0, [%1]" : : "rZ" (val), "r" (addr)); 46 } 47 48 #define __raw_readb __raw_readb 49 static inline u8 __raw_readb(const volatile void __iomem *addr) 50 { 51 u8 val; 52 asm volatile(ALTERNATIVE("ldrb %w0, [%1]", 53 "ldarb %w0, [%1]", 54 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) 55 : "=r" (val) : "r" (addr)); 56 return val; 57 } 58 59 #define __raw_readw __raw_readw 60 static inline u16 __raw_readw(const volatile void __iomem *addr) 61 { 62 u16 val; 63 64 asm volatile(ALTERNATIVE("ldrh %w0, [%1]", 65 "ldarh %w0, [%1]", 66 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) 67 : "=r" (val) : "r" (addr)); 68 return val; 69 } 70 71 #define __raw_readl __raw_readl 72 static __always_inline u32 __raw_readl(const volatile void __iomem *addr) 73 { 74 u32 val; 75 asm volatile(ALTERNATIVE("ldr %w0, [%1]", 76 "ldar %w0, [%1]", 77 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) 78 : "=r" (val) : "r" (addr)); 79 return val; 80 } 81 82 #define __raw_readq __raw_readq 83 static inline u64 __raw_readq(const volatile void __iomem *addr) 84 { 85 u64 val; 86 asm volatile(ALTERNATIVE("ldr %0, [%1]", 87 "ldar %0, [%1]", 88 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) 89 : "=r" (val) : "r" (addr)); 90 return val; 91 } 92 93 /* IO barriers */ 94 #define __iormb(v) \ 95 ({ \ 96 unsigned long tmp; \ 97 \ 98 dma_rmb(); \ 99 \ 100 /* \ 101 * Create a dummy control dependency from the IO read to any \ 102 * later instructions. This ensures that a subsequent call to \ 103 * udelay() will be ordered due to the ISB in get_cycles(). \ 104 */ \ 105 asm volatile("eor %0, %1, %1\n" \ 106 "cbnz %0, ." \ 107 : "=r" (tmp) : "r" ((unsigned long)(v)) \ 108 : "memory"); \ 109 }) 110 111 #define __io_par(v) __iormb(v) 112 #define __iowmb() dma_wmb() 113 114 /* 115 * Relaxed I/O memory access primitives. These follow the Device memory 116 * ordering rules but do not guarantee any ordering relative to Normal memory 117 * accesses. 118 */ 119 #define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; }) 120 #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; }) 121 #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; }) 122 #define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; }) 123 124 #define writeb_relaxed(v,c) ((void)__raw_writeb((v),(c))) 125 #define writew_relaxed(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(c))) 126 #define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c))) 127 #define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c))) 128 129 /* 130 * I/O memory access primitives. Reads are ordered relative to any 131 * following Normal memory access. Writes are ordered relative to any prior 132 * Normal memory access. 133 */ 134 #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(__v); __v; }) 135 #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(__v); __v; }) 136 #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(__v); __v; }) 137 #define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(__v); __v; }) 138 139 #define writeb(v,c) ({ __iowmb(); writeb_relaxed((v),(c)); }) 140 #define writew(v,c) ({ __iowmb(); writew_relaxed((v),(c)); }) 141 #define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c)); }) 142 #define writeq(v,c) ({ __iowmb(); writeq_relaxed((v),(c)); }) 143 144 /* 145 * I/O port access primitives. 146 */ 147 #define arch_has_dev_port() (1) 148 #define IO_SPACE_LIMIT (PCI_IO_SIZE - 1) 149 #define PCI_IOBASE ((void __iomem *)PCI_IO_START) 150 151 /* 152 * String version of I/O memory access operations. 153 */ 154 extern void __memcpy_fromio(void *, const volatile void __iomem *, size_t); 155 extern void __memcpy_toio(volatile void __iomem *, const void *, size_t); 156 extern void __memset_io(volatile void __iomem *, int, size_t); 157 158 #define memset_io(c,v,l) __memset_io((c),(v),(l)) 159 #define memcpy_fromio(a,c,l) __memcpy_fromio((a),(c),(l)) 160 #define memcpy_toio(c,a,l) __memcpy_toio((c),(a),(l)) 161 162 /* 163 * I/O memory mapping functions. 164 */ 165 extern void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot); 166 extern void iounmap(volatile void __iomem *addr); 167 extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size); 168 169 #define ioremap(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE)) 170 #define ioremap_wc(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC)) 171 172 /* 173 * PCI configuration space mapping function. 174 * 175 * The PCI specification disallows posted write configuration transactions. 176 * Add an arch specific pci_remap_cfgspace() definition that is implemented 177 * through nGnRnE device memory attribute as recommended by the ARM v8 178 * Architecture reference manual Issue A.k B2.8.2 "Device memory". 179 */ 180 #define pci_remap_cfgspace(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRnE)) 181 182 /* 183 * io{read,write}{16,32,64}be() macros 184 */ 185 #define ioread16be(p) ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(__v); __v; }) 186 #define ioread32be(p) ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(__v); __v; }) 187 #define ioread64be(p) ({ __u64 __v = be64_to_cpu((__force __be64)__raw_readq(p)); __iormb(__v); __v; }) 188 189 #define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); }) 190 #define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); }) 191 #define iowrite64be(v,p) ({ __iowmb(); __raw_writeq((__force __u64)cpu_to_be64(v), p); }) 192 193 #include <asm-generic/io.h> 194 195 /* 196 * More restrictive address range checking than the default implementation 197 * (PHYS_OFFSET and PHYS_MASK taken into account). 198 */ 199 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE 200 extern int valid_phys_addr_range(phys_addr_t addr, size_t size); 201 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); 202 203 extern int devmem_is_allowed(unsigned long pfn); 204 205 #endif /* __ASM_IO_H */ 206