1 /* 2 * Copyright (C) 2013 Huawei Ltd. 3 * Author: Jiang Liu <liuj97@gmail.com> 4 * 5 * Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef __ASM_INSN_H 20 #define __ASM_INSN_H 21 #include <linux/types.h> 22 23 /* A64 instructions are always 32 bits. */ 24 #define AARCH64_INSN_SIZE 4 25 26 #ifndef __ASSEMBLY__ 27 /* 28 * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a 29 * Section C3.1 "A64 instruction index by encoding": 30 * AArch64 main encoding table 31 * Bit position 32 * 28 27 26 25 Encoding Group 33 * 0 0 - - Unallocated 34 * 1 0 0 - Data processing, immediate 35 * 1 0 1 - Branch, exception generation and system instructions 36 * - 1 - 0 Loads and stores 37 * - 1 0 1 Data processing - register 38 * 0 1 1 1 Data processing - SIMD and floating point 39 * 1 1 1 1 Data processing - SIMD and floating point 40 * "-" means "don't care" 41 */ 42 enum aarch64_insn_encoding_class { 43 AARCH64_INSN_CLS_UNKNOWN, /* UNALLOCATED */ 44 AARCH64_INSN_CLS_DP_IMM, /* Data processing - immediate */ 45 AARCH64_INSN_CLS_DP_REG, /* Data processing - register */ 46 AARCH64_INSN_CLS_DP_FPSIMD, /* Data processing - SIMD and FP */ 47 AARCH64_INSN_CLS_LDST, /* Loads and stores */ 48 AARCH64_INSN_CLS_BR_SYS, /* Branch, exception generation and 49 * system instructions */ 50 }; 51 52 enum aarch64_insn_hint_op { 53 AARCH64_INSN_HINT_NOP = 0x0 << 5, 54 AARCH64_INSN_HINT_YIELD = 0x1 << 5, 55 AARCH64_INSN_HINT_WFE = 0x2 << 5, 56 AARCH64_INSN_HINT_WFI = 0x3 << 5, 57 AARCH64_INSN_HINT_SEV = 0x4 << 5, 58 AARCH64_INSN_HINT_SEVL = 0x5 << 5, 59 }; 60 61 enum aarch64_insn_imm_type { 62 AARCH64_INSN_IMM_ADR, 63 AARCH64_INSN_IMM_26, 64 AARCH64_INSN_IMM_19, 65 AARCH64_INSN_IMM_16, 66 AARCH64_INSN_IMM_14, 67 AARCH64_INSN_IMM_12, 68 AARCH64_INSN_IMM_9, 69 AARCH64_INSN_IMM_7, 70 AARCH64_INSN_IMM_6, 71 AARCH64_INSN_IMM_S, 72 AARCH64_INSN_IMM_R, 73 AARCH64_INSN_IMM_N, 74 AARCH64_INSN_IMM_MAX 75 }; 76 77 enum aarch64_insn_register_type { 78 AARCH64_INSN_REGTYPE_RT, 79 AARCH64_INSN_REGTYPE_RN, 80 AARCH64_INSN_REGTYPE_RT2, 81 AARCH64_INSN_REGTYPE_RM, 82 AARCH64_INSN_REGTYPE_RD, 83 AARCH64_INSN_REGTYPE_RA, 84 AARCH64_INSN_REGTYPE_RS, 85 }; 86 87 enum aarch64_insn_register { 88 AARCH64_INSN_REG_0 = 0, 89 AARCH64_INSN_REG_1 = 1, 90 AARCH64_INSN_REG_2 = 2, 91 AARCH64_INSN_REG_3 = 3, 92 AARCH64_INSN_REG_4 = 4, 93 AARCH64_INSN_REG_5 = 5, 94 AARCH64_INSN_REG_6 = 6, 95 AARCH64_INSN_REG_7 = 7, 96 AARCH64_INSN_REG_8 = 8, 97 AARCH64_INSN_REG_9 = 9, 98 AARCH64_INSN_REG_10 = 10, 99 AARCH64_INSN_REG_11 = 11, 100 AARCH64_INSN_REG_12 = 12, 101 AARCH64_INSN_REG_13 = 13, 102 AARCH64_INSN_REG_14 = 14, 103 AARCH64_INSN_REG_15 = 15, 104 AARCH64_INSN_REG_16 = 16, 105 AARCH64_INSN_REG_17 = 17, 106 AARCH64_INSN_REG_18 = 18, 107 AARCH64_INSN_REG_19 = 19, 108 AARCH64_INSN_REG_20 = 20, 109 AARCH64_INSN_REG_21 = 21, 110 AARCH64_INSN_REG_22 = 22, 111 AARCH64_INSN_REG_23 = 23, 112 AARCH64_INSN_REG_24 = 24, 113 AARCH64_INSN_REG_25 = 25, 114 AARCH64_INSN_REG_26 = 26, 115 AARCH64_INSN_REG_27 = 27, 116 AARCH64_INSN_REG_28 = 28, 117 AARCH64_INSN_REG_29 = 29, 118 AARCH64_INSN_REG_FP = 29, /* Frame pointer */ 119 AARCH64_INSN_REG_30 = 30, 120 AARCH64_INSN_REG_LR = 30, /* Link register */ 121 AARCH64_INSN_REG_ZR = 31, /* Zero: as source register */ 122 AARCH64_INSN_REG_SP = 31 /* Stack pointer: as load/store base reg */ 123 }; 124 125 enum aarch64_insn_special_register { 126 AARCH64_INSN_SPCLREG_SPSR_EL1 = 0xC200, 127 AARCH64_INSN_SPCLREG_ELR_EL1 = 0xC201, 128 AARCH64_INSN_SPCLREG_SP_EL0 = 0xC208, 129 AARCH64_INSN_SPCLREG_SPSEL = 0xC210, 130 AARCH64_INSN_SPCLREG_CURRENTEL = 0xC212, 131 AARCH64_INSN_SPCLREG_DAIF = 0xDA11, 132 AARCH64_INSN_SPCLREG_NZCV = 0xDA10, 133 AARCH64_INSN_SPCLREG_FPCR = 0xDA20, 134 AARCH64_INSN_SPCLREG_DSPSR_EL0 = 0xDA28, 135 AARCH64_INSN_SPCLREG_DLR_EL0 = 0xDA29, 136 AARCH64_INSN_SPCLREG_SPSR_EL2 = 0xE200, 137 AARCH64_INSN_SPCLREG_ELR_EL2 = 0xE201, 138 AARCH64_INSN_SPCLREG_SP_EL1 = 0xE208, 139 AARCH64_INSN_SPCLREG_SPSR_INQ = 0xE218, 140 AARCH64_INSN_SPCLREG_SPSR_ABT = 0xE219, 141 AARCH64_INSN_SPCLREG_SPSR_UND = 0xE21A, 142 AARCH64_INSN_SPCLREG_SPSR_FIQ = 0xE21B, 143 AARCH64_INSN_SPCLREG_SPSR_EL3 = 0xF200, 144 AARCH64_INSN_SPCLREG_ELR_EL3 = 0xF201, 145 AARCH64_INSN_SPCLREG_SP_EL2 = 0xF210 146 }; 147 148 enum aarch64_insn_variant { 149 AARCH64_INSN_VARIANT_32BIT, 150 AARCH64_INSN_VARIANT_64BIT 151 }; 152 153 enum aarch64_insn_condition { 154 AARCH64_INSN_COND_EQ = 0x0, /* == */ 155 AARCH64_INSN_COND_NE = 0x1, /* != */ 156 AARCH64_INSN_COND_CS = 0x2, /* unsigned >= */ 157 AARCH64_INSN_COND_CC = 0x3, /* unsigned < */ 158 AARCH64_INSN_COND_MI = 0x4, /* < 0 */ 159 AARCH64_INSN_COND_PL = 0x5, /* >= 0 */ 160 AARCH64_INSN_COND_VS = 0x6, /* overflow */ 161 AARCH64_INSN_COND_VC = 0x7, /* no overflow */ 162 AARCH64_INSN_COND_HI = 0x8, /* unsigned > */ 163 AARCH64_INSN_COND_LS = 0x9, /* unsigned <= */ 164 AARCH64_INSN_COND_GE = 0xa, /* signed >= */ 165 AARCH64_INSN_COND_LT = 0xb, /* signed < */ 166 AARCH64_INSN_COND_GT = 0xc, /* signed > */ 167 AARCH64_INSN_COND_LE = 0xd, /* signed <= */ 168 AARCH64_INSN_COND_AL = 0xe, /* always */ 169 }; 170 171 enum aarch64_insn_branch_type { 172 AARCH64_INSN_BRANCH_NOLINK, 173 AARCH64_INSN_BRANCH_LINK, 174 AARCH64_INSN_BRANCH_RETURN, 175 AARCH64_INSN_BRANCH_COMP_ZERO, 176 AARCH64_INSN_BRANCH_COMP_NONZERO, 177 }; 178 179 enum aarch64_insn_size_type { 180 AARCH64_INSN_SIZE_8, 181 AARCH64_INSN_SIZE_16, 182 AARCH64_INSN_SIZE_32, 183 AARCH64_INSN_SIZE_64, 184 }; 185 186 enum aarch64_insn_ldst_type { 187 AARCH64_INSN_LDST_LOAD_REG_OFFSET, 188 AARCH64_INSN_LDST_STORE_REG_OFFSET, 189 AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX, 190 AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX, 191 AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX, 192 AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX, 193 AARCH64_INSN_LDST_LOAD_EX, 194 AARCH64_INSN_LDST_STORE_EX, 195 }; 196 197 enum aarch64_insn_adsb_type { 198 AARCH64_INSN_ADSB_ADD, 199 AARCH64_INSN_ADSB_SUB, 200 AARCH64_INSN_ADSB_ADD_SETFLAGS, 201 AARCH64_INSN_ADSB_SUB_SETFLAGS 202 }; 203 204 enum aarch64_insn_movewide_type { 205 AARCH64_INSN_MOVEWIDE_ZERO, 206 AARCH64_INSN_MOVEWIDE_KEEP, 207 AARCH64_INSN_MOVEWIDE_INVERSE 208 }; 209 210 enum aarch64_insn_bitfield_type { 211 AARCH64_INSN_BITFIELD_MOVE, 212 AARCH64_INSN_BITFIELD_MOVE_UNSIGNED, 213 AARCH64_INSN_BITFIELD_MOVE_SIGNED 214 }; 215 216 enum aarch64_insn_data1_type { 217 AARCH64_INSN_DATA1_REVERSE_16, 218 AARCH64_INSN_DATA1_REVERSE_32, 219 AARCH64_INSN_DATA1_REVERSE_64, 220 }; 221 222 enum aarch64_insn_data2_type { 223 AARCH64_INSN_DATA2_UDIV, 224 AARCH64_INSN_DATA2_SDIV, 225 AARCH64_INSN_DATA2_LSLV, 226 AARCH64_INSN_DATA2_LSRV, 227 AARCH64_INSN_DATA2_ASRV, 228 AARCH64_INSN_DATA2_RORV, 229 }; 230 231 enum aarch64_insn_data3_type { 232 AARCH64_INSN_DATA3_MADD, 233 AARCH64_INSN_DATA3_MSUB, 234 }; 235 236 enum aarch64_insn_logic_type { 237 AARCH64_INSN_LOGIC_AND, 238 AARCH64_INSN_LOGIC_BIC, 239 AARCH64_INSN_LOGIC_ORR, 240 AARCH64_INSN_LOGIC_ORN, 241 AARCH64_INSN_LOGIC_EOR, 242 AARCH64_INSN_LOGIC_EON, 243 AARCH64_INSN_LOGIC_AND_SETFLAGS, 244 AARCH64_INSN_LOGIC_BIC_SETFLAGS 245 }; 246 247 enum aarch64_insn_prfm_type { 248 AARCH64_INSN_PRFM_TYPE_PLD, 249 AARCH64_INSN_PRFM_TYPE_PLI, 250 AARCH64_INSN_PRFM_TYPE_PST, 251 }; 252 253 enum aarch64_insn_prfm_target { 254 AARCH64_INSN_PRFM_TARGET_L1, 255 AARCH64_INSN_PRFM_TARGET_L2, 256 AARCH64_INSN_PRFM_TARGET_L3, 257 }; 258 259 enum aarch64_insn_prfm_policy { 260 AARCH64_INSN_PRFM_POLICY_KEEP, 261 AARCH64_INSN_PRFM_POLICY_STRM, 262 }; 263 264 enum aarch64_insn_adr_type { 265 AARCH64_INSN_ADR_TYPE_ADRP, 266 AARCH64_INSN_ADR_TYPE_ADR, 267 }; 268 269 #define __AARCH64_INSN_FUNCS(abbr, mask, val) \ 270 static __always_inline bool aarch64_insn_is_##abbr(u32 code) \ 271 { return (code & (mask)) == (val); } \ 272 static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \ 273 { return (val); } 274 275 __AARCH64_INSN_FUNCS(adr, 0x9F000000, 0x10000000) 276 __AARCH64_INSN_FUNCS(adrp, 0x9F000000, 0x90000000) 277 __AARCH64_INSN_FUNCS(prfm, 0x3FC00000, 0x39800000) 278 __AARCH64_INSN_FUNCS(prfm_lit, 0xFF000000, 0xD8000000) 279 __AARCH64_INSN_FUNCS(str_reg, 0x3FE0EC00, 0x38206800) 280 __AARCH64_INSN_FUNCS(ldr_reg, 0x3FE0EC00, 0x38606800) 281 __AARCH64_INSN_FUNCS(ldr_lit, 0xBF000000, 0x18000000) 282 __AARCH64_INSN_FUNCS(ldrsw_lit, 0xFF000000, 0x98000000) 283 __AARCH64_INSN_FUNCS(exclusive, 0x3F800000, 0x08000000) 284 __AARCH64_INSN_FUNCS(load_ex, 0x3F400000, 0x08400000) 285 __AARCH64_INSN_FUNCS(store_ex, 0x3F400000, 0x08000000) 286 __AARCH64_INSN_FUNCS(stp_post, 0x7FC00000, 0x28800000) 287 __AARCH64_INSN_FUNCS(ldp_post, 0x7FC00000, 0x28C00000) 288 __AARCH64_INSN_FUNCS(stp_pre, 0x7FC00000, 0x29800000) 289 __AARCH64_INSN_FUNCS(ldp_pre, 0x7FC00000, 0x29C00000) 290 __AARCH64_INSN_FUNCS(add_imm, 0x7F000000, 0x11000000) 291 __AARCH64_INSN_FUNCS(adds_imm, 0x7F000000, 0x31000000) 292 __AARCH64_INSN_FUNCS(sub_imm, 0x7F000000, 0x51000000) 293 __AARCH64_INSN_FUNCS(subs_imm, 0x7F000000, 0x71000000) 294 __AARCH64_INSN_FUNCS(movn, 0x7F800000, 0x12800000) 295 __AARCH64_INSN_FUNCS(sbfm, 0x7F800000, 0x13000000) 296 __AARCH64_INSN_FUNCS(bfm, 0x7F800000, 0x33000000) 297 __AARCH64_INSN_FUNCS(movz, 0x7F800000, 0x52800000) 298 __AARCH64_INSN_FUNCS(ubfm, 0x7F800000, 0x53000000) 299 __AARCH64_INSN_FUNCS(movk, 0x7F800000, 0x72800000) 300 __AARCH64_INSN_FUNCS(add, 0x7F200000, 0x0B000000) 301 __AARCH64_INSN_FUNCS(adds, 0x7F200000, 0x2B000000) 302 __AARCH64_INSN_FUNCS(sub, 0x7F200000, 0x4B000000) 303 __AARCH64_INSN_FUNCS(subs, 0x7F200000, 0x6B000000) 304 __AARCH64_INSN_FUNCS(madd, 0x7FE08000, 0x1B000000) 305 __AARCH64_INSN_FUNCS(msub, 0x7FE08000, 0x1B008000) 306 __AARCH64_INSN_FUNCS(udiv, 0x7FE0FC00, 0x1AC00800) 307 __AARCH64_INSN_FUNCS(sdiv, 0x7FE0FC00, 0x1AC00C00) 308 __AARCH64_INSN_FUNCS(lslv, 0x7FE0FC00, 0x1AC02000) 309 __AARCH64_INSN_FUNCS(lsrv, 0x7FE0FC00, 0x1AC02400) 310 __AARCH64_INSN_FUNCS(asrv, 0x7FE0FC00, 0x1AC02800) 311 __AARCH64_INSN_FUNCS(rorv, 0x7FE0FC00, 0x1AC02C00) 312 __AARCH64_INSN_FUNCS(rev16, 0x7FFFFC00, 0x5AC00400) 313 __AARCH64_INSN_FUNCS(rev32, 0x7FFFFC00, 0x5AC00800) 314 __AARCH64_INSN_FUNCS(rev64, 0x7FFFFC00, 0x5AC00C00) 315 __AARCH64_INSN_FUNCS(and, 0x7F200000, 0x0A000000) 316 __AARCH64_INSN_FUNCS(bic, 0x7F200000, 0x0A200000) 317 __AARCH64_INSN_FUNCS(orr, 0x7F200000, 0x2A000000) 318 __AARCH64_INSN_FUNCS(orn, 0x7F200000, 0x2A200000) 319 __AARCH64_INSN_FUNCS(eor, 0x7F200000, 0x4A000000) 320 __AARCH64_INSN_FUNCS(eon, 0x7F200000, 0x4A200000) 321 __AARCH64_INSN_FUNCS(ands, 0x7F200000, 0x6A000000) 322 __AARCH64_INSN_FUNCS(bics, 0x7F200000, 0x6A200000) 323 __AARCH64_INSN_FUNCS(and_imm, 0x7F800000, 0x12000000) 324 __AARCH64_INSN_FUNCS(orr_imm, 0x7F800000, 0x32000000) 325 __AARCH64_INSN_FUNCS(eor_imm, 0x7F800000, 0x52000000) 326 __AARCH64_INSN_FUNCS(ands_imm, 0x7F800000, 0x72000000) 327 __AARCH64_INSN_FUNCS(extr, 0x7FA00000, 0x13800000) 328 __AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000) 329 __AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000) 330 __AARCH64_INSN_FUNCS(cbz, 0x7F000000, 0x34000000) 331 __AARCH64_INSN_FUNCS(cbnz, 0x7F000000, 0x35000000) 332 __AARCH64_INSN_FUNCS(tbz, 0x7F000000, 0x36000000) 333 __AARCH64_INSN_FUNCS(tbnz, 0x7F000000, 0x37000000) 334 __AARCH64_INSN_FUNCS(bcond, 0xFF000010, 0x54000000) 335 __AARCH64_INSN_FUNCS(svc, 0xFFE0001F, 0xD4000001) 336 __AARCH64_INSN_FUNCS(hvc, 0xFFE0001F, 0xD4000002) 337 __AARCH64_INSN_FUNCS(smc, 0xFFE0001F, 0xD4000003) 338 __AARCH64_INSN_FUNCS(brk, 0xFFE0001F, 0xD4200000) 339 __AARCH64_INSN_FUNCS(exception, 0xFF000000, 0xD4000000) 340 __AARCH64_INSN_FUNCS(hint, 0xFFFFF01F, 0xD503201F) 341 __AARCH64_INSN_FUNCS(br, 0xFFFFFC1F, 0xD61F0000) 342 __AARCH64_INSN_FUNCS(blr, 0xFFFFFC1F, 0xD63F0000) 343 __AARCH64_INSN_FUNCS(ret, 0xFFFFFC1F, 0xD65F0000) 344 __AARCH64_INSN_FUNCS(eret, 0xFFFFFFFF, 0xD69F03E0) 345 __AARCH64_INSN_FUNCS(mrs, 0xFFF00000, 0xD5300000) 346 __AARCH64_INSN_FUNCS(msr_imm, 0xFFF8F01F, 0xD500401F) 347 __AARCH64_INSN_FUNCS(msr_reg, 0xFFF00000, 0xD5100000) 348 349 #undef __AARCH64_INSN_FUNCS 350 351 bool aarch64_insn_is_nop(u32 insn); 352 bool aarch64_insn_is_branch_imm(u32 insn); 353 354 static inline bool aarch64_insn_is_adr_adrp(u32 insn) 355 { 356 return aarch64_insn_is_adr(insn) || aarch64_insn_is_adrp(insn); 357 } 358 359 int aarch64_insn_read(void *addr, u32 *insnp); 360 int aarch64_insn_write(void *addr, u32 insn); 361 enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn); 362 bool aarch64_insn_uses_literal(u32 insn); 363 bool aarch64_insn_is_branch(u32 insn); 364 u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn); 365 u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type, 366 u32 insn, u64 imm); 367 u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type, 368 u32 insn); 369 u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr, 370 enum aarch64_insn_branch_type type); 371 u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr, 372 enum aarch64_insn_register reg, 373 enum aarch64_insn_variant variant, 374 enum aarch64_insn_branch_type type); 375 u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr, 376 enum aarch64_insn_condition cond); 377 u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_op op); 378 u32 aarch64_insn_gen_nop(void); 379 u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg, 380 enum aarch64_insn_branch_type type); 381 u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg, 382 enum aarch64_insn_register base, 383 enum aarch64_insn_register offset, 384 enum aarch64_insn_size_type size, 385 enum aarch64_insn_ldst_type type); 386 u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1, 387 enum aarch64_insn_register reg2, 388 enum aarch64_insn_register base, 389 int offset, 390 enum aarch64_insn_variant variant, 391 enum aarch64_insn_ldst_type type); 392 u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg, 393 enum aarch64_insn_register base, 394 enum aarch64_insn_register state, 395 enum aarch64_insn_size_type size, 396 enum aarch64_insn_ldst_type type); 397 u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst, 398 enum aarch64_insn_register src, 399 int imm, enum aarch64_insn_variant variant, 400 enum aarch64_insn_adsb_type type); 401 u32 aarch64_insn_gen_adr(unsigned long pc, unsigned long addr, 402 enum aarch64_insn_register reg, 403 enum aarch64_insn_adr_type type); 404 u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst, 405 enum aarch64_insn_register src, 406 int immr, int imms, 407 enum aarch64_insn_variant variant, 408 enum aarch64_insn_bitfield_type type); 409 u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst, 410 int imm, int shift, 411 enum aarch64_insn_variant variant, 412 enum aarch64_insn_movewide_type type); 413 u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst, 414 enum aarch64_insn_register src, 415 enum aarch64_insn_register reg, 416 int shift, 417 enum aarch64_insn_variant variant, 418 enum aarch64_insn_adsb_type type); 419 u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst, 420 enum aarch64_insn_register src, 421 enum aarch64_insn_variant variant, 422 enum aarch64_insn_data1_type type); 423 u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst, 424 enum aarch64_insn_register src, 425 enum aarch64_insn_register reg, 426 enum aarch64_insn_variant variant, 427 enum aarch64_insn_data2_type type); 428 u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst, 429 enum aarch64_insn_register src, 430 enum aarch64_insn_register reg1, 431 enum aarch64_insn_register reg2, 432 enum aarch64_insn_variant variant, 433 enum aarch64_insn_data3_type type); 434 u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst, 435 enum aarch64_insn_register src, 436 enum aarch64_insn_register reg, 437 int shift, 438 enum aarch64_insn_variant variant, 439 enum aarch64_insn_logic_type type); 440 u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type, 441 enum aarch64_insn_variant variant, 442 enum aarch64_insn_register Rn, 443 enum aarch64_insn_register Rd, 444 u64 imm); 445 u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant, 446 enum aarch64_insn_register Rm, 447 enum aarch64_insn_register Rn, 448 enum aarch64_insn_register Rd, 449 u8 lsb); 450 u32 aarch64_insn_gen_prefetch(enum aarch64_insn_register base, 451 enum aarch64_insn_prfm_type type, 452 enum aarch64_insn_prfm_target target, 453 enum aarch64_insn_prfm_policy policy); 454 s32 aarch64_get_branch_offset(u32 insn); 455 u32 aarch64_set_branch_offset(u32 insn, s32 offset); 456 457 int aarch64_insn_patch_text_nosync(void *addr, u32 insn); 458 int aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt); 459 460 s32 aarch64_insn_adrp_get_offset(u32 insn); 461 u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset); 462 463 bool aarch32_insn_is_wide(u32 insn); 464 465 #define A32_RN_OFFSET 16 466 #define A32_RT_OFFSET 12 467 #define A32_RT2_OFFSET 0 468 469 u32 aarch64_insn_extract_system_reg(u32 insn); 470 u32 aarch32_insn_extract_reg_num(u32 insn, int offset); 471 u32 aarch32_insn_mcr_extract_opc2(u32 insn); 472 u32 aarch32_insn_mcr_extract_crm(u32 insn); 473 474 typedef bool (pstate_check_t)(unsigned long); 475 extern pstate_check_t * const aarch32_opcode_cond_checks[16]; 476 #endif /* __ASSEMBLY__ */ 477 478 #endif /* __ASM_INSN_H */ 479