1 /* 2 * Copyright (C) 2012 ARM Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 #ifndef __ASM_HW_BREAKPOINT_H 17 #define __ASM_HW_BREAKPOINT_H 18 19 #include <asm/cputype.h> 20 21 #ifdef __KERNEL__ 22 23 struct arch_hw_breakpoint_ctrl { 24 u32 __reserved : 19, 25 len : 8, 26 type : 2, 27 privilege : 2, 28 enabled : 1; 29 }; 30 31 struct arch_hw_breakpoint { 32 u64 address; 33 u64 trigger; 34 struct arch_hw_breakpoint_ctrl ctrl; 35 }; 36 37 static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl) 38 { 39 return (ctrl.len << 5) | (ctrl.type << 3) | (ctrl.privilege << 1) | 40 ctrl.enabled; 41 } 42 43 static inline void decode_ctrl_reg(u32 reg, 44 struct arch_hw_breakpoint_ctrl *ctrl) 45 { 46 ctrl->enabled = reg & 0x1; 47 reg >>= 1; 48 ctrl->privilege = reg & 0x3; 49 reg >>= 2; 50 ctrl->type = reg & 0x3; 51 reg >>= 2; 52 ctrl->len = reg & 0xff; 53 } 54 55 /* Breakpoint */ 56 #define ARM_BREAKPOINT_EXECUTE 0 57 58 /* Watchpoints */ 59 #define ARM_BREAKPOINT_LOAD 1 60 #define ARM_BREAKPOINT_STORE 2 61 #define AARCH64_ESR_ACCESS_MASK (1 << 6) 62 63 /* Privilege Levels */ 64 #define AARCH64_BREAKPOINT_EL1 1 65 #define AARCH64_BREAKPOINT_EL0 2 66 67 /* Lengths */ 68 #define ARM_BREAKPOINT_LEN_1 0x1 69 #define ARM_BREAKPOINT_LEN_2 0x3 70 #define ARM_BREAKPOINT_LEN_4 0xf 71 #define ARM_BREAKPOINT_LEN_8 0xff 72 73 /* Kernel stepping */ 74 #define ARM_KERNEL_STEP_NONE 0 75 #define ARM_KERNEL_STEP_ACTIVE 1 76 #define ARM_KERNEL_STEP_SUSPEND 2 77 78 /* 79 * Limits. 80 * Changing these will require modifications to the register accessors. 81 */ 82 #define ARM_MAX_BRP 16 83 #define ARM_MAX_WRP 16 84 85 /* Virtual debug register bases. */ 86 #define AARCH64_DBG_REG_BVR 0 87 #define AARCH64_DBG_REG_BCR (AARCH64_DBG_REG_BVR + ARM_MAX_BRP) 88 #define AARCH64_DBG_REG_WVR (AARCH64_DBG_REG_BCR + ARM_MAX_BRP) 89 #define AARCH64_DBG_REG_WCR (AARCH64_DBG_REG_WVR + ARM_MAX_WRP) 90 91 /* Debug register names. */ 92 #define AARCH64_DBG_REG_NAME_BVR "bvr" 93 #define AARCH64_DBG_REG_NAME_BCR "bcr" 94 #define AARCH64_DBG_REG_NAME_WVR "wvr" 95 #define AARCH64_DBG_REG_NAME_WCR "wcr" 96 97 /* Accessor macros for the debug registers. */ 98 #define AARCH64_DBG_READ(N, REG, VAL) do {\ 99 asm volatile("mrs %0, dbg" REG #N "_el1" : "=r" (VAL));\ 100 } while (0) 101 102 #define AARCH64_DBG_WRITE(N, REG, VAL) do {\ 103 asm volatile("msr dbg" REG #N "_el1, %0" :: "r" (VAL));\ 104 } while (0) 105 106 struct task_struct; 107 struct notifier_block; 108 struct perf_event; 109 struct pmu; 110 111 extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl, 112 int *gen_len, int *gen_type); 113 extern int arch_check_bp_in_kernelspace(struct perf_event *bp); 114 extern int arch_validate_hwbkpt_settings(struct perf_event *bp); 115 extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused, 116 unsigned long val, void *data); 117 118 extern int arch_install_hw_breakpoint(struct perf_event *bp); 119 extern void arch_uninstall_hw_breakpoint(struct perf_event *bp); 120 extern void hw_breakpoint_pmu_read(struct perf_event *bp); 121 extern int hw_breakpoint_slots(int type); 122 123 #ifdef CONFIG_HAVE_HW_BREAKPOINT 124 extern void hw_breakpoint_thread_switch(struct task_struct *next); 125 extern void ptrace_hw_copy_thread(struct task_struct *task); 126 #else 127 static inline void hw_breakpoint_thread_switch(struct task_struct *next) 128 { 129 } 130 static inline void ptrace_hw_copy_thread(struct task_struct *task) 131 { 132 } 133 #endif 134 135 extern struct pmu perf_ops_bp; 136 137 /* Determine number of BRP registers available. */ 138 static inline int get_num_brps(void) 139 { 140 return ((read_cpuid(ID_AA64DFR0_EL1) >> 12) & 0xf) + 1; 141 } 142 143 /* Determine number of WRP registers available. */ 144 static inline int get_num_wrps(void) 145 { 146 return ((read_cpuid(ID_AA64DFR0_EL1) >> 20) & 0xf) + 1; 147 } 148 149 #endif /* __KERNEL__ */ 150 #endif /* __ASM_BREAKPOINT_H */ 151