1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #ifndef __ASM_ESR_H 8 #define __ASM_ESR_H 9 10 #include <asm/memory.h> 11 #include <asm/sysreg.h> 12 13 #define ESR_ELx_EC_UNKNOWN (0x00) 14 #define ESR_ELx_EC_WFx (0x01) 15 /* Unallocated EC: 0x02 */ 16 #define ESR_ELx_EC_CP15_32 (0x03) 17 #define ESR_ELx_EC_CP15_64 (0x04) 18 #define ESR_ELx_EC_CP14_MR (0x05) 19 #define ESR_ELx_EC_CP14_LS (0x06) 20 #define ESR_ELx_EC_FP_ASIMD (0x07) 21 #define ESR_ELx_EC_CP10_ID (0x08) /* EL2 only */ 22 #define ESR_ELx_EC_PAC (0x09) /* EL2 and above */ 23 /* Unallocated EC: 0x0A - 0x0B */ 24 #define ESR_ELx_EC_CP14_64 (0x0C) 25 #define ESR_ELx_EC_BTI (0x0D) 26 #define ESR_ELx_EC_ILL (0x0E) 27 /* Unallocated EC: 0x0F - 0x10 */ 28 #define ESR_ELx_EC_SVC32 (0x11) 29 #define ESR_ELx_EC_HVC32 (0x12) /* EL2 only */ 30 #define ESR_ELx_EC_SMC32 (0x13) /* EL2 and above */ 31 /* Unallocated EC: 0x14 */ 32 #define ESR_ELx_EC_SVC64 (0x15) 33 #define ESR_ELx_EC_HVC64 (0x16) /* EL2 and above */ 34 #define ESR_ELx_EC_SMC64 (0x17) /* EL2 and above */ 35 #define ESR_ELx_EC_SYS64 (0x18) 36 #define ESR_ELx_EC_SVE (0x19) 37 #define ESR_ELx_EC_ERET (0x1a) /* EL2 only */ 38 /* Unallocated EC: 0x1B */ 39 #define ESR_ELx_EC_FPAC (0x1C) /* EL1 and above */ 40 #define ESR_ELx_EC_SME (0x1D) 41 /* Unallocated EC: 0x1E */ 42 #define ESR_ELx_EC_IMP_DEF (0x1f) /* EL3 only */ 43 #define ESR_ELx_EC_IABT_LOW (0x20) 44 #define ESR_ELx_EC_IABT_CUR (0x21) 45 #define ESR_ELx_EC_PC_ALIGN (0x22) 46 /* Unallocated EC: 0x23 */ 47 #define ESR_ELx_EC_DABT_LOW (0x24) 48 #define ESR_ELx_EC_DABT_CUR (0x25) 49 #define ESR_ELx_EC_SP_ALIGN (0x26) 50 #define ESR_ELx_EC_MOPS (0x27) 51 #define ESR_ELx_EC_FP_EXC32 (0x28) 52 /* Unallocated EC: 0x29 - 0x2B */ 53 #define ESR_ELx_EC_FP_EXC64 (0x2C) 54 /* Unallocated EC: 0x2D - 0x2E */ 55 #define ESR_ELx_EC_SERROR (0x2F) 56 #define ESR_ELx_EC_BREAKPT_LOW (0x30) 57 #define ESR_ELx_EC_BREAKPT_CUR (0x31) 58 #define ESR_ELx_EC_SOFTSTP_LOW (0x32) 59 #define ESR_ELx_EC_SOFTSTP_CUR (0x33) 60 #define ESR_ELx_EC_WATCHPT_LOW (0x34) 61 #define ESR_ELx_EC_WATCHPT_CUR (0x35) 62 /* Unallocated EC: 0x36 - 0x37 */ 63 #define ESR_ELx_EC_BKPT32 (0x38) 64 /* Unallocated EC: 0x39 */ 65 #define ESR_ELx_EC_VECTOR32 (0x3A) /* EL2 only */ 66 /* Unallocated EC: 0x3B */ 67 #define ESR_ELx_EC_BRK64 (0x3C) 68 /* Unallocated EC: 0x3D - 0x3F */ 69 #define ESR_ELx_EC_MAX (0x3F) 70 71 #define ESR_ELx_EC_SHIFT (26) 72 #define ESR_ELx_EC_WIDTH (6) 73 #define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT) 74 #define ESR_ELx_EC(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) 75 76 #define ESR_ELx_IL_SHIFT (25) 77 #define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT) 78 #define ESR_ELx_ISS_MASK (GENMASK(24, 0)) 79 #define ESR_ELx_ISS(esr) ((esr) & ESR_ELx_ISS_MASK) 80 #define ESR_ELx_ISS2_SHIFT (32) 81 #define ESR_ELx_ISS2_MASK (GENMASK_ULL(55, 32)) 82 #define ESR_ELx_ISS2(esr) (((esr) & ESR_ELx_ISS2_MASK) >> ESR_ELx_ISS2_SHIFT) 83 84 /* ISS field definitions shared by different classes */ 85 #define ESR_ELx_WNR_SHIFT (6) 86 #define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT) 87 88 /* Asynchronous Error Type */ 89 #define ESR_ELx_IDS_SHIFT (24) 90 #define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT) 91 #define ESR_ELx_AET_SHIFT (10) 92 #define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT) 93 94 #define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT) 95 #define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT) 96 #define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT) 97 #define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT) 98 #define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT) 99 100 /* Shared ISS field definitions for Data/Instruction aborts */ 101 #define ESR_ELx_SET_SHIFT (11) 102 #define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT) 103 #define ESR_ELx_FnV_SHIFT (10) 104 #define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT) 105 #define ESR_ELx_EA_SHIFT (9) 106 #define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT) 107 #define ESR_ELx_S1PTW_SHIFT (7) 108 #define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT) 109 110 /* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */ 111 #define ESR_ELx_FSC (0x3F) 112 #define ESR_ELx_FSC_TYPE (0x3C) 113 #define ESR_ELx_FSC_LEVEL (0x03) 114 #define ESR_ELx_FSC_EXTABT (0x10) 115 #define ESR_ELx_FSC_MTE (0x11) 116 #define ESR_ELx_FSC_SERROR (0x11) 117 #define ESR_ELx_FSC_ACCESS (0x08) 118 #define ESR_ELx_FSC_FAULT (0x04) 119 #define ESR_ELx_FSC_PERM (0x0C) 120 #define ESR_ELx_FSC_SEA_TTW(n) (0x14 + (n)) 121 #define ESR_ELx_FSC_SECC (0x18) 122 #define ESR_ELx_FSC_SECC_TTW(n) (0x1c + (n)) 123 124 /* Status codes for individual page table levels */ 125 #define ESR_ELx_FSC_ACCESS_L(n) (ESR_ELx_FSC_ACCESS + n) 126 #define ESR_ELx_FSC_PERM_L(n) (ESR_ELx_FSC_PERM + n) 127 128 #define ESR_ELx_FSC_FAULT_nL (0x2C) 129 #define ESR_ELx_FSC_FAULT_L(n) (((n) < 0 ? ESR_ELx_FSC_FAULT_nL : \ 130 ESR_ELx_FSC_FAULT) + (n)) 131 132 /* ISS field definitions for Data Aborts */ 133 #define ESR_ELx_ISV_SHIFT (24) 134 #define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT) 135 #define ESR_ELx_SAS_SHIFT (22) 136 #define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT) 137 #define ESR_ELx_SSE_SHIFT (21) 138 #define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT) 139 #define ESR_ELx_SRT_SHIFT (16) 140 #define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT) 141 #define ESR_ELx_SF_SHIFT (15) 142 #define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT) 143 #define ESR_ELx_AR_SHIFT (14) 144 #define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT) 145 #define ESR_ELx_CM_SHIFT (8) 146 #define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT) 147 148 /* ISS2 field definitions for Data Aborts */ 149 #define ESR_ELx_TnD_SHIFT (10) 150 #define ESR_ELx_TnD (UL(1) << ESR_ELx_TnD_SHIFT) 151 #define ESR_ELx_TagAccess_SHIFT (9) 152 #define ESR_ELx_TagAccess (UL(1) << ESR_ELx_TagAccess_SHIFT) 153 #define ESR_ELx_GCS_SHIFT (8) 154 #define ESR_ELx_GCS (UL(1) << ESR_ELx_GCS_SHIFT) 155 #define ESR_ELx_Overlay_SHIFT (6) 156 #define ESR_ELx_Overlay (UL(1) << ESR_ELx_Overlay_SHIFT) 157 #define ESR_ELx_DirtyBit_SHIFT (5) 158 #define ESR_ELx_DirtyBit (UL(1) << ESR_ELx_DirtyBit_SHIFT) 159 #define ESR_ELx_Xs_SHIFT (0) 160 #define ESR_ELx_Xs_MASK (GENMASK_ULL(4, 0)) 161 162 /* ISS field definitions for exceptions taken in to Hyp */ 163 #define ESR_ELx_CV (UL(1) << 24) 164 #define ESR_ELx_COND_SHIFT (20) 165 #define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT) 166 #define ESR_ELx_WFx_ISS_RN (UL(0x1F) << 5) 167 #define ESR_ELx_WFx_ISS_RV (UL(1) << 2) 168 #define ESR_ELx_WFx_ISS_TI (UL(3) << 0) 169 #define ESR_ELx_WFx_ISS_WFxT (UL(2) << 0) 170 #define ESR_ELx_WFx_ISS_WFI (UL(0) << 0) 171 #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0) 172 #define ESR_ELx_xVC_IMM_MASK ((UL(1) << 16) - 1) 173 174 #define DISR_EL1_IDS (UL(1) << 24) 175 /* 176 * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean 177 * different things in the future... 178 */ 179 #define DISR_EL1_ESR_MASK (ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC) 180 181 /* ESR value templates for specific events */ 182 #define ESR_ELx_WFx_MASK (ESR_ELx_EC_MASK | \ 183 (ESR_ELx_WFx_ISS_TI & ~ESR_ELx_WFx_ISS_WFxT)) 184 #define ESR_ELx_WFx_WFI_VAL ((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) | \ 185 ESR_ELx_WFx_ISS_WFI) 186 187 /* BRK instruction trap from AArch64 state */ 188 #define ESR_ELx_BRK64_ISS_COMMENT_MASK 0xffff 189 190 /* ISS field definitions for System instruction traps */ 191 #define ESR_ELx_SYS64_ISS_RES0_SHIFT 22 192 #define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT) 193 #define ESR_ELx_SYS64_ISS_DIR_MASK 0x1 194 #define ESR_ELx_SYS64_ISS_DIR_READ 0x1 195 #define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0 196 197 #define ESR_ELx_SYS64_ISS_RT_SHIFT 5 198 #define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT) 199 #define ESR_ELx_SYS64_ISS_CRM_SHIFT 1 200 #define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT) 201 #define ESR_ELx_SYS64_ISS_CRN_SHIFT 10 202 #define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT) 203 #define ESR_ELx_SYS64_ISS_OP1_SHIFT 14 204 #define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT) 205 #define ESR_ELx_SYS64_ISS_OP2_SHIFT 17 206 #define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT) 207 #define ESR_ELx_SYS64_ISS_OP0_SHIFT 20 208 #define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT) 209 #define ESR_ELx_SYS64_ISS_SYS_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ 210 ESR_ELx_SYS64_ISS_OP1_MASK | \ 211 ESR_ELx_SYS64_ISS_OP2_MASK | \ 212 ESR_ELx_SYS64_ISS_CRN_MASK | \ 213 ESR_ELx_SYS64_ISS_CRM_MASK) 214 #define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \ 215 (((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \ 216 ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \ 217 ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \ 218 ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \ 219 ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT)) 220 221 #define ESR_ELx_SYS64_ISS_SYS_OP_MASK (ESR_ELx_SYS64_ISS_SYS_MASK | \ 222 ESR_ELx_SYS64_ISS_DIR_MASK) 223 #define ESR_ELx_SYS64_ISS_RT(esr) \ 224 (((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT) 225 /* 226 * User space cache operations have the following sysreg encoding 227 * in System instructions. 228 * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0) 229 */ 230 #define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14 231 #define ESR_ELx_SYS64_ISS_CRM_DC_CVADP 13 232 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAP 12 233 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11 234 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10 235 #define ESR_ELx_SYS64_ISS_CRM_IC_IVAU 5 236 237 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ 238 ESR_ELx_SYS64_ISS_OP1_MASK | \ 239 ESR_ELx_SYS64_ISS_OP2_MASK | \ 240 ESR_ELx_SYS64_ISS_CRN_MASK | \ 241 ESR_ELx_SYS64_ISS_DIR_MASK) 242 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \ 243 (ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \ 244 ESR_ELx_SYS64_ISS_DIR_WRITE) 245 /* 246 * User space MRS operations which are supported for emulation 247 * have the following sysreg encoding in System instructions. 248 * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1) 249 */ 250 #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ 251 ESR_ELx_SYS64_ISS_OP1_MASK | \ 252 ESR_ELx_SYS64_ISS_CRN_MASK | \ 253 ESR_ELx_SYS64_ISS_DIR_MASK) 254 #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \ 255 (ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \ 256 ESR_ELx_SYS64_ISS_DIR_READ) 257 258 #define ESR_ELx_SYS64_ISS_SYS_CTR ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0) 259 #define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \ 260 ESR_ELx_SYS64_ISS_DIR_READ) 261 262 #define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \ 263 ESR_ELx_SYS64_ISS_DIR_READ) 264 265 #define ESR_ELx_SYS64_ISS_SYS_CNTVCTSS (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 6, 14, 0) | \ 266 ESR_ELx_SYS64_ISS_DIR_READ) 267 268 #define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \ 269 ESR_ELx_SYS64_ISS_DIR_READ) 270 271 #define esr_sys64_to_sysreg(e) \ 272 sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> \ 273 ESR_ELx_SYS64_ISS_OP0_SHIFT), \ 274 (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \ 275 ESR_ELx_SYS64_ISS_OP1_SHIFT), \ 276 (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \ 277 ESR_ELx_SYS64_ISS_CRN_SHIFT), \ 278 (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \ 279 ESR_ELx_SYS64_ISS_CRM_SHIFT), \ 280 (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \ 281 ESR_ELx_SYS64_ISS_OP2_SHIFT)) 282 283 #define esr_cp15_to_sysreg(e) \ 284 sys_reg(3, \ 285 (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \ 286 ESR_ELx_SYS64_ISS_OP1_SHIFT), \ 287 (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \ 288 ESR_ELx_SYS64_ISS_CRN_SHIFT), \ 289 (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \ 290 ESR_ELx_SYS64_ISS_CRM_SHIFT), \ 291 (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \ 292 ESR_ELx_SYS64_ISS_OP2_SHIFT)) 293 294 /* ISS field definitions for ERET/ERETAA/ERETAB trapping */ 295 #define ESR_ELx_ERET_ISS_ERET 0x2 296 #define ESR_ELx_ERET_ISS_ERETA 0x1 297 298 /* 299 * ISS field definitions for floating-point exception traps 300 * (FP_EXC_32/FP_EXC_64). 301 * 302 * (The FPEXC_* constants are used instead for common bits.) 303 */ 304 305 #define ESR_ELx_FP_EXC_TFV (UL(1) << 23) 306 307 /* 308 * ISS field definitions for CP15 accesses 309 */ 310 #define ESR_ELx_CP15_32_ISS_DIR_MASK 0x1 311 #define ESR_ELx_CP15_32_ISS_DIR_READ 0x1 312 #define ESR_ELx_CP15_32_ISS_DIR_WRITE 0x0 313 314 #define ESR_ELx_CP15_32_ISS_RT_SHIFT 5 315 #define ESR_ELx_CP15_32_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT) 316 #define ESR_ELx_CP15_32_ISS_CRM_SHIFT 1 317 #define ESR_ELx_CP15_32_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT) 318 #define ESR_ELx_CP15_32_ISS_CRN_SHIFT 10 319 #define ESR_ELx_CP15_32_ISS_CRN_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) 320 #define ESR_ELx_CP15_32_ISS_OP1_SHIFT 14 321 #define ESR_ELx_CP15_32_ISS_OP1_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) 322 #define ESR_ELx_CP15_32_ISS_OP2_SHIFT 17 323 #define ESR_ELx_CP15_32_ISS_OP2_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) 324 325 #define ESR_ELx_CP15_32_ISS_SYS_MASK (ESR_ELx_CP15_32_ISS_OP1_MASK | \ 326 ESR_ELx_CP15_32_ISS_OP2_MASK | \ 327 ESR_ELx_CP15_32_ISS_CRN_MASK | \ 328 ESR_ELx_CP15_32_ISS_CRM_MASK | \ 329 ESR_ELx_CP15_32_ISS_DIR_MASK) 330 #define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \ 331 (((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \ 332 ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \ 333 ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \ 334 ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)) 335 336 #define ESR_ELx_CP15_64_ISS_DIR_MASK 0x1 337 #define ESR_ELx_CP15_64_ISS_DIR_READ 0x1 338 #define ESR_ELx_CP15_64_ISS_DIR_WRITE 0x0 339 340 #define ESR_ELx_CP15_64_ISS_RT_SHIFT 5 341 #define ESR_ELx_CP15_64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT) 342 343 #define ESR_ELx_CP15_64_ISS_RT2_SHIFT 10 344 #define ESR_ELx_CP15_64_ISS_RT2_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT) 345 346 #define ESR_ELx_CP15_64_ISS_OP1_SHIFT 16 347 #define ESR_ELx_CP15_64_ISS_OP1_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) 348 #define ESR_ELx_CP15_64_ISS_CRM_SHIFT 1 349 #define ESR_ELx_CP15_64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT) 350 351 #define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \ 352 (((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \ 353 ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)) 354 355 #define ESR_ELx_CP15_64_ISS_SYS_MASK (ESR_ELx_CP15_64_ISS_OP1_MASK | \ 356 ESR_ELx_CP15_64_ISS_CRM_MASK | \ 357 ESR_ELx_CP15_64_ISS_DIR_MASK) 358 359 #define ESR_ELx_CP15_64_ISS_SYS_CNTVCT (ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \ 360 ESR_ELx_CP15_64_ISS_DIR_READ) 361 362 #define ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS (ESR_ELx_CP15_64_ISS_SYS_VAL(9, 14) | \ 363 ESR_ELx_CP15_64_ISS_DIR_READ) 364 365 #define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ (ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\ 366 ESR_ELx_CP15_32_ISS_DIR_READ) 367 368 /* 369 * ISS values for SME traps 370 */ 371 372 #define ESR_ELx_SME_ISS_SME_DISABLED 0 373 #define ESR_ELx_SME_ISS_ILL 1 374 #define ESR_ELx_SME_ISS_SM_DISABLED 2 375 #define ESR_ELx_SME_ISS_ZA_DISABLED 3 376 #define ESR_ELx_SME_ISS_ZT_DISABLED 4 377 378 /* ISS field definitions for MOPS exceptions */ 379 #define ESR_ELx_MOPS_ISS_MEM_INST (UL(1) << 24) 380 #define ESR_ELx_MOPS_ISS_FROM_EPILOGUE (UL(1) << 18) 381 #define ESR_ELx_MOPS_ISS_WRONG_OPTION (UL(1) << 17) 382 #define ESR_ELx_MOPS_ISS_OPTION_A (UL(1) << 16) 383 #define ESR_ELx_MOPS_ISS_DESTREG(esr) (((esr) & (UL(0x1f) << 10)) >> 10) 384 #define ESR_ELx_MOPS_ISS_SRCREG(esr) (((esr) & (UL(0x1f) << 5)) >> 5) 385 #define ESR_ELx_MOPS_ISS_SIZEREG(esr) (((esr) & (UL(0x1f) << 0)) >> 0) 386 387 #ifndef __ASSEMBLY__ 388 #include <asm/types.h> 389 390 static inline bool esr_is_data_abort(unsigned long esr) 391 { 392 const unsigned long ec = ESR_ELx_EC(esr); 393 394 return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR; 395 } 396 397 static inline bool esr_fsc_is_translation_fault(unsigned long esr) 398 { 399 esr = esr & ESR_ELx_FSC; 400 401 return (esr == ESR_ELx_FSC_FAULT_L(3)) || 402 (esr == ESR_ELx_FSC_FAULT_L(2)) || 403 (esr == ESR_ELx_FSC_FAULT_L(1)) || 404 (esr == ESR_ELx_FSC_FAULT_L(0)) || 405 (esr == ESR_ELx_FSC_FAULT_L(-1)); 406 } 407 408 static inline bool esr_fsc_is_permission_fault(unsigned long esr) 409 { 410 esr = esr & ESR_ELx_FSC; 411 412 return (esr == ESR_ELx_FSC_PERM_L(3)) || 413 (esr == ESR_ELx_FSC_PERM_L(2)) || 414 (esr == ESR_ELx_FSC_PERM_L(1)) || 415 (esr == ESR_ELx_FSC_PERM_L(0)); 416 } 417 418 static inline bool esr_fsc_is_access_flag_fault(unsigned long esr) 419 { 420 esr = esr & ESR_ELx_FSC; 421 422 return (esr == ESR_ELx_FSC_ACCESS_L(3)) || 423 (esr == ESR_ELx_FSC_ACCESS_L(2)) || 424 (esr == ESR_ELx_FSC_ACCESS_L(1)) || 425 (esr == ESR_ELx_FSC_ACCESS_L(0)); 426 } 427 428 /* Indicate whether ESR.EC==0x1A is for an ERETAx instruction */ 429 static inline bool esr_iss_is_eretax(unsigned long esr) 430 { 431 return esr & ESR_ELx_ERET_ISS_ERET; 432 } 433 434 /* Indicate which key is used for ERETAx (false: A-Key, true: B-Key) */ 435 static inline bool esr_iss_is_eretab(unsigned long esr) 436 { 437 return esr & ESR_ELx_ERET_ISS_ERETA; 438 } 439 440 const char *esr_get_class_string(unsigned long esr); 441 #endif /* __ASSEMBLY */ 442 443 #endif /* __ASM_ESR_H */ 444