1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #ifndef __ASM_ESR_H 8 #define __ASM_ESR_H 9 10 #include <asm/memory.h> 11 #include <asm/sysreg.h> 12 13 #define ESR_ELx_EC_UNKNOWN UL(0x00) 14 #define ESR_ELx_EC_WFx UL(0x01) 15 /* Unallocated EC: 0x02 */ 16 #define ESR_ELx_EC_CP15_32 UL(0x03) 17 #define ESR_ELx_EC_CP15_64 UL(0x04) 18 #define ESR_ELx_EC_CP14_MR UL(0x05) 19 #define ESR_ELx_EC_CP14_LS UL(0x06) 20 #define ESR_ELx_EC_FP_ASIMD UL(0x07) 21 #define ESR_ELx_EC_CP10_ID UL(0x08) /* EL2 only */ 22 #define ESR_ELx_EC_PAC UL(0x09) /* EL2 and above */ 23 /* Unallocated EC: 0x0A - 0x0B */ 24 #define ESR_ELx_EC_CP14_64 UL(0x0C) 25 #define ESR_ELx_EC_BTI UL(0x0D) 26 #define ESR_ELx_EC_ILL UL(0x0E) 27 /* Unallocated EC: 0x0F - 0x10 */ 28 #define ESR_ELx_EC_SVC32 UL(0x11) 29 #define ESR_ELx_EC_HVC32 UL(0x12) /* EL2 only */ 30 #define ESR_ELx_EC_SMC32 UL(0x13) /* EL2 and above */ 31 /* Unallocated EC: 0x14 */ 32 #define ESR_ELx_EC_SVC64 UL(0x15) 33 #define ESR_ELx_EC_HVC64 UL(0x16) /* EL2 and above */ 34 #define ESR_ELx_EC_SMC64 UL(0x17) /* EL2 and above */ 35 #define ESR_ELx_EC_SYS64 UL(0x18) 36 #define ESR_ELx_EC_SVE UL(0x19) 37 #define ESR_ELx_EC_ERET UL(0x1a) /* EL2 only */ 38 /* Unallocated EC: 0x1B */ 39 #define ESR_ELx_EC_FPAC UL(0x1C) /* EL1 and above */ 40 #define ESR_ELx_EC_SME UL(0x1D) 41 /* Unallocated EC: 0x1E */ 42 #define ESR_ELx_EC_IMP_DEF UL(0x1f) /* EL3 only */ 43 #define ESR_ELx_EC_IABT_LOW UL(0x20) 44 #define ESR_ELx_EC_IABT_CUR UL(0x21) 45 #define ESR_ELx_EC_PC_ALIGN UL(0x22) 46 /* Unallocated EC: 0x23 */ 47 #define ESR_ELx_EC_DABT_LOW UL(0x24) 48 #define ESR_ELx_EC_DABT_CUR UL(0x25) 49 #define ESR_ELx_EC_SP_ALIGN UL(0x26) 50 #define ESR_ELx_EC_MOPS UL(0x27) 51 #define ESR_ELx_EC_FP_EXC32 UL(0x28) 52 /* Unallocated EC: 0x29 - 0x2B */ 53 #define ESR_ELx_EC_FP_EXC64 UL(0x2C) 54 #define ESR_ELx_EC_GCS UL(0x2D) 55 /* Unallocated EC: 0x2E */ 56 #define ESR_ELx_EC_SERROR UL(0x2F) 57 #define ESR_ELx_EC_BREAKPT_LOW UL(0x30) 58 #define ESR_ELx_EC_BREAKPT_CUR UL(0x31) 59 #define ESR_ELx_EC_SOFTSTP_LOW UL(0x32) 60 #define ESR_ELx_EC_SOFTSTP_CUR UL(0x33) 61 #define ESR_ELx_EC_WATCHPT_LOW UL(0x34) 62 #define ESR_ELx_EC_WATCHPT_CUR UL(0x35) 63 /* Unallocated EC: 0x36 - 0x37 */ 64 #define ESR_ELx_EC_BKPT32 UL(0x38) 65 /* Unallocated EC: 0x39 */ 66 #define ESR_ELx_EC_VECTOR32 UL(0x3A) /* EL2 only */ 67 /* Unallocated EC: 0x3B */ 68 #define ESR_ELx_EC_BRK64 UL(0x3C) 69 /* Unallocated EC: 0x3D - 0x3F */ 70 #define ESR_ELx_EC_MAX UL(0x3F) 71 72 #define ESR_ELx_EC_SHIFT (26) 73 #define ESR_ELx_EC_WIDTH (6) 74 #define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT) 75 #define ESR_ELx_EC(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) 76 77 #define ESR_ELx_IL_SHIFT (25) 78 #define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT) 79 #define ESR_ELx_ISS_MASK (GENMASK(24, 0)) 80 #define ESR_ELx_ISS(esr) ((esr) & ESR_ELx_ISS_MASK) 81 #define ESR_ELx_ISS2_SHIFT (32) 82 #define ESR_ELx_ISS2_MASK (GENMASK_ULL(55, 32)) 83 #define ESR_ELx_ISS2(esr) (((esr) & ESR_ELx_ISS2_MASK) >> ESR_ELx_ISS2_SHIFT) 84 85 /* ISS field definitions shared by different classes */ 86 #define ESR_ELx_WNR_SHIFT (6) 87 #define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT) 88 89 /* Asynchronous Error Type */ 90 #define ESR_ELx_IDS_SHIFT (24) 91 #define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT) 92 #define ESR_ELx_AET_SHIFT (10) 93 #define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT) 94 95 #define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT) 96 #define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT) 97 #define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT) 98 #define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT) 99 #define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT) 100 101 /* Shared ISS field definitions for Data/Instruction aborts */ 102 #define ESR_ELx_SET_SHIFT (11) 103 #define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT) 104 #define ESR_ELx_FnV_SHIFT (10) 105 #define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT) 106 #define ESR_ELx_EA_SHIFT (9) 107 #define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT) 108 #define ESR_ELx_S1PTW_SHIFT (7) 109 #define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT) 110 111 /* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */ 112 #define ESR_ELx_FSC (0x3F) 113 #define ESR_ELx_FSC_TYPE (0x3C) 114 #define ESR_ELx_FSC_LEVEL (0x03) 115 #define ESR_ELx_FSC_EXTABT (0x10) 116 #define ESR_ELx_FSC_MTE (0x11) 117 #define ESR_ELx_FSC_SERROR (0x11) 118 #define ESR_ELx_FSC_ACCESS (0x08) 119 #define ESR_ELx_FSC_FAULT (0x04) 120 #define ESR_ELx_FSC_PERM (0x0C) 121 #define ESR_ELx_FSC_SEA_TTW(n) (0x14 + (n)) 122 #define ESR_ELx_FSC_SECC (0x18) 123 #define ESR_ELx_FSC_SECC_TTW(n) (0x1c + (n)) 124 #define ESR_ELx_FSC_ADDRSZ (0x00) 125 126 /* 127 * Annoyingly, the negative levels for Address size faults aren't laid out 128 * contiguously (or in the desired order) 129 */ 130 #define ESR_ELx_FSC_ADDRSZ_nL(n) ((n) == -1 ? 0x25 : 0x2C) 131 #define ESR_ELx_FSC_ADDRSZ_L(n) ((n) < 0 ? ESR_ELx_FSC_ADDRSZ_nL(n) : \ 132 (ESR_ELx_FSC_ADDRSZ + (n))) 133 134 /* Status codes for individual page table levels */ 135 #define ESR_ELx_FSC_ACCESS_L(n) (ESR_ELx_FSC_ACCESS + (n)) 136 #define ESR_ELx_FSC_PERM_L(n) (ESR_ELx_FSC_PERM + (n)) 137 138 #define ESR_ELx_FSC_FAULT_nL (0x2C) 139 #define ESR_ELx_FSC_FAULT_L(n) (((n) < 0 ? ESR_ELx_FSC_FAULT_nL : \ 140 ESR_ELx_FSC_FAULT) + (n)) 141 142 /* ISS field definitions for Data Aborts */ 143 #define ESR_ELx_ISV_SHIFT (24) 144 #define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT) 145 #define ESR_ELx_SAS_SHIFT (22) 146 #define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT) 147 #define ESR_ELx_SSE_SHIFT (21) 148 #define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT) 149 #define ESR_ELx_SRT_SHIFT (16) 150 #define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT) 151 #define ESR_ELx_SF_SHIFT (15) 152 #define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT) 153 #define ESR_ELx_AR_SHIFT (14) 154 #define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT) 155 #define ESR_ELx_CM_SHIFT (8) 156 #define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT) 157 158 /* ISS2 field definitions for Data Aborts */ 159 #define ESR_ELx_TnD_SHIFT (10) 160 #define ESR_ELx_TnD (UL(1) << ESR_ELx_TnD_SHIFT) 161 #define ESR_ELx_TagAccess_SHIFT (9) 162 #define ESR_ELx_TagAccess (UL(1) << ESR_ELx_TagAccess_SHIFT) 163 #define ESR_ELx_GCS_SHIFT (8) 164 #define ESR_ELx_GCS (UL(1) << ESR_ELx_GCS_SHIFT) 165 #define ESR_ELx_Overlay_SHIFT (6) 166 #define ESR_ELx_Overlay (UL(1) << ESR_ELx_Overlay_SHIFT) 167 #define ESR_ELx_DirtyBit_SHIFT (5) 168 #define ESR_ELx_DirtyBit (UL(1) << ESR_ELx_DirtyBit_SHIFT) 169 #define ESR_ELx_Xs_SHIFT (0) 170 #define ESR_ELx_Xs_MASK (GENMASK_ULL(4, 0)) 171 172 /* ISS field definitions for exceptions taken in to Hyp */ 173 #define ESR_ELx_CV (UL(1) << 24) 174 #define ESR_ELx_COND_SHIFT (20) 175 #define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT) 176 #define ESR_ELx_WFx_ISS_RN (UL(0x1F) << 5) 177 #define ESR_ELx_WFx_ISS_RV (UL(1) << 2) 178 #define ESR_ELx_WFx_ISS_TI (UL(3) << 0) 179 #define ESR_ELx_WFx_ISS_WFxT (UL(2) << 0) 180 #define ESR_ELx_WFx_ISS_WFI (UL(0) << 0) 181 #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0) 182 #define ESR_ELx_xVC_IMM_MASK ((UL(1) << 16) - 1) 183 184 #define DISR_EL1_IDS (UL(1) << 24) 185 /* 186 * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean 187 * different things in the future... 188 */ 189 #define DISR_EL1_ESR_MASK (ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC) 190 191 /* ESR value templates for specific events */ 192 #define ESR_ELx_WFx_MASK (ESR_ELx_EC_MASK | \ 193 (ESR_ELx_WFx_ISS_TI & ~ESR_ELx_WFx_ISS_WFxT)) 194 #define ESR_ELx_WFx_WFI_VAL ((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) | \ 195 ESR_ELx_WFx_ISS_WFI) 196 197 /* BRK instruction trap from AArch64 state */ 198 #define ESR_ELx_BRK64_ISS_COMMENT_MASK 0xffff 199 200 /* ISS field definitions for System instruction traps */ 201 #define ESR_ELx_SYS64_ISS_RES0_SHIFT 22 202 #define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT) 203 #define ESR_ELx_SYS64_ISS_DIR_MASK 0x1 204 #define ESR_ELx_SYS64_ISS_DIR_READ 0x1 205 #define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0 206 207 #define ESR_ELx_SYS64_ISS_RT_SHIFT 5 208 #define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT) 209 #define ESR_ELx_SYS64_ISS_CRM_SHIFT 1 210 #define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT) 211 #define ESR_ELx_SYS64_ISS_CRN_SHIFT 10 212 #define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT) 213 #define ESR_ELx_SYS64_ISS_OP1_SHIFT 14 214 #define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT) 215 #define ESR_ELx_SYS64_ISS_OP2_SHIFT 17 216 #define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT) 217 #define ESR_ELx_SYS64_ISS_OP0_SHIFT 20 218 #define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT) 219 #define ESR_ELx_SYS64_ISS_SYS_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ 220 ESR_ELx_SYS64_ISS_OP1_MASK | \ 221 ESR_ELx_SYS64_ISS_OP2_MASK | \ 222 ESR_ELx_SYS64_ISS_CRN_MASK | \ 223 ESR_ELx_SYS64_ISS_CRM_MASK) 224 #define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \ 225 (((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \ 226 ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \ 227 ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \ 228 ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \ 229 ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT)) 230 231 #define ESR_ELx_SYS64_ISS_SYS_OP_MASK (ESR_ELx_SYS64_ISS_SYS_MASK | \ 232 ESR_ELx_SYS64_ISS_DIR_MASK) 233 #define ESR_ELx_SYS64_ISS_RT(esr) \ 234 (((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT) 235 /* 236 * User space cache operations have the following sysreg encoding 237 * in System instructions. 238 * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0) 239 */ 240 #define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14 241 #define ESR_ELx_SYS64_ISS_CRM_DC_CVADP 13 242 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAP 12 243 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11 244 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10 245 #define ESR_ELx_SYS64_ISS_CRM_IC_IVAU 5 246 247 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ 248 ESR_ELx_SYS64_ISS_OP1_MASK | \ 249 ESR_ELx_SYS64_ISS_OP2_MASK | \ 250 ESR_ELx_SYS64_ISS_CRN_MASK | \ 251 ESR_ELx_SYS64_ISS_DIR_MASK) 252 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \ 253 (ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \ 254 ESR_ELx_SYS64_ISS_DIR_WRITE) 255 /* 256 * User space MRS operations which are supported for emulation 257 * have the following sysreg encoding in System instructions. 258 * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1) 259 */ 260 #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ 261 ESR_ELx_SYS64_ISS_OP1_MASK | \ 262 ESR_ELx_SYS64_ISS_CRN_MASK | \ 263 ESR_ELx_SYS64_ISS_DIR_MASK) 264 #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \ 265 (ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \ 266 ESR_ELx_SYS64_ISS_DIR_READ) 267 268 #define ESR_ELx_SYS64_ISS_SYS_CTR ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0) 269 #define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \ 270 ESR_ELx_SYS64_ISS_DIR_READ) 271 272 #define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \ 273 ESR_ELx_SYS64_ISS_DIR_READ) 274 275 #define ESR_ELx_SYS64_ISS_SYS_CNTVCTSS (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 6, 14, 0) | \ 276 ESR_ELx_SYS64_ISS_DIR_READ) 277 278 #define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \ 279 ESR_ELx_SYS64_ISS_DIR_READ) 280 281 #define esr_sys64_to_sysreg(e) \ 282 sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> \ 283 ESR_ELx_SYS64_ISS_OP0_SHIFT), \ 284 (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \ 285 ESR_ELx_SYS64_ISS_OP1_SHIFT), \ 286 (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \ 287 ESR_ELx_SYS64_ISS_CRN_SHIFT), \ 288 (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \ 289 ESR_ELx_SYS64_ISS_CRM_SHIFT), \ 290 (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \ 291 ESR_ELx_SYS64_ISS_OP2_SHIFT)) 292 293 #define esr_cp15_to_sysreg(e) \ 294 sys_reg(3, \ 295 (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \ 296 ESR_ELx_SYS64_ISS_OP1_SHIFT), \ 297 (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \ 298 ESR_ELx_SYS64_ISS_CRN_SHIFT), \ 299 (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \ 300 ESR_ELx_SYS64_ISS_CRM_SHIFT), \ 301 (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \ 302 ESR_ELx_SYS64_ISS_OP2_SHIFT)) 303 304 /* ISS field definitions for ERET/ERETAA/ERETAB trapping */ 305 #define ESR_ELx_ERET_ISS_ERET 0x2 306 #define ESR_ELx_ERET_ISS_ERETA 0x1 307 308 /* 309 * ISS field definitions for floating-point exception traps 310 * (FP_EXC_32/FP_EXC_64). 311 * 312 * (The FPEXC_* constants are used instead for common bits.) 313 */ 314 315 #define ESR_ELx_FP_EXC_TFV (UL(1) << 23) 316 317 /* 318 * ISS field definitions for CP15 accesses 319 */ 320 #define ESR_ELx_CP15_32_ISS_DIR_MASK 0x1 321 #define ESR_ELx_CP15_32_ISS_DIR_READ 0x1 322 #define ESR_ELx_CP15_32_ISS_DIR_WRITE 0x0 323 324 #define ESR_ELx_CP15_32_ISS_RT_SHIFT 5 325 #define ESR_ELx_CP15_32_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT) 326 #define ESR_ELx_CP15_32_ISS_CRM_SHIFT 1 327 #define ESR_ELx_CP15_32_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT) 328 #define ESR_ELx_CP15_32_ISS_CRN_SHIFT 10 329 #define ESR_ELx_CP15_32_ISS_CRN_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) 330 #define ESR_ELx_CP15_32_ISS_OP1_SHIFT 14 331 #define ESR_ELx_CP15_32_ISS_OP1_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) 332 #define ESR_ELx_CP15_32_ISS_OP2_SHIFT 17 333 #define ESR_ELx_CP15_32_ISS_OP2_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) 334 335 #define ESR_ELx_CP15_32_ISS_SYS_MASK (ESR_ELx_CP15_32_ISS_OP1_MASK | \ 336 ESR_ELx_CP15_32_ISS_OP2_MASK | \ 337 ESR_ELx_CP15_32_ISS_CRN_MASK | \ 338 ESR_ELx_CP15_32_ISS_CRM_MASK | \ 339 ESR_ELx_CP15_32_ISS_DIR_MASK) 340 #define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \ 341 (((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \ 342 ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \ 343 ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \ 344 ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)) 345 346 #define ESR_ELx_CP15_64_ISS_DIR_MASK 0x1 347 #define ESR_ELx_CP15_64_ISS_DIR_READ 0x1 348 #define ESR_ELx_CP15_64_ISS_DIR_WRITE 0x0 349 350 #define ESR_ELx_CP15_64_ISS_RT_SHIFT 5 351 #define ESR_ELx_CP15_64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT) 352 353 #define ESR_ELx_CP15_64_ISS_RT2_SHIFT 10 354 #define ESR_ELx_CP15_64_ISS_RT2_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT) 355 356 #define ESR_ELx_CP15_64_ISS_OP1_SHIFT 16 357 #define ESR_ELx_CP15_64_ISS_OP1_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) 358 #define ESR_ELx_CP15_64_ISS_CRM_SHIFT 1 359 #define ESR_ELx_CP15_64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT) 360 361 #define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \ 362 (((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \ 363 ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)) 364 365 #define ESR_ELx_CP15_64_ISS_SYS_MASK (ESR_ELx_CP15_64_ISS_OP1_MASK | \ 366 ESR_ELx_CP15_64_ISS_CRM_MASK | \ 367 ESR_ELx_CP15_64_ISS_DIR_MASK) 368 369 #define ESR_ELx_CP15_64_ISS_SYS_CNTVCT (ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \ 370 ESR_ELx_CP15_64_ISS_DIR_READ) 371 372 #define ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS (ESR_ELx_CP15_64_ISS_SYS_VAL(9, 14) | \ 373 ESR_ELx_CP15_64_ISS_DIR_READ) 374 375 #define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ (ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\ 376 ESR_ELx_CP15_32_ISS_DIR_READ) 377 378 /* 379 * ISS values for SME traps 380 */ 381 382 #define ESR_ELx_SME_ISS_SME_DISABLED 0 383 #define ESR_ELx_SME_ISS_ILL 1 384 #define ESR_ELx_SME_ISS_SM_DISABLED 2 385 #define ESR_ELx_SME_ISS_ZA_DISABLED 3 386 #define ESR_ELx_SME_ISS_ZT_DISABLED 4 387 388 /* ISS field definitions for MOPS exceptions */ 389 #define ESR_ELx_MOPS_ISS_MEM_INST (UL(1) << 24) 390 #define ESR_ELx_MOPS_ISS_FROM_EPILOGUE (UL(1) << 18) 391 #define ESR_ELx_MOPS_ISS_WRONG_OPTION (UL(1) << 17) 392 #define ESR_ELx_MOPS_ISS_OPTION_A (UL(1) << 16) 393 #define ESR_ELx_MOPS_ISS_DESTREG(esr) (((esr) & (UL(0x1f) << 10)) >> 10) 394 #define ESR_ELx_MOPS_ISS_SRCREG(esr) (((esr) & (UL(0x1f) << 5)) >> 5) 395 #define ESR_ELx_MOPS_ISS_SIZEREG(esr) (((esr) & (UL(0x1f) << 0)) >> 0) 396 397 /* ISS field definitions for GCS */ 398 #define ESR_ELx_ExType_SHIFT (20) 399 #define ESR_ELx_ExType_MASK GENMASK(23, 20) 400 #define ESR_ELx_Raddr_SHIFT (10) 401 #define ESR_ELx_Raddr_MASK GENMASK(14, 10) 402 #define ESR_ELx_Rn_SHIFT (5) 403 #define ESR_ELx_Rn_MASK GENMASK(9, 5) 404 #define ESR_ELx_Rvalue_SHIFT 5 405 #define ESR_ELx_Rvalue_MASK GENMASK(9, 5) 406 #define ESR_ELx_IT_SHIFT (0) 407 #define ESR_ELx_IT_MASK GENMASK(4, 0) 408 409 #define ESR_ELx_ExType_DATA_CHECK 0 410 #define ESR_ELx_ExType_EXLOCK 1 411 #define ESR_ELx_ExType_STR 2 412 413 #define ESR_ELx_IT_RET 0 414 #define ESR_ELx_IT_GCSPOPM 1 415 #define ESR_ELx_IT_RET_KEYA 2 416 #define ESR_ELx_IT_RET_KEYB 3 417 #define ESR_ELx_IT_GCSSS1 4 418 #define ESR_ELx_IT_GCSSS2 5 419 #define ESR_ELx_IT_GCSPOPCX 6 420 #define ESR_ELx_IT_GCSPOPX 7 421 422 #ifndef __ASSEMBLY__ 423 #include <asm/types.h> 424 425 static inline unsigned long esr_brk_comment(unsigned long esr) 426 { 427 return esr & ESR_ELx_BRK64_ISS_COMMENT_MASK; 428 } 429 430 static inline bool esr_is_data_abort(unsigned long esr) 431 { 432 const unsigned long ec = ESR_ELx_EC(esr); 433 434 return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR; 435 } 436 437 static inline bool esr_is_cfi_brk(unsigned long esr) 438 { 439 return ESR_ELx_EC(esr) == ESR_ELx_EC_BRK64 && 440 (esr_brk_comment(esr) & ~CFI_BRK_IMM_MASK) == CFI_BRK_IMM_BASE; 441 } 442 443 static inline bool esr_fsc_is_translation_fault(unsigned long esr) 444 { 445 esr = esr & ESR_ELx_FSC; 446 447 return (esr == ESR_ELx_FSC_FAULT_L(3)) || 448 (esr == ESR_ELx_FSC_FAULT_L(2)) || 449 (esr == ESR_ELx_FSC_FAULT_L(1)) || 450 (esr == ESR_ELx_FSC_FAULT_L(0)) || 451 (esr == ESR_ELx_FSC_FAULT_L(-1)); 452 } 453 454 static inline bool esr_fsc_is_permission_fault(unsigned long esr) 455 { 456 esr = esr & ESR_ELx_FSC; 457 458 return (esr == ESR_ELx_FSC_PERM_L(3)) || 459 (esr == ESR_ELx_FSC_PERM_L(2)) || 460 (esr == ESR_ELx_FSC_PERM_L(1)) || 461 (esr == ESR_ELx_FSC_PERM_L(0)); 462 } 463 464 static inline bool esr_fsc_is_access_flag_fault(unsigned long esr) 465 { 466 esr = esr & ESR_ELx_FSC; 467 468 return (esr == ESR_ELx_FSC_ACCESS_L(3)) || 469 (esr == ESR_ELx_FSC_ACCESS_L(2)) || 470 (esr == ESR_ELx_FSC_ACCESS_L(1)) || 471 (esr == ESR_ELx_FSC_ACCESS_L(0)); 472 } 473 474 static inline bool esr_fsc_is_addr_sz_fault(unsigned long esr) 475 { 476 esr &= ESR_ELx_FSC; 477 478 return (esr == ESR_ELx_FSC_ADDRSZ_L(3)) || 479 (esr == ESR_ELx_FSC_ADDRSZ_L(2)) || 480 (esr == ESR_ELx_FSC_ADDRSZ_L(1)) || 481 (esr == ESR_ELx_FSC_ADDRSZ_L(0)) || 482 (esr == ESR_ELx_FSC_ADDRSZ_L(-1)); 483 } 484 485 static inline bool esr_fsc_is_sea_ttw(unsigned long esr) 486 { 487 esr = esr & ESR_ELx_FSC; 488 489 return (esr == ESR_ELx_FSC_SEA_TTW(3)) || 490 (esr == ESR_ELx_FSC_SEA_TTW(2)) || 491 (esr == ESR_ELx_FSC_SEA_TTW(1)) || 492 (esr == ESR_ELx_FSC_SEA_TTW(0)) || 493 (esr == ESR_ELx_FSC_SEA_TTW(-1)); 494 } 495 496 static inline bool esr_fsc_is_secc_ttw(unsigned long esr) 497 { 498 esr = esr & ESR_ELx_FSC; 499 500 return (esr == ESR_ELx_FSC_SECC_TTW(3)) || 501 (esr == ESR_ELx_FSC_SECC_TTW(2)) || 502 (esr == ESR_ELx_FSC_SECC_TTW(1)) || 503 (esr == ESR_ELx_FSC_SECC_TTW(0)) || 504 (esr == ESR_ELx_FSC_SECC_TTW(-1)); 505 } 506 507 /* Indicate whether ESR.EC==0x1A is for an ERETAx instruction */ 508 static inline bool esr_iss_is_eretax(unsigned long esr) 509 { 510 return esr & ESR_ELx_ERET_ISS_ERET; 511 } 512 513 /* Indicate which key is used for ERETAx (false: A-Key, true: B-Key) */ 514 static inline bool esr_iss_is_eretab(unsigned long esr) 515 { 516 return esr & ESR_ELx_ERET_ISS_ERETA; 517 } 518 519 const char *esr_get_class_string(unsigned long esr); 520 #endif /* __ASSEMBLY */ 521 522 #endif /* __ASM_ESR_H */ 523