1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #ifndef __ASM_ESR_H 8 #define __ASM_ESR_H 9 10 #include <asm/memory.h> 11 #include <asm/sysreg.h> 12 13 #define ESR_ELx_EC_UNKNOWN UL(0x00) 14 #define ESR_ELx_EC_WFx UL(0x01) 15 /* Unallocated EC: 0x02 */ 16 #define ESR_ELx_EC_CP15_32 UL(0x03) 17 #define ESR_ELx_EC_CP15_64 UL(0x04) 18 #define ESR_ELx_EC_CP14_MR UL(0x05) 19 #define ESR_ELx_EC_CP14_LS UL(0x06) 20 #define ESR_ELx_EC_FP_ASIMD UL(0x07) 21 #define ESR_ELx_EC_CP10_ID UL(0x08) /* EL2 only */ 22 #define ESR_ELx_EC_PAC UL(0x09) /* EL2 and above */ 23 #define ESR_ELx_EC_OTHER UL(0x0A) 24 /* Unallocated EC: 0x0B */ 25 #define ESR_ELx_EC_CP14_64 UL(0x0C) 26 #define ESR_ELx_EC_BTI UL(0x0D) 27 #define ESR_ELx_EC_ILL UL(0x0E) 28 /* Unallocated EC: 0x0F - 0x10 */ 29 #define ESR_ELx_EC_SVC32 UL(0x11) 30 #define ESR_ELx_EC_HVC32 UL(0x12) /* EL2 only */ 31 #define ESR_ELx_EC_SMC32 UL(0x13) /* EL2 and above */ 32 /* Unallocated EC: 0x14 */ 33 #define ESR_ELx_EC_SVC64 UL(0x15) 34 #define ESR_ELx_EC_HVC64 UL(0x16) /* EL2 and above */ 35 #define ESR_ELx_EC_SMC64 UL(0x17) /* EL2 and above */ 36 #define ESR_ELx_EC_SYS64 UL(0x18) 37 #define ESR_ELx_EC_SVE UL(0x19) 38 #define ESR_ELx_EC_ERET UL(0x1a) /* EL2 only */ 39 /* Unallocated EC: 0x1B */ 40 #define ESR_ELx_EC_FPAC UL(0x1C) /* EL1 and above */ 41 #define ESR_ELx_EC_SME UL(0x1D) 42 /* Unallocated EC: 0x1E */ 43 #define ESR_ELx_EC_IMP_DEF UL(0x1f) /* EL3 only */ 44 #define ESR_ELx_EC_IABT_LOW UL(0x20) 45 #define ESR_ELx_EC_IABT_CUR UL(0x21) 46 #define ESR_ELx_EC_PC_ALIGN UL(0x22) 47 /* Unallocated EC: 0x23 */ 48 #define ESR_ELx_EC_DABT_LOW UL(0x24) 49 #define ESR_ELx_EC_DABT_CUR UL(0x25) 50 #define ESR_ELx_EC_SP_ALIGN UL(0x26) 51 #define ESR_ELx_EC_MOPS UL(0x27) 52 #define ESR_ELx_EC_FP_EXC32 UL(0x28) 53 /* Unallocated EC: 0x29 - 0x2B */ 54 #define ESR_ELx_EC_FP_EXC64 UL(0x2C) 55 #define ESR_ELx_EC_GCS UL(0x2D) 56 /* Unallocated EC: 0x2E */ 57 #define ESR_ELx_EC_SERROR UL(0x2F) 58 #define ESR_ELx_EC_BREAKPT_LOW UL(0x30) 59 #define ESR_ELx_EC_BREAKPT_CUR UL(0x31) 60 #define ESR_ELx_EC_SOFTSTP_LOW UL(0x32) 61 #define ESR_ELx_EC_SOFTSTP_CUR UL(0x33) 62 #define ESR_ELx_EC_WATCHPT_LOW UL(0x34) 63 #define ESR_ELx_EC_WATCHPT_CUR UL(0x35) 64 /* Unallocated EC: 0x36 - 0x37 */ 65 #define ESR_ELx_EC_BKPT32 UL(0x38) 66 /* Unallocated EC: 0x39 */ 67 #define ESR_ELx_EC_VECTOR32 UL(0x3A) /* EL2 only */ 68 /* Unallocated EC: 0x3B */ 69 #define ESR_ELx_EC_BRK64 UL(0x3C) 70 /* Unallocated EC: 0x3D - 0x3F */ 71 #define ESR_ELx_EC_MAX UL(0x3F) 72 73 #define ESR_ELx_EC_SHIFT (26) 74 #define ESR_ELx_EC_WIDTH (6) 75 #define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT) 76 #define ESR_ELx_EC(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) 77 78 #define ESR_ELx_IL_SHIFT (25) 79 #define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT) 80 #define ESR_ELx_ISS_MASK (GENMASK(24, 0)) 81 #define ESR_ELx_ISS(esr) ((esr) & ESR_ELx_ISS_MASK) 82 #define ESR_ELx_ISS2_SHIFT (32) 83 #define ESR_ELx_ISS2_MASK (GENMASK_ULL(55, 32)) 84 #define ESR_ELx_ISS2(esr) (((esr) & ESR_ELx_ISS2_MASK) >> ESR_ELx_ISS2_SHIFT) 85 86 /* ISS field definitions shared by different classes */ 87 #define ESR_ELx_WNR_SHIFT (6) 88 #define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT) 89 90 /* Asynchronous Error Type */ 91 #define ESR_ELx_IDS_SHIFT (24) 92 #define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT) 93 #define ESR_ELx_AET_SHIFT (10) 94 #define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT) 95 96 #define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT) 97 #define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT) 98 #define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT) 99 #define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT) 100 #define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT) 101 102 /* Shared ISS field definitions for Data/Instruction aborts */ 103 #define ESR_ELx_VNCR_SHIFT (13) 104 #define ESR_ELx_VNCR (UL(1) << ESR_ELx_VNCR_SHIFT) 105 #define ESR_ELx_SET_SHIFT (11) 106 #define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT) 107 #define ESR_ELx_FnV_SHIFT (10) 108 #define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT) 109 #define ESR_ELx_EA_SHIFT (9) 110 #define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT) 111 #define ESR_ELx_S1PTW_SHIFT (7) 112 #define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT) 113 114 /* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */ 115 #define ESR_ELx_FSC (0x3F) 116 #define ESR_ELx_FSC_TYPE (0x3C) 117 #define ESR_ELx_FSC_LEVEL (0x03) 118 #define ESR_ELx_FSC_EXTABT (0x10) 119 #define ESR_ELx_FSC_MTE (0x11) 120 #define ESR_ELx_FSC_SERROR (0x11) 121 #define ESR_ELx_FSC_ACCESS (0x08) 122 #define ESR_ELx_FSC_FAULT (0x04) 123 #define ESR_ELx_FSC_PERM (0x0C) 124 #define ESR_ELx_FSC_SEA_TTW(n) (0x14 + (n)) 125 #define ESR_ELx_FSC_SECC (0x18) 126 #define ESR_ELx_FSC_SECC_TTW(n) (0x1c + (n)) 127 #define ESR_ELx_FSC_EXCL_ATOMIC (0x35) 128 #define ESR_ELx_FSC_ADDRSZ (0x00) 129 130 /* 131 * Annoyingly, the negative levels for Address size faults aren't laid out 132 * contiguously (or in the desired order) 133 */ 134 #define ESR_ELx_FSC_ADDRSZ_nL(n) ((n) == -1 ? 0x25 : 0x2C) 135 #define ESR_ELx_FSC_ADDRSZ_L(n) ((n) < 0 ? ESR_ELx_FSC_ADDRSZ_nL(n) : \ 136 (ESR_ELx_FSC_ADDRSZ + (n))) 137 138 /* Status codes for individual page table levels */ 139 #define ESR_ELx_FSC_ACCESS_L(n) (ESR_ELx_FSC_ACCESS + (n)) 140 #define ESR_ELx_FSC_PERM_L(n) (ESR_ELx_FSC_PERM + (n)) 141 142 #define ESR_ELx_FSC_FAULT_nL (0x2C) 143 #define ESR_ELx_FSC_FAULT_L(n) (((n) < 0 ? ESR_ELx_FSC_FAULT_nL : \ 144 ESR_ELx_FSC_FAULT) + (n)) 145 146 /* ISS field definitions for Data Aborts */ 147 #define ESR_ELx_ISV_SHIFT (24) 148 #define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT) 149 #define ESR_ELx_SAS_SHIFT (22) 150 #define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT) 151 #define ESR_ELx_SSE_SHIFT (21) 152 #define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT) 153 #define ESR_ELx_SRT_SHIFT (16) 154 #define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT) 155 #define ESR_ELx_SF_SHIFT (15) 156 #define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT) 157 #define ESR_ELx_AR_SHIFT (14) 158 #define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT) 159 #define ESR_ELx_CM_SHIFT (8) 160 #define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT) 161 162 /* ISS2 field definitions for Data Aborts */ 163 #define ESR_ELx_TnD_SHIFT (10) 164 #define ESR_ELx_TnD (UL(1) << ESR_ELx_TnD_SHIFT) 165 #define ESR_ELx_TagAccess_SHIFT (9) 166 #define ESR_ELx_TagAccess (UL(1) << ESR_ELx_TagAccess_SHIFT) 167 #define ESR_ELx_GCS_SHIFT (8) 168 #define ESR_ELx_GCS (UL(1) << ESR_ELx_GCS_SHIFT) 169 #define ESR_ELx_Overlay_SHIFT (6) 170 #define ESR_ELx_Overlay (UL(1) << ESR_ELx_Overlay_SHIFT) 171 #define ESR_ELx_DirtyBit_SHIFT (5) 172 #define ESR_ELx_DirtyBit (UL(1) << ESR_ELx_DirtyBit_SHIFT) 173 #define ESR_ELx_Xs_SHIFT (0) 174 #define ESR_ELx_Xs_MASK (GENMASK_ULL(4, 0)) 175 176 /* ISS field definitions for exceptions taken in to Hyp */ 177 #define ESR_ELx_CV (UL(1) << 24) 178 #define ESR_ELx_COND_SHIFT (20) 179 #define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT) 180 #define ESR_ELx_WFx_ISS_RN (UL(0x1F) << 5) 181 #define ESR_ELx_WFx_ISS_RV (UL(1) << 2) 182 #define ESR_ELx_WFx_ISS_TI (UL(3) << 0) 183 #define ESR_ELx_WFx_ISS_WFxT (UL(2) << 0) 184 #define ESR_ELx_WFx_ISS_WFI (UL(0) << 0) 185 #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0) 186 #define ESR_ELx_xVC_IMM_MASK ((UL(1) << 16) - 1) 187 188 /* ISS definitions for LD64B/ST64B/{T,P}SBCSYNC instructions */ 189 #define ESR_ELx_ISS_OTHER_ST64BV (0) 190 #define ESR_ELx_ISS_OTHER_ST64BV0 (1) 191 #define ESR_ELx_ISS_OTHER_LDST64B (2) 192 #define ESR_ELx_ISS_OTHER_TSBCSYNC (3) 193 #define ESR_ELx_ISS_OTHER_PSBCSYNC (4) 194 195 #define DISR_EL1_IDS (UL(1) << 24) 196 /* 197 * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean 198 * different things in the future... 199 */ 200 #define DISR_EL1_ESR_MASK (ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC) 201 202 /* ESR value templates for specific events */ 203 #define ESR_ELx_WFx_MASK (ESR_ELx_EC_MASK | \ 204 (ESR_ELx_WFx_ISS_TI & ~ESR_ELx_WFx_ISS_WFxT)) 205 #define ESR_ELx_WFx_WFI_VAL ((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) | \ 206 ESR_ELx_WFx_ISS_WFI) 207 208 /* BRK instruction trap from AArch64 state */ 209 #define ESR_ELx_BRK64_ISS_COMMENT_MASK 0xffff 210 211 /* ISS field definitions for System instruction traps */ 212 #define ESR_ELx_SYS64_ISS_RES0_SHIFT 22 213 #define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT) 214 #define ESR_ELx_SYS64_ISS_DIR_MASK 0x1 215 #define ESR_ELx_SYS64_ISS_DIR_READ 0x1 216 #define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0 217 218 #define ESR_ELx_SYS64_ISS_RT_SHIFT 5 219 #define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT) 220 #define ESR_ELx_SYS64_ISS_CRM_SHIFT 1 221 #define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT) 222 #define ESR_ELx_SYS64_ISS_CRN_SHIFT 10 223 #define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT) 224 #define ESR_ELx_SYS64_ISS_OP1_SHIFT 14 225 #define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT) 226 #define ESR_ELx_SYS64_ISS_OP2_SHIFT 17 227 #define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT) 228 #define ESR_ELx_SYS64_ISS_OP0_SHIFT 20 229 #define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT) 230 #define ESR_ELx_SYS64_ISS_SYS_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ 231 ESR_ELx_SYS64_ISS_OP1_MASK | \ 232 ESR_ELx_SYS64_ISS_OP2_MASK | \ 233 ESR_ELx_SYS64_ISS_CRN_MASK | \ 234 ESR_ELx_SYS64_ISS_CRM_MASK) 235 #define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \ 236 (((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \ 237 ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \ 238 ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \ 239 ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \ 240 ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT)) 241 242 #define ESR_ELx_SYS64_ISS_SYS_OP_MASK (ESR_ELx_SYS64_ISS_SYS_MASK | \ 243 ESR_ELx_SYS64_ISS_DIR_MASK) 244 #define ESR_ELx_SYS64_ISS_RT(esr) \ 245 (((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT) 246 /* 247 * User space cache operations have the following sysreg encoding 248 * in System instructions. 249 * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0) 250 */ 251 #define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14 252 #define ESR_ELx_SYS64_ISS_CRM_DC_CVADP 13 253 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAP 12 254 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11 255 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10 256 #define ESR_ELx_SYS64_ISS_CRM_IC_IVAU 5 257 258 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ 259 ESR_ELx_SYS64_ISS_OP1_MASK | \ 260 ESR_ELx_SYS64_ISS_OP2_MASK | \ 261 ESR_ELx_SYS64_ISS_CRN_MASK | \ 262 ESR_ELx_SYS64_ISS_DIR_MASK) 263 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \ 264 (ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \ 265 ESR_ELx_SYS64_ISS_DIR_WRITE) 266 /* 267 * User space MRS operations which are supported for emulation 268 * have the following sysreg encoding in System instructions. 269 * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1) 270 */ 271 #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ 272 ESR_ELx_SYS64_ISS_OP1_MASK | \ 273 ESR_ELx_SYS64_ISS_CRN_MASK | \ 274 ESR_ELx_SYS64_ISS_DIR_MASK) 275 #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \ 276 (ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \ 277 ESR_ELx_SYS64_ISS_DIR_READ) 278 279 #define ESR_ELx_SYS64_ISS_SYS_CTR ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0) 280 #define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \ 281 ESR_ELx_SYS64_ISS_DIR_READ) 282 283 #define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \ 284 ESR_ELx_SYS64_ISS_DIR_READ) 285 286 #define ESR_ELx_SYS64_ISS_SYS_CNTVCTSS (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 6, 14, 0) | \ 287 ESR_ELx_SYS64_ISS_DIR_READ) 288 289 #define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \ 290 ESR_ELx_SYS64_ISS_DIR_READ) 291 292 #define esr_sys64_to_sysreg(e) \ 293 sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> \ 294 ESR_ELx_SYS64_ISS_OP0_SHIFT), \ 295 (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \ 296 ESR_ELx_SYS64_ISS_OP1_SHIFT), \ 297 (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \ 298 ESR_ELx_SYS64_ISS_CRN_SHIFT), \ 299 (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \ 300 ESR_ELx_SYS64_ISS_CRM_SHIFT), \ 301 (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \ 302 ESR_ELx_SYS64_ISS_OP2_SHIFT)) 303 304 #define esr_cp15_to_sysreg(e) \ 305 sys_reg(3, \ 306 (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \ 307 ESR_ELx_SYS64_ISS_OP1_SHIFT), \ 308 (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \ 309 ESR_ELx_SYS64_ISS_CRN_SHIFT), \ 310 (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \ 311 ESR_ELx_SYS64_ISS_CRM_SHIFT), \ 312 (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \ 313 ESR_ELx_SYS64_ISS_OP2_SHIFT)) 314 315 /* ISS field definitions for ERET/ERETAA/ERETAB trapping */ 316 #define ESR_ELx_ERET_ISS_ERET 0x2 317 #define ESR_ELx_ERET_ISS_ERETA 0x1 318 319 /* 320 * ISS field definitions for floating-point exception traps 321 * (FP_EXC_32/FP_EXC_64). 322 * 323 * (The FPEXC_* constants are used instead for common bits.) 324 */ 325 326 #define ESR_ELx_FP_EXC_TFV (UL(1) << 23) 327 328 /* 329 * ISS field definitions for CP15 accesses 330 */ 331 #define ESR_ELx_CP15_32_ISS_DIR_MASK 0x1 332 #define ESR_ELx_CP15_32_ISS_DIR_READ 0x1 333 #define ESR_ELx_CP15_32_ISS_DIR_WRITE 0x0 334 335 #define ESR_ELx_CP15_32_ISS_RT_SHIFT 5 336 #define ESR_ELx_CP15_32_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT) 337 #define ESR_ELx_CP15_32_ISS_CRM_SHIFT 1 338 #define ESR_ELx_CP15_32_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT) 339 #define ESR_ELx_CP15_32_ISS_CRN_SHIFT 10 340 #define ESR_ELx_CP15_32_ISS_CRN_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) 341 #define ESR_ELx_CP15_32_ISS_OP1_SHIFT 14 342 #define ESR_ELx_CP15_32_ISS_OP1_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) 343 #define ESR_ELx_CP15_32_ISS_OP2_SHIFT 17 344 #define ESR_ELx_CP15_32_ISS_OP2_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) 345 346 #define ESR_ELx_CP15_32_ISS_SYS_MASK (ESR_ELx_CP15_32_ISS_OP1_MASK | \ 347 ESR_ELx_CP15_32_ISS_OP2_MASK | \ 348 ESR_ELx_CP15_32_ISS_CRN_MASK | \ 349 ESR_ELx_CP15_32_ISS_CRM_MASK | \ 350 ESR_ELx_CP15_32_ISS_DIR_MASK) 351 #define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \ 352 (((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \ 353 ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \ 354 ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \ 355 ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)) 356 357 #define ESR_ELx_CP15_64_ISS_DIR_MASK 0x1 358 #define ESR_ELx_CP15_64_ISS_DIR_READ 0x1 359 #define ESR_ELx_CP15_64_ISS_DIR_WRITE 0x0 360 361 #define ESR_ELx_CP15_64_ISS_RT_SHIFT 5 362 #define ESR_ELx_CP15_64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT) 363 364 #define ESR_ELx_CP15_64_ISS_RT2_SHIFT 10 365 #define ESR_ELx_CP15_64_ISS_RT2_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT) 366 367 #define ESR_ELx_CP15_64_ISS_OP1_SHIFT 16 368 #define ESR_ELx_CP15_64_ISS_OP1_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) 369 #define ESR_ELx_CP15_64_ISS_CRM_SHIFT 1 370 #define ESR_ELx_CP15_64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT) 371 372 #define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \ 373 (((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \ 374 ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)) 375 376 #define ESR_ELx_CP15_64_ISS_SYS_MASK (ESR_ELx_CP15_64_ISS_OP1_MASK | \ 377 ESR_ELx_CP15_64_ISS_CRM_MASK | \ 378 ESR_ELx_CP15_64_ISS_DIR_MASK) 379 380 #define ESR_ELx_CP15_64_ISS_SYS_CNTVCT (ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \ 381 ESR_ELx_CP15_64_ISS_DIR_READ) 382 383 #define ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS (ESR_ELx_CP15_64_ISS_SYS_VAL(9, 14) | \ 384 ESR_ELx_CP15_64_ISS_DIR_READ) 385 386 #define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ (ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\ 387 ESR_ELx_CP15_32_ISS_DIR_READ) 388 389 /* 390 * ISS values for SME traps 391 */ 392 #define ESR_ELx_SME_ISS_SMTC_MASK GENMASK(2, 0) 393 #define ESR_ELx_SME_ISS_SMTC(esr) ((esr) & ESR_ELx_SME_ISS_SMTC_MASK) 394 395 #define ESR_ELx_SME_ISS_SMTC_SME_DISABLED 0 396 #define ESR_ELx_SME_ISS_SMTC_ILL 1 397 #define ESR_ELx_SME_ISS_SMTC_SM_DISABLED 2 398 #define ESR_ELx_SME_ISS_SMTC_ZA_DISABLED 3 399 #define ESR_ELx_SME_ISS_SMTC_ZT_DISABLED 4 400 401 /* ISS field definitions for MOPS exceptions */ 402 #define ESR_ELx_MOPS_ISS_MEM_INST (UL(1) << 24) 403 #define ESR_ELx_MOPS_ISS_FROM_EPILOGUE (UL(1) << 18) 404 #define ESR_ELx_MOPS_ISS_WRONG_OPTION (UL(1) << 17) 405 #define ESR_ELx_MOPS_ISS_OPTION_A (UL(1) << 16) 406 #define ESR_ELx_MOPS_ISS_DESTREG(esr) (((esr) & (UL(0x1f) << 10)) >> 10) 407 #define ESR_ELx_MOPS_ISS_SRCREG(esr) (((esr) & (UL(0x1f) << 5)) >> 5) 408 #define ESR_ELx_MOPS_ISS_SIZEREG(esr) (((esr) & (UL(0x1f) << 0)) >> 0) 409 410 /* ISS field definitions for GCS */ 411 #define ESR_ELx_ExType_SHIFT (20) 412 #define ESR_ELx_ExType_MASK GENMASK(23, 20) 413 #define ESR_ELx_Raddr_SHIFT (10) 414 #define ESR_ELx_Raddr_MASK GENMASK(14, 10) 415 #define ESR_ELx_Rn_SHIFT (5) 416 #define ESR_ELx_Rn_MASK GENMASK(9, 5) 417 #define ESR_ELx_Rvalue_SHIFT 5 418 #define ESR_ELx_Rvalue_MASK GENMASK(9, 5) 419 #define ESR_ELx_IT_SHIFT (0) 420 #define ESR_ELx_IT_MASK GENMASK(4, 0) 421 422 #define ESR_ELx_ExType_DATA_CHECK 0 423 #define ESR_ELx_ExType_EXLOCK 1 424 #define ESR_ELx_ExType_STR 2 425 426 #define ESR_ELx_IT_RET 0 427 #define ESR_ELx_IT_GCSPOPM 1 428 #define ESR_ELx_IT_RET_KEYA 2 429 #define ESR_ELx_IT_RET_KEYB 3 430 #define ESR_ELx_IT_GCSSS1 4 431 #define ESR_ELx_IT_GCSSS2 5 432 #define ESR_ELx_IT_GCSPOPCX 6 433 #define ESR_ELx_IT_GCSPOPX 7 434 435 #ifndef __ASSEMBLER__ 436 #include <asm/types.h> 437 438 static inline unsigned long esr_brk_comment(unsigned long esr) 439 { 440 return esr & ESR_ELx_BRK64_ISS_COMMENT_MASK; 441 } 442 443 static inline bool esr_is_data_abort(unsigned long esr) 444 { 445 const unsigned long ec = ESR_ELx_EC(esr); 446 447 return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR; 448 } 449 450 static inline bool esr_is_cfi_brk(unsigned long esr) 451 { 452 return ESR_ELx_EC(esr) == ESR_ELx_EC_BRK64 && 453 (esr_brk_comment(esr) & ~CFI_BRK_IMM_MASK) == CFI_BRK_IMM_BASE; 454 } 455 456 static inline bool esr_is_ubsan_brk(unsigned long esr) 457 { 458 return (esr_brk_comment(esr) & ~UBSAN_BRK_MASK) == UBSAN_BRK_IMM; 459 } 460 461 static inline bool esr_fsc_is_translation_fault(unsigned long esr) 462 { 463 esr = esr & ESR_ELx_FSC; 464 465 return (esr == ESR_ELx_FSC_FAULT_L(3)) || 466 (esr == ESR_ELx_FSC_FAULT_L(2)) || 467 (esr == ESR_ELx_FSC_FAULT_L(1)) || 468 (esr == ESR_ELx_FSC_FAULT_L(0)) || 469 (esr == ESR_ELx_FSC_FAULT_L(-1)); 470 } 471 472 static inline bool esr_fsc_is_permission_fault(unsigned long esr) 473 { 474 esr = esr & ESR_ELx_FSC; 475 476 return (esr == ESR_ELx_FSC_PERM_L(3)) || 477 (esr == ESR_ELx_FSC_PERM_L(2)) || 478 (esr == ESR_ELx_FSC_PERM_L(1)) || 479 (esr == ESR_ELx_FSC_PERM_L(0)); 480 } 481 482 static inline bool esr_fsc_is_access_flag_fault(unsigned long esr) 483 { 484 esr = esr & ESR_ELx_FSC; 485 486 return (esr == ESR_ELx_FSC_ACCESS_L(3)) || 487 (esr == ESR_ELx_FSC_ACCESS_L(2)) || 488 (esr == ESR_ELx_FSC_ACCESS_L(1)) || 489 (esr == ESR_ELx_FSC_ACCESS_L(0)); 490 } 491 492 static inline bool esr_fsc_is_excl_atomic_fault(unsigned long esr) 493 { 494 esr = esr & ESR_ELx_FSC; 495 496 return esr == ESR_ELx_FSC_EXCL_ATOMIC; 497 } 498 499 static inline bool esr_fsc_is_addr_sz_fault(unsigned long esr) 500 { 501 esr &= ESR_ELx_FSC; 502 503 return (esr == ESR_ELx_FSC_ADDRSZ_L(3)) || 504 (esr == ESR_ELx_FSC_ADDRSZ_L(2)) || 505 (esr == ESR_ELx_FSC_ADDRSZ_L(1)) || 506 (esr == ESR_ELx_FSC_ADDRSZ_L(0)) || 507 (esr == ESR_ELx_FSC_ADDRSZ_L(-1)); 508 } 509 510 static inline bool esr_fsc_is_sea_ttw(unsigned long esr) 511 { 512 esr = esr & ESR_ELx_FSC; 513 514 return (esr == ESR_ELx_FSC_SEA_TTW(3)) || 515 (esr == ESR_ELx_FSC_SEA_TTW(2)) || 516 (esr == ESR_ELx_FSC_SEA_TTW(1)) || 517 (esr == ESR_ELx_FSC_SEA_TTW(0)) || 518 (esr == ESR_ELx_FSC_SEA_TTW(-1)); 519 } 520 521 static inline bool esr_fsc_is_secc_ttw(unsigned long esr) 522 { 523 esr = esr & ESR_ELx_FSC; 524 525 return (esr == ESR_ELx_FSC_SECC_TTW(3)) || 526 (esr == ESR_ELx_FSC_SECC_TTW(2)) || 527 (esr == ESR_ELx_FSC_SECC_TTW(1)) || 528 (esr == ESR_ELx_FSC_SECC_TTW(0)) || 529 (esr == ESR_ELx_FSC_SECC_TTW(-1)); 530 } 531 532 /* Indicate whether ESR.EC==0x1A is for an ERETAx instruction */ 533 static inline bool esr_iss_is_eretax(unsigned long esr) 534 { 535 return esr & ESR_ELx_ERET_ISS_ERET; 536 } 537 538 /* Indicate which key is used for ERETAx (false: A-Key, true: B-Key) */ 539 static inline bool esr_iss_is_eretab(unsigned long esr) 540 { 541 return esr & ESR_ELx_ERET_ISS_ERETA; 542 } 543 544 const char *esr_get_class_string(unsigned long esr); 545 #endif /* __ASSEMBLER__ */ 546 547 #endif /* __ASM_ESR_H */ 548