1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #ifndef __ASM_ESR_H 8 #define __ASM_ESR_H 9 10 #include <asm/memory.h> 11 #include <asm/sysreg.h> 12 13 #define ESR_ELx_EC_UNKNOWN UL(0x00) 14 #define ESR_ELx_EC_WFx UL(0x01) 15 /* Unallocated EC: 0x02 */ 16 #define ESR_ELx_EC_CP15_32 UL(0x03) 17 #define ESR_ELx_EC_CP15_64 UL(0x04) 18 #define ESR_ELx_EC_CP14_MR UL(0x05) 19 #define ESR_ELx_EC_CP14_LS UL(0x06) 20 #define ESR_ELx_EC_FP_ASIMD UL(0x07) 21 #define ESR_ELx_EC_CP10_ID UL(0x08) /* EL2 only */ 22 #define ESR_ELx_EC_PAC UL(0x09) /* EL2 and above */ 23 /* Unallocated EC: 0x0A - 0x0B */ 24 #define ESR_ELx_EC_CP14_64 UL(0x0C) 25 #define ESR_ELx_EC_BTI UL(0x0D) 26 #define ESR_ELx_EC_ILL UL(0x0E) 27 /* Unallocated EC: 0x0F - 0x10 */ 28 #define ESR_ELx_EC_SVC32 UL(0x11) 29 #define ESR_ELx_EC_HVC32 UL(0x12) /* EL2 only */ 30 #define ESR_ELx_EC_SMC32 UL(0x13) /* EL2 and above */ 31 /* Unallocated EC: 0x14 */ 32 #define ESR_ELx_EC_SVC64 UL(0x15) 33 #define ESR_ELx_EC_HVC64 UL(0x16) /* EL2 and above */ 34 #define ESR_ELx_EC_SMC64 UL(0x17) /* EL2 and above */ 35 #define ESR_ELx_EC_SYS64 UL(0x18) 36 #define ESR_ELx_EC_SVE UL(0x19) 37 #define ESR_ELx_EC_ERET UL(0x1a) /* EL2 only */ 38 /* Unallocated EC: 0x1B */ 39 #define ESR_ELx_EC_FPAC UL(0x1C) /* EL1 and above */ 40 #define ESR_ELx_EC_SME UL(0x1D) 41 /* Unallocated EC: 0x1E */ 42 #define ESR_ELx_EC_IMP_DEF UL(0x1f) /* EL3 only */ 43 #define ESR_ELx_EC_IABT_LOW UL(0x20) 44 #define ESR_ELx_EC_IABT_CUR UL(0x21) 45 #define ESR_ELx_EC_PC_ALIGN UL(0x22) 46 /* Unallocated EC: 0x23 */ 47 #define ESR_ELx_EC_DABT_LOW UL(0x24) 48 #define ESR_ELx_EC_DABT_CUR UL(0x25) 49 #define ESR_ELx_EC_SP_ALIGN UL(0x26) 50 #define ESR_ELx_EC_MOPS UL(0x27) 51 #define ESR_ELx_EC_FP_EXC32 UL(0x28) 52 /* Unallocated EC: 0x29 - 0x2B */ 53 #define ESR_ELx_EC_FP_EXC64 UL(0x2C) 54 /* Unallocated EC: 0x2D - 0x2E */ 55 #define ESR_ELx_EC_SERROR UL(0x2F) 56 #define ESR_ELx_EC_BREAKPT_LOW UL(0x30) 57 #define ESR_ELx_EC_BREAKPT_CUR UL(0x31) 58 #define ESR_ELx_EC_SOFTSTP_LOW UL(0x32) 59 #define ESR_ELx_EC_SOFTSTP_CUR UL(0x33) 60 #define ESR_ELx_EC_WATCHPT_LOW UL(0x34) 61 #define ESR_ELx_EC_WATCHPT_CUR UL(0x35) 62 /* Unallocated EC: 0x36 - 0x37 */ 63 #define ESR_ELx_EC_BKPT32 UL(0x38) 64 /* Unallocated EC: 0x39 */ 65 #define ESR_ELx_EC_VECTOR32 UL(0x3A) /* EL2 only */ 66 /* Unallocated EC: 0x3B */ 67 #define ESR_ELx_EC_BRK64 UL(0x3C) 68 /* Unallocated EC: 0x3D - 0x3F */ 69 #define ESR_ELx_EC_MAX UL(0x3F) 70 71 #define ESR_ELx_EC_SHIFT (26) 72 #define ESR_ELx_EC_WIDTH (6) 73 #define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT) 74 #define ESR_ELx_EC(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) 75 76 #define ESR_ELx_IL_SHIFT (25) 77 #define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT) 78 #define ESR_ELx_ISS_MASK (GENMASK(24, 0)) 79 #define ESR_ELx_ISS(esr) ((esr) & ESR_ELx_ISS_MASK) 80 #define ESR_ELx_ISS2_SHIFT (32) 81 #define ESR_ELx_ISS2_MASK (GENMASK_ULL(55, 32)) 82 #define ESR_ELx_ISS2(esr) (((esr) & ESR_ELx_ISS2_MASK) >> ESR_ELx_ISS2_SHIFT) 83 84 /* ISS field definitions shared by different classes */ 85 #define ESR_ELx_WNR_SHIFT (6) 86 #define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT) 87 88 /* Asynchronous Error Type */ 89 #define ESR_ELx_IDS_SHIFT (24) 90 #define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT) 91 #define ESR_ELx_AET_SHIFT (10) 92 #define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT) 93 94 #define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT) 95 #define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT) 96 #define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT) 97 #define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT) 98 #define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT) 99 100 /* Shared ISS field definitions for Data/Instruction aborts */ 101 #define ESR_ELx_SET_SHIFT (11) 102 #define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT) 103 #define ESR_ELx_FnV_SHIFT (10) 104 #define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT) 105 #define ESR_ELx_EA_SHIFT (9) 106 #define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT) 107 #define ESR_ELx_S1PTW_SHIFT (7) 108 #define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT) 109 110 /* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */ 111 #define ESR_ELx_FSC (0x3F) 112 #define ESR_ELx_FSC_TYPE (0x3C) 113 #define ESR_ELx_FSC_LEVEL (0x03) 114 #define ESR_ELx_FSC_EXTABT (0x10) 115 #define ESR_ELx_FSC_MTE (0x11) 116 #define ESR_ELx_FSC_SERROR (0x11) 117 #define ESR_ELx_FSC_ACCESS (0x08) 118 #define ESR_ELx_FSC_FAULT (0x04) 119 #define ESR_ELx_FSC_PERM (0x0C) 120 #define ESR_ELx_FSC_SEA_TTW(n) (0x14 + (n)) 121 #define ESR_ELx_FSC_SECC (0x18) 122 #define ESR_ELx_FSC_SECC_TTW(n) (0x1c + (n)) 123 124 /* Status codes for individual page table levels */ 125 #define ESR_ELx_FSC_ACCESS_L(n) (ESR_ELx_FSC_ACCESS + (n)) 126 #define ESR_ELx_FSC_PERM_L(n) (ESR_ELx_FSC_PERM + (n)) 127 128 #define ESR_ELx_FSC_FAULT_nL (0x2C) 129 #define ESR_ELx_FSC_FAULT_L(n) (((n) < 0 ? ESR_ELx_FSC_FAULT_nL : \ 130 ESR_ELx_FSC_FAULT) + (n)) 131 132 /* ISS field definitions for Data Aborts */ 133 #define ESR_ELx_ISV_SHIFT (24) 134 #define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT) 135 #define ESR_ELx_SAS_SHIFT (22) 136 #define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT) 137 #define ESR_ELx_SSE_SHIFT (21) 138 #define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT) 139 #define ESR_ELx_SRT_SHIFT (16) 140 #define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT) 141 #define ESR_ELx_SF_SHIFT (15) 142 #define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT) 143 #define ESR_ELx_AR_SHIFT (14) 144 #define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT) 145 #define ESR_ELx_CM_SHIFT (8) 146 #define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT) 147 148 /* ISS2 field definitions for Data Aborts */ 149 #define ESR_ELx_TnD_SHIFT (10) 150 #define ESR_ELx_TnD (UL(1) << ESR_ELx_TnD_SHIFT) 151 #define ESR_ELx_TagAccess_SHIFT (9) 152 #define ESR_ELx_TagAccess (UL(1) << ESR_ELx_TagAccess_SHIFT) 153 #define ESR_ELx_GCS_SHIFT (8) 154 #define ESR_ELx_GCS (UL(1) << ESR_ELx_GCS_SHIFT) 155 #define ESR_ELx_Overlay_SHIFT (6) 156 #define ESR_ELx_Overlay (UL(1) << ESR_ELx_Overlay_SHIFT) 157 #define ESR_ELx_DirtyBit_SHIFT (5) 158 #define ESR_ELx_DirtyBit (UL(1) << ESR_ELx_DirtyBit_SHIFT) 159 #define ESR_ELx_Xs_SHIFT (0) 160 #define ESR_ELx_Xs_MASK (GENMASK_ULL(4, 0)) 161 162 /* ISS field definitions for exceptions taken in to Hyp */ 163 #define ESR_ELx_FSC_ADDRSZ (0x00) 164 #define ESR_ELx_FSC_ADDRSZ_L(n) (ESR_ELx_FSC_ADDRSZ + (n)) 165 #define ESR_ELx_CV (UL(1) << 24) 166 #define ESR_ELx_COND_SHIFT (20) 167 #define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT) 168 #define ESR_ELx_WFx_ISS_RN (UL(0x1F) << 5) 169 #define ESR_ELx_WFx_ISS_RV (UL(1) << 2) 170 #define ESR_ELx_WFx_ISS_TI (UL(3) << 0) 171 #define ESR_ELx_WFx_ISS_WFxT (UL(2) << 0) 172 #define ESR_ELx_WFx_ISS_WFI (UL(0) << 0) 173 #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0) 174 #define ESR_ELx_xVC_IMM_MASK ((UL(1) << 16) - 1) 175 176 #define DISR_EL1_IDS (UL(1) << 24) 177 /* 178 * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean 179 * different things in the future... 180 */ 181 #define DISR_EL1_ESR_MASK (ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC) 182 183 /* ESR value templates for specific events */ 184 #define ESR_ELx_WFx_MASK (ESR_ELx_EC_MASK | \ 185 (ESR_ELx_WFx_ISS_TI & ~ESR_ELx_WFx_ISS_WFxT)) 186 #define ESR_ELx_WFx_WFI_VAL ((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) | \ 187 ESR_ELx_WFx_ISS_WFI) 188 189 /* BRK instruction trap from AArch64 state */ 190 #define ESR_ELx_BRK64_ISS_COMMENT_MASK 0xffff 191 192 /* ISS field definitions for System instruction traps */ 193 #define ESR_ELx_SYS64_ISS_RES0_SHIFT 22 194 #define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT) 195 #define ESR_ELx_SYS64_ISS_DIR_MASK 0x1 196 #define ESR_ELx_SYS64_ISS_DIR_READ 0x1 197 #define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0 198 199 #define ESR_ELx_SYS64_ISS_RT_SHIFT 5 200 #define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT) 201 #define ESR_ELx_SYS64_ISS_CRM_SHIFT 1 202 #define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT) 203 #define ESR_ELx_SYS64_ISS_CRN_SHIFT 10 204 #define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT) 205 #define ESR_ELx_SYS64_ISS_OP1_SHIFT 14 206 #define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT) 207 #define ESR_ELx_SYS64_ISS_OP2_SHIFT 17 208 #define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT) 209 #define ESR_ELx_SYS64_ISS_OP0_SHIFT 20 210 #define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT) 211 #define ESR_ELx_SYS64_ISS_SYS_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ 212 ESR_ELx_SYS64_ISS_OP1_MASK | \ 213 ESR_ELx_SYS64_ISS_OP2_MASK | \ 214 ESR_ELx_SYS64_ISS_CRN_MASK | \ 215 ESR_ELx_SYS64_ISS_CRM_MASK) 216 #define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \ 217 (((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \ 218 ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \ 219 ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \ 220 ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \ 221 ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT)) 222 223 #define ESR_ELx_SYS64_ISS_SYS_OP_MASK (ESR_ELx_SYS64_ISS_SYS_MASK | \ 224 ESR_ELx_SYS64_ISS_DIR_MASK) 225 #define ESR_ELx_SYS64_ISS_RT(esr) \ 226 (((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT) 227 /* 228 * User space cache operations have the following sysreg encoding 229 * in System instructions. 230 * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0) 231 */ 232 #define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14 233 #define ESR_ELx_SYS64_ISS_CRM_DC_CVADP 13 234 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAP 12 235 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11 236 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10 237 #define ESR_ELx_SYS64_ISS_CRM_IC_IVAU 5 238 239 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ 240 ESR_ELx_SYS64_ISS_OP1_MASK | \ 241 ESR_ELx_SYS64_ISS_OP2_MASK | \ 242 ESR_ELx_SYS64_ISS_CRN_MASK | \ 243 ESR_ELx_SYS64_ISS_DIR_MASK) 244 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \ 245 (ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \ 246 ESR_ELx_SYS64_ISS_DIR_WRITE) 247 /* 248 * User space MRS operations which are supported for emulation 249 * have the following sysreg encoding in System instructions. 250 * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1) 251 */ 252 #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ 253 ESR_ELx_SYS64_ISS_OP1_MASK | \ 254 ESR_ELx_SYS64_ISS_CRN_MASK | \ 255 ESR_ELx_SYS64_ISS_DIR_MASK) 256 #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \ 257 (ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \ 258 ESR_ELx_SYS64_ISS_DIR_READ) 259 260 #define ESR_ELx_SYS64_ISS_SYS_CTR ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0) 261 #define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \ 262 ESR_ELx_SYS64_ISS_DIR_READ) 263 264 #define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \ 265 ESR_ELx_SYS64_ISS_DIR_READ) 266 267 #define ESR_ELx_SYS64_ISS_SYS_CNTVCTSS (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 6, 14, 0) | \ 268 ESR_ELx_SYS64_ISS_DIR_READ) 269 270 #define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \ 271 ESR_ELx_SYS64_ISS_DIR_READ) 272 273 #define esr_sys64_to_sysreg(e) \ 274 sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> \ 275 ESR_ELx_SYS64_ISS_OP0_SHIFT), \ 276 (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \ 277 ESR_ELx_SYS64_ISS_OP1_SHIFT), \ 278 (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \ 279 ESR_ELx_SYS64_ISS_CRN_SHIFT), \ 280 (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \ 281 ESR_ELx_SYS64_ISS_CRM_SHIFT), \ 282 (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \ 283 ESR_ELx_SYS64_ISS_OP2_SHIFT)) 284 285 #define esr_cp15_to_sysreg(e) \ 286 sys_reg(3, \ 287 (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \ 288 ESR_ELx_SYS64_ISS_OP1_SHIFT), \ 289 (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \ 290 ESR_ELx_SYS64_ISS_CRN_SHIFT), \ 291 (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \ 292 ESR_ELx_SYS64_ISS_CRM_SHIFT), \ 293 (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \ 294 ESR_ELx_SYS64_ISS_OP2_SHIFT)) 295 296 /* ISS field definitions for ERET/ERETAA/ERETAB trapping */ 297 #define ESR_ELx_ERET_ISS_ERET 0x2 298 #define ESR_ELx_ERET_ISS_ERETA 0x1 299 300 /* 301 * ISS field definitions for floating-point exception traps 302 * (FP_EXC_32/FP_EXC_64). 303 * 304 * (The FPEXC_* constants are used instead for common bits.) 305 */ 306 307 #define ESR_ELx_FP_EXC_TFV (UL(1) << 23) 308 309 /* 310 * ISS field definitions for CP15 accesses 311 */ 312 #define ESR_ELx_CP15_32_ISS_DIR_MASK 0x1 313 #define ESR_ELx_CP15_32_ISS_DIR_READ 0x1 314 #define ESR_ELx_CP15_32_ISS_DIR_WRITE 0x0 315 316 #define ESR_ELx_CP15_32_ISS_RT_SHIFT 5 317 #define ESR_ELx_CP15_32_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT) 318 #define ESR_ELx_CP15_32_ISS_CRM_SHIFT 1 319 #define ESR_ELx_CP15_32_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT) 320 #define ESR_ELx_CP15_32_ISS_CRN_SHIFT 10 321 #define ESR_ELx_CP15_32_ISS_CRN_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) 322 #define ESR_ELx_CP15_32_ISS_OP1_SHIFT 14 323 #define ESR_ELx_CP15_32_ISS_OP1_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) 324 #define ESR_ELx_CP15_32_ISS_OP2_SHIFT 17 325 #define ESR_ELx_CP15_32_ISS_OP2_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) 326 327 #define ESR_ELx_CP15_32_ISS_SYS_MASK (ESR_ELx_CP15_32_ISS_OP1_MASK | \ 328 ESR_ELx_CP15_32_ISS_OP2_MASK | \ 329 ESR_ELx_CP15_32_ISS_CRN_MASK | \ 330 ESR_ELx_CP15_32_ISS_CRM_MASK | \ 331 ESR_ELx_CP15_32_ISS_DIR_MASK) 332 #define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \ 333 (((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \ 334 ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \ 335 ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \ 336 ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)) 337 338 #define ESR_ELx_CP15_64_ISS_DIR_MASK 0x1 339 #define ESR_ELx_CP15_64_ISS_DIR_READ 0x1 340 #define ESR_ELx_CP15_64_ISS_DIR_WRITE 0x0 341 342 #define ESR_ELx_CP15_64_ISS_RT_SHIFT 5 343 #define ESR_ELx_CP15_64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT) 344 345 #define ESR_ELx_CP15_64_ISS_RT2_SHIFT 10 346 #define ESR_ELx_CP15_64_ISS_RT2_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT) 347 348 #define ESR_ELx_CP15_64_ISS_OP1_SHIFT 16 349 #define ESR_ELx_CP15_64_ISS_OP1_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) 350 #define ESR_ELx_CP15_64_ISS_CRM_SHIFT 1 351 #define ESR_ELx_CP15_64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT) 352 353 #define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \ 354 (((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \ 355 ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)) 356 357 #define ESR_ELx_CP15_64_ISS_SYS_MASK (ESR_ELx_CP15_64_ISS_OP1_MASK | \ 358 ESR_ELx_CP15_64_ISS_CRM_MASK | \ 359 ESR_ELx_CP15_64_ISS_DIR_MASK) 360 361 #define ESR_ELx_CP15_64_ISS_SYS_CNTVCT (ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \ 362 ESR_ELx_CP15_64_ISS_DIR_READ) 363 364 #define ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS (ESR_ELx_CP15_64_ISS_SYS_VAL(9, 14) | \ 365 ESR_ELx_CP15_64_ISS_DIR_READ) 366 367 #define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ (ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\ 368 ESR_ELx_CP15_32_ISS_DIR_READ) 369 370 /* 371 * ISS values for SME traps 372 */ 373 374 #define ESR_ELx_SME_ISS_SME_DISABLED 0 375 #define ESR_ELx_SME_ISS_ILL 1 376 #define ESR_ELx_SME_ISS_SM_DISABLED 2 377 #define ESR_ELx_SME_ISS_ZA_DISABLED 3 378 #define ESR_ELx_SME_ISS_ZT_DISABLED 4 379 380 /* ISS field definitions for MOPS exceptions */ 381 #define ESR_ELx_MOPS_ISS_MEM_INST (UL(1) << 24) 382 #define ESR_ELx_MOPS_ISS_FROM_EPILOGUE (UL(1) << 18) 383 #define ESR_ELx_MOPS_ISS_WRONG_OPTION (UL(1) << 17) 384 #define ESR_ELx_MOPS_ISS_OPTION_A (UL(1) << 16) 385 #define ESR_ELx_MOPS_ISS_DESTREG(esr) (((esr) & (UL(0x1f) << 10)) >> 10) 386 #define ESR_ELx_MOPS_ISS_SRCREG(esr) (((esr) & (UL(0x1f) << 5)) >> 5) 387 #define ESR_ELx_MOPS_ISS_SIZEREG(esr) (((esr) & (UL(0x1f) << 0)) >> 0) 388 389 #ifndef __ASSEMBLY__ 390 #include <asm/types.h> 391 392 static inline unsigned long esr_brk_comment(unsigned long esr) 393 { 394 return esr & ESR_ELx_BRK64_ISS_COMMENT_MASK; 395 } 396 397 static inline bool esr_is_data_abort(unsigned long esr) 398 { 399 const unsigned long ec = ESR_ELx_EC(esr); 400 401 return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR; 402 } 403 404 static inline bool esr_is_cfi_brk(unsigned long esr) 405 { 406 return ESR_ELx_EC(esr) == ESR_ELx_EC_BRK64 && 407 (esr_brk_comment(esr) & ~CFI_BRK_IMM_MASK) == CFI_BRK_IMM_BASE; 408 } 409 410 static inline bool esr_fsc_is_translation_fault(unsigned long esr) 411 { 412 esr = esr & ESR_ELx_FSC; 413 414 return (esr == ESR_ELx_FSC_FAULT_L(3)) || 415 (esr == ESR_ELx_FSC_FAULT_L(2)) || 416 (esr == ESR_ELx_FSC_FAULT_L(1)) || 417 (esr == ESR_ELx_FSC_FAULT_L(0)) || 418 (esr == ESR_ELx_FSC_FAULT_L(-1)); 419 } 420 421 static inline bool esr_fsc_is_permission_fault(unsigned long esr) 422 { 423 esr = esr & ESR_ELx_FSC; 424 425 return (esr == ESR_ELx_FSC_PERM_L(3)) || 426 (esr == ESR_ELx_FSC_PERM_L(2)) || 427 (esr == ESR_ELx_FSC_PERM_L(1)) || 428 (esr == ESR_ELx_FSC_PERM_L(0)); 429 } 430 431 static inline bool esr_fsc_is_access_flag_fault(unsigned long esr) 432 { 433 esr = esr & ESR_ELx_FSC; 434 435 return (esr == ESR_ELx_FSC_ACCESS_L(3)) || 436 (esr == ESR_ELx_FSC_ACCESS_L(2)) || 437 (esr == ESR_ELx_FSC_ACCESS_L(1)) || 438 (esr == ESR_ELx_FSC_ACCESS_L(0)); 439 } 440 441 /* Indicate whether ESR.EC==0x1A is for an ERETAx instruction */ 442 static inline bool esr_iss_is_eretax(unsigned long esr) 443 { 444 return esr & ESR_ELx_ERET_ISS_ERET; 445 } 446 447 /* Indicate which key is used for ERETAx (false: A-Key, true: B-Key) */ 448 static inline bool esr_iss_is_eretab(unsigned long esr) 449 { 450 return esr & ESR_ELx_ERET_ISS_ERETA; 451 } 452 453 const char *esr_get_class_string(unsigned long esr); 454 #endif /* __ASSEMBLY */ 455 456 #endif /* __ASM_ESR_H */ 457