1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #ifndef __ARM_KVM_INIT_H__ 8 #define __ARM_KVM_INIT_H__ 9 10 #ifndef __ASSEMBLY__ 11 #error Assembly-only header 12 #endif 13 14 #include <asm/kvm_arm.h> 15 #include <asm/ptrace.h> 16 #include <asm/sysreg.h> 17 #include <linux/irqchip/arm-gic-v3.h> 18 19 .macro init_el2_hcr val 20 mov_q x0, \val 21 22 /* 23 * Compliant CPUs advertise their VHE-onlyness with 24 * ID_AA64MMFR4_EL1.E2H0 < 0. On such CPUs HCR_EL2.E2H is RES1, but it 25 * can reset into an UNKNOWN state and might not read as 1 until it has 26 * been initialized explicitly. 27 * 28 * Fruity CPUs seem to have HCR_EL2.E2H set to RAO/WI, but 29 * don't advertise it (they predate this relaxation). 30 * 31 * Initalize HCR_EL2.E2H so that later code can rely upon HCR_EL2.E2H 32 * indicating whether the CPU is running in E2H mode. 33 */ 34 mrs_s x1, SYS_ID_AA64MMFR4_EL1 35 sbfx x1, x1, #ID_AA64MMFR4_EL1_E2H0_SHIFT, #ID_AA64MMFR4_EL1_E2H0_WIDTH 36 cmp x1, #0 37 b.ge .LnVHE_\@ 38 39 orr x0, x0, #HCR_E2H 40 .LnVHE_\@: 41 msr_hcr_el2 x0 42 isb 43 .endm 44 45 .macro __init_el2_sctlr 46 mov_q x0, INIT_SCTLR_EL2_MMU_OFF 47 msr sctlr_el2, x0 48 isb 49 .endm 50 51 .macro __init_el2_hcrx 52 mrs x0, id_aa64mmfr1_el1 53 ubfx x0, x0, #ID_AA64MMFR1_EL1_HCX_SHIFT, #4 54 cbz x0, .Lskip_hcrx_\@ 55 mov_q x0, (HCRX_EL2_MSCEn | HCRX_EL2_TCR2En | HCRX_EL2_EnFPM) 56 57 /* Enable GCS if supported */ 58 mrs_s x1, SYS_ID_AA64PFR1_EL1 59 ubfx x1, x1, #ID_AA64PFR1_EL1_GCS_SHIFT, #4 60 cbz x1, .Lset_hcrx_\@ 61 orr x0, x0, #HCRX_EL2_GCSEn 62 63 .Lset_hcrx_\@: 64 msr_s SYS_HCRX_EL2, x0 65 .Lskip_hcrx_\@: 66 .endm 67 68 /* Check if running in host at EL2 mode, i.e., (h)VHE. Jump to fail if not. */ 69 .macro __check_hvhe fail, tmp 70 mrs \tmp, hcr_el2 71 and \tmp, \tmp, #HCR_E2H 72 cbz \tmp, \fail 73 .endm 74 75 /* 76 * Allow Non-secure EL1 and EL0 to access physical timer and counter. 77 * This is not necessary for VHE, since the host kernel runs in EL2, 78 * and EL0 accesses are configured in the later stage of boot process. 79 * Note that when HCR_EL2.E2H == 1, CNTHCTL_EL2 has the same bit layout 80 * as CNTKCTL_EL1, and CNTKCTL_EL1 accessing instructions are redefined 81 * to access CNTHCTL_EL2. This allows the kernel designed to run at EL1 82 * to transparently mess with the EL0 bits via CNTKCTL_EL1 access in 83 * EL2. 84 */ 85 .macro __init_el2_timers 86 mov x0, #3 // Enable EL1 physical timers 87 __check_hvhe .LnVHE_\@, x1 88 lsl x0, x0, #10 89 .LnVHE_\@: 90 msr cnthctl_el2, x0 91 msr cntvoff_el2, xzr // Clear virtual offset 92 .endm 93 94 .macro __init_el2_debug 95 mrs x1, id_aa64dfr0_el1 96 ubfx x0, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4 97 cmp x0, #ID_AA64DFR0_EL1_PMUVer_NI 98 ccmp x0, #ID_AA64DFR0_EL1_PMUVer_IMP_DEF, #4, ne 99 b.eq .Lskip_pmu_\@ // Skip if no PMU present or IMP_DEF 100 mrs x0, pmcr_el0 // Disable debug access traps 101 ubfx x0, x0, #11, #5 // to EL2 and allow access to 102 .Lskip_pmu_\@: 103 csel x2, xzr, x0, eq // all PMU counters from EL1 104 105 /* Statistical profiling */ 106 ubfx x0, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4 107 cbz x0, .Lskip_spe_\@ // Skip if SPE not present 108 109 mrs_s x0, SYS_PMBIDR_EL1 // If SPE available at EL2, 110 and x0, x0, #(1 << PMBIDR_EL1_P_SHIFT) 111 cbnz x0, .Lskip_spe_el2_\@ // then permit sampling of physical 112 mov x0, #(1 << PMSCR_EL2_PCT_SHIFT | \ 113 1 << PMSCR_EL2_PA_SHIFT) 114 msr_s SYS_PMSCR_EL2, x0 // addresses and physical counter 115 .Lskip_spe_el2_\@: 116 mov x0, #MDCR_EL2_E2PB_MASK 117 orr x2, x2, x0 // If we don't have VHE, then 118 // use EL1&0 translation. 119 120 .Lskip_spe_\@: 121 /* Trace buffer */ 122 ubfx x0, x1, #ID_AA64DFR0_EL1_TraceBuffer_SHIFT, #4 123 cbz x0, .Lskip_trace_\@ // Skip if TraceBuffer is not present 124 125 mrs_s x0, SYS_TRBIDR_EL1 126 and x0, x0, TRBIDR_EL1_P 127 cbnz x0, .Lskip_trace_\@ // If TRBE is available at EL2 128 129 mov x0, #MDCR_EL2_E2TB_MASK 130 orr x2, x2, x0 // allow the EL1&0 translation 131 // to own it. 132 133 .Lskip_trace_\@: 134 msr mdcr_el2, x2 // Configure debug traps 135 .endm 136 137 /* LORegions */ 138 .macro __init_el2_lor 139 mrs x1, id_aa64mmfr1_el1 140 ubfx x0, x1, #ID_AA64MMFR1_EL1_LO_SHIFT, 4 141 cbz x0, .Lskip_lor_\@ 142 msr_s SYS_LORC_EL1, xzr 143 .Lskip_lor_\@: 144 .endm 145 146 /* Stage-2 translation */ 147 .macro __init_el2_stage2 148 msr vttbr_el2, xzr 149 .endm 150 151 /* GICv3 system register access */ 152 .macro __init_el2_gicv3 153 mrs x0, id_aa64pfr0_el1 154 ubfx x0, x0, #ID_AA64PFR0_EL1_GIC_SHIFT, #4 155 cbz x0, .Lskip_gicv3_\@ 156 157 mrs_s x0, SYS_ICC_SRE_EL2 158 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1 159 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1 160 msr_s SYS_ICC_SRE_EL2, x0 161 isb // Make sure SRE is now set 162 mrs_s x0, SYS_ICC_SRE_EL2 // Read SRE back, 163 tbz x0, #0, .Lskip_gicv3_\@ // and check that it sticks 164 msr_s SYS_ICH_HCR_EL2, xzr // Reset ICH_HCR_EL2 to defaults 165 .Lskip_gicv3_\@: 166 .endm 167 168 /* GICv5 system register access */ 169 .macro __init_el2_gicv5 170 mrs_s x0, SYS_ID_AA64PFR2_EL1 171 ubfx x0, x0, #ID_AA64PFR2_EL1_GCIE_SHIFT, #4 172 cbz x0, .Lskip_gicv5_\@ 173 174 mov x0, #(ICH_HFGITR_EL2_GICRCDNMIA | \ 175 ICH_HFGITR_EL2_GICRCDIA | \ 176 ICH_HFGITR_EL2_GICCDDI | \ 177 ICH_HFGITR_EL2_GICCDEOI | \ 178 ICH_HFGITR_EL2_GICCDHM | \ 179 ICH_HFGITR_EL2_GICCDRCFG | \ 180 ICH_HFGITR_EL2_GICCDPEND | \ 181 ICH_HFGITR_EL2_GICCDAFF | \ 182 ICH_HFGITR_EL2_GICCDPRI | \ 183 ICH_HFGITR_EL2_GICCDDIS | \ 184 ICH_HFGITR_EL2_GICCDEN) 185 msr_s SYS_ICH_HFGITR_EL2, x0 // Disable instruction traps 186 mov_q x0, (ICH_HFGRTR_EL2_ICC_PPI_ACTIVERn_EL1 | \ 187 ICH_HFGRTR_EL2_ICC_PPI_PRIORITYRn_EL1 | \ 188 ICH_HFGRTR_EL2_ICC_PPI_PENDRn_EL1 | \ 189 ICH_HFGRTR_EL2_ICC_PPI_ENABLERn_EL1 | \ 190 ICH_HFGRTR_EL2_ICC_PPI_HMRn_EL1 | \ 191 ICH_HFGRTR_EL2_ICC_IAFFIDR_EL1 | \ 192 ICH_HFGRTR_EL2_ICC_ICSR_EL1 | \ 193 ICH_HFGRTR_EL2_ICC_PCR_EL1 | \ 194 ICH_HFGRTR_EL2_ICC_HPPIR_EL1 | \ 195 ICH_HFGRTR_EL2_ICC_HAPR_EL1 | \ 196 ICH_HFGRTR_EL2_ICC_CR0_EL1 | \ 197 ICH_HFGRTR_EL2_ICC_IDRn_EL1 | \ 198 ICH_HFGRTR_EL2_ICC_APR_EL1) 199 msr_s SYS_ICH_HFGRTR_EL2, x0 // Disable reg read traps 200 mov_q x0, (ICH_HFGWTR_EL2_ICC_PPI_ACTIVERn_EL1 | \ 201 ICH_HFGWTR_EL2_ICC_PPI_PRIORITYRn_EL1 | \ 202 ICH_HFGWTR_EL2_ICC_PPI_PENDRn_EL1 | \ 203 ICH_HFGWTR_EL2_ICC_PPI_ENABLERn_EL1 | \ 204 ICH_HFGWTR_EL2_ICC_ICSR_EL1 | \ 205 ICH_HFGWTR_EL2_ICC_PCR_EL1 | \ 206 ICH_HFGWTR_EL2_ICC_CR0_EL1 | \ 207 ICH_HFGWTR_EL2_ICC_APR_EL1) 208 msr_s SYS_ICH_HFGWTR_EL2, x0 // Disable reg write traps 209 .Lskip_gicv5_\@: 210 .endm 211 212 .macro __init_el2_hstr 213 msr hstr_el2, xzr // Disable CP15 traps to EL2 214 .endm 215 216 /* Virtual CPU ID registers */ 217 .macro __init_el2_nvhe_idregs 218 mrs x0, midr_el1 219 mrs x1, mpidr_el1 220 msr vpidr_el2, x0 221 msr vmpidr_el2, x1 222 .endm 223 224 /* Coprocessor traps */ 225 .macro __init_el2_cptr 226 __check_hvhe .LnVHE_\@, x1 227 mov x0, #CPACR_EL1_FPEN 228 msr cpacr_el1, x0 229 b .Lskip_set_cptr_\@ 230 .LnVHE_\@: 231 mov x0, #0x33ff 232 msr cptr_el2, x0 // Disable copro. traps to EL2 233 .Lskip_set_cptr_\@: 234 .endm 235 236 /* 237 * Configure BRBE to permit recording cycle counts and branch mispredicts. 238 * 239 * At any EL, to record cycle counts BRBE requires that both BRBCR_EL2.CC=1 and 240 * BRBCR_EL1.CC=1. 241 * 242 * At any EL, to record branch mispredicts BRBE requires that both 243 * BRBCR_EL2.MPRED=1 and BRBCR_EL1.MPRED=1. 244 * 245 * Set {CC,MPRED} in BRBCR_EL2 in case nVHE mode is used and we are 246 * executing in EL1. 247 */ 248 .macro __init_el2_brbe 249 mrs x1, id_aa64dfr0_el1 250 ubfx x1, x1, #ID_AA64DFR0_EL1_BRBE_SHIFT, #4 251 cbz x1, .Lskip_brbe_\@ 252 253 mov_q x0, BRBCR_ELx_CC | BRBCR_ELx_MPRED 254 msr_s SYS_BRBCR_EL2, x0 255 .Lskip_brbe_\@: 256 .endm 257 258 /* Disable any fine grained traps */ 259 .macro __init_el2_fgt 260 mrs x1, id_aa64mmfr0_el1 261 ubfx x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4 262 cbz x1, .Lskip_fgt_\@ 263 264 mov x0, xzr 265 mov x2, xzr 266 mrs x1, id_aa64dfr0_el1 267 ubfx x1, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4 268 cmp x1, #3 269 b.lt .Lskip_spe_fgt_\@ 270 /* Disable PMSNEVFR_EL1 read and write traps */ 271 orr x0, x0, #HDFGRTR_EL2_nPMSNEVFR_EL1_MASK 272 orr x2, x2, #HDFGWTR_EL2_nPMSNEVFR_EL1_MASK 273 274 .Lskip_spe_fgt_\@: 275 mrs x1, id_aa64dfr0_el1 276 ubfx x1, x1, #ID_AA64DFR0_EL1_BRBE_SHIFT, #4 277 cbz x1, .Lskip_brbe_fgt_\@ 278 279 /* 280 * Disable read traps for the following registers 281 * 282 * [BRBSRC|BRBTGT|RBINF]_EL1 283 * [BRBSRCINJ|BRBTGTINJ|BRBINFINJ|BRBTS]_EL1 284 */ 285 orr x0, x0, #HDFGRTR_EL2_nBRBDATA_MASK 286 287 /* 288 * Disable write traps for the following registers 289 * 290 * [BRBSRCINJ|BRBTGTINJ|BRBINFINJ|BRBTS]_EL1 291 */ 292 orr x2, x2, #HDFGWTR_EL2_nBRBDATA_MASK 293 294 /* Disable read and write traps for [BRBCR|BRBFCR]_EL1 */ 295 orr x0, x0, #HDFGRTR_EL2_nBRBCTL_MASK 296 orr x2, x2, #HDFGWTR_EL2_nBRBCTL_MASK 297 298 /* Disable read traps for BRBIDR_EL1 */ 299 orr x0, x0, #HDFGRTR_EL2_nBRBIDR_MASK 300 301 .Lskip_brbe_fgt_\@: 302 303 .Lset_debug_fgt_\@: 304 msr_s SYS_HDFGRTR_EL2, x0 305 msr_s SYS_HDFGWTR_EL2, x2 306 307 mov x0, xzr 308 mov x2, xzr 309 310 mrs x1, id_aa64dfr0_el1 311 ubfx x1, x1, #ID_AA64DFR0_EL1_BRBE_SHIFT, #4 312 cbz x1, .Lskip_brbe_insn_fgt_\@ 313 314 /* Disable traps for BRBIALL instruction */ 315 orr x2, x2, #HFGITR_EL2_nBRBIALL_MASK 316 317 /* Disable traps for BRBINJ instruction */ 318 orr x2, x2, #HFGITR_EL2_nBRBINJ_MASK 319 320 .Lskip_brbe_insn_fgt_\@: 321 mrs x1, id_aa64pfr1_el1 322 ubfx x1, x1, #ID_AA64PFR1_EL1_SME_SHIFT, #4 323 cbz x1, .Lskip_sme_fgt_\@ 324 325 /* Disable nVHE traps of TPIDR2 and SMPRI */ 326 orr x0, x0, #HFGRTR_EL2_nSMPRI_EL1_MASK 327 orr x0, x0, #HFGRTR_EL2_nTPIDR2_EL0_MASK 328 329 .Lskip_sme_fgt_\@: 330 mrs_s x1, SYS_ID_AA64MMFR3_EL1 331 ubfx x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4 332 cbz x1, .Lskip_pie_fgt_\@ 333 334 /* Disable trapping of PIR_EL1 / PIRE0_EL1 */ 335 orr x0, x0, #HFGRTR_EL2_nPIR_EL1 336 orr x0, x0, #HFGRTR_EL2_nPIRE0_EL1 337 338 .Lskip_pie_fgt_\@: 339 mrs_s x1, SYS_ID_AA64MMFR3_EL1 340 ubfx x1, x1, #ID_AA64MMFR3_EL1_S1POE_SHIFT, #4 341 cbz x1, .Lskip_poe_fgt_\@ 342 343 /* Disable trapping of POR_EL0 */ 344 orr x0, x0, #HFGRTR_EL2_nPOR_EL0 345 346 .Lskip_poe_fgt_\@: 347 /* GCS depends on PIE so we don't check it if PIE is absent */ 348 mrs_s x1, SYS_ID_AA64PFR1_EL1 349 ubfx x1, x1, #ID_AA64PFR1_EL1_GCS_SHIFT, #4 350 cbz x1, .Lskip_gce_fgt_\@ 351 352 /* Disable traps of access to GCS registers at EL0 and EL1 */ 353 orr x0, x0, #HFGRTR_EL2_nGCS_EL1_MASK 354 orr x0, x0, #HFGRTR_EL2_nGCS_EL0_MASK 355 356 .Lskip_gce_fgt_\@: 357 358 .Lset_fgt_\@: 359 msr_s SYS_HFGRTR_EL2, x0 360 msr_s SYS_HFGWTR_EL2, x0 361 msr_s SYS_HFGITR_EL2, x2 362 363 mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU 364 ubfx x1, x1, #ID_AA64PFR0_EL1_AMU_SHIFT, #4 365 cbz x1, .Lskip_amu_fgt_\@ 366 367 msr_s SYS_HAFGRTR_EL2, xzr 368 369 .Lskip_amu_fgt_\@: 370 371 .Lskip_fgt_\@: 372 .endm 373 374 .macro __init_el2_fgt2 375 mrs x1, id_aa64mmfr0_el1 376 ubfx x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4 377 cmp x1, #ID_AA64MMFR0_EL1_FGT_FGT2 378 b.lt .Lskip_fgt2_\@ 379 380 mov x0, xzr 381 mrs x1, id_aa64dfr0_el1 382 ubfx x1, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4 383 cmp x1, #ID_AA64DFR0_EL1_PMUVer_V3P9 384 b.lt .Lskip_pmuv3p9_\@ 385 386 orr x0, x0, #HDFGRTR2_EL2_nPMICNTR_EL0 387 orr x0, x0, #HDFGRTR2_EL2_nPMICFILTR_EL0 388 orr x0, x0, #HDFGRTR2_EL2_nPMUACR_EL1 389 .Lskip_pmuv3p9_\@: 390 msr_s SYS_HDFGRTR2_EL2, x0 391 msr_s SYS_HDFGWTR2_EL2, x0 392 msr_s SYS_HFGRTR2_EL2, xzr 393 msr_s SYS_HFGWTR2_EL2, xzr 394 msr_s SYS_HFGITR2_EL2, xzr 395 .Lskip_fgt2_\@: 396 .endm 397 398 /** 399 * Initialize EL2 registers to sane values. This should be called early on all 400 * cores that were booted in EL2. Note that everything gets initialised as 401 * if VHE was not available. The kernel context will be upgraded to VHE 402 * if possible later on in the boot process 403 * 404 * Regs: x0, x1 and x2 are clobbered. 405 */ 406 .macro init_el2_state 407 __init_el2_sctlr 408 __init_el2_hcrx 409 __init_el2_timers 410 __init_el2_debug 411 __init_el2_brbe 412 __init_el2_lor 413 __init_el2_stage2 414 __init_el2_gicv3 415 __init_el2_gicv5 416 __init_el2_hstr 417 __init_el2_nvhe_idregs 418 __init_el2_cptr 419 __init_el2_fgt 420 __init_el2_fgt2 421 .endm 422 423 #ifndef __KVM_NVHE_HYPERVISOR__ 424 // This will clobber tmp1 and tmp2, and expect tmp1 to contain 425 // the id register value as read from the HW 426 .macro __check_override idreg, fld, width, pass, fail, tmp1, tmp2 427 ubfx \tmp1, \tmp1, #\fld, #\width 428 cbz \tmp1, \fail 429 430 adr_l \tmp1, \idreg\()_override 431 ldr \tmp2, [\tmp1, FTR_OVR_VAL_OFFSET] 432 ldr \tmp1, [\tmp1, FTR_OVR_MASK_OFFSET] 433 ubfx \tmp2, \tmp2, #\fld, #\width 434 ubfx \tmp1, \tmp1, #\fld, #\width 435 cmp \tmp1, xzr 436 and \tmp2, \tmp2, \tmp1 437 csinv \tmp2, \tmp2, xzr, ne 438 cbnz \tmp2, \pass 439 b \fail 440 .endm 441 442 // This will clobber tmp1 and tmp2 443 .macro check_override idreg, fld, pass, fail, tmp1, tmp2 444 mrs \tmp1, \idreg\()_el1 445 __check_override \idreg \fld 4 \pass \fail \tmp1 \tmp2 446 .endm 447 #else 448 // This will clobber tmp 449 .macro __check_override idreg, fld, width, pass, fail, tmp, ignore 450 ldr_l \tmp, \idreg\()_el1_sys_val 451 ubfx \tmp, \tmp, #\fld, #\width 452 cbnz \tmp, \pass 453 b \fail 454 .endm 455 456 .macro check_override idreg, fld, pass, fail, tmp, ignore 457 __check_override \idreg \fld 4 \pass \fail \tmp \ignore 458 .endm 459 #endif 460 461 .macro finalise_el2_state 462 check_override id_aa64pfr0, ID_AA64PFR0_EL1_MPAM_SHIFT, .Linit_mpam_\@, .Lskip_mpam_\@, x1, x2 463 464 .Linit_mpam_\@: 465 msr_s SYS_MPAM2_EL2, xzr // use the default partition 466 // and disable lower traps 467 mrs_s x0, SYS_MPAMIDR_EL1 468 tbz x0, #MPAMIDR_EL1_HAS_HCR_SHIFT, .Lskip_mpam_\@ // skip if no MPAMHCR reg 469 msr_s SYS_MPAMHCR_EL2, xzr // clear TRAP_MPAMIDR_EL1 -> EL2 470 471 .Lskip_mpam_\@: 472 check_override id_aa64pfr1, ID_AA64PFR1_EL1_GCS_SHIFT, .Linit_gcs_\@, .Lskip_gcs_\@, x1, x2 473 474 .Linit_gcs_\@: 475 msr_s SYS_GCSCR_EL1, xzr 476 msr_s SYS_GCSCRE0_EL1, xzr 477 478 .Lskip_gcs_\@: 479 check_override id_aa64pfr0, ID_AA64PFR0_EL1_SVE_SHIFT, .Linit_sve_\@, .Lskip_sve_\@, x1, x2 480 481 .Linit_sve_\@: /* SVE register access */ 482 __check_hvhe .Lcptr_nvhe_\@, x1 483 484 // (h)VHE case 485 mrs x0, cpacr_el1 // Disable SVE traps 486 orr x0, x0, #CPACR_EL1_ZEN 487 msr cpacr_el1, x0 488 b .Lskip_set_cptr_\@ 489 490 .Lcptr_nvhe_\@: // nVHE case 491 mrs x0, cptr_el2 // Disable SVE traps 492 bic x0, x0, #CPTR_EL2_TZ 493 msr cptr_el2, x0 494 .Lskip_set_cptr_\@: 495 isb 496 mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector 497 msr_s SYS_ZCR_EL2, x1 // length for EL1. 498 499 .Lskip_sve_\@: 500 check_override id_aa64pfr1, ID_AA64PFR1_EL1_SME_SHIFT, .Linit_sme_\@, .Lskip_sme_\@, x1, x2 501 502 .Linit_sme_\@: /* SME register access and priority mapping */ 503 __check_hvhe .Lcptr_nvhe_sme_\@, x1 504 505 // (h)VHE case 506 mrs x0, cpacr_el1 // Disable SME traps 507 orr x0, x0, #CPACR_EL1_SMEN 508 msr cpacr_el1, x0 509 b .Lskip_set_cptr_sme_\@ 510 511 .Lcptr_nvhe_sme_\@: // nVHE case 512 mrs x0, cptr_el2 // Disable SME traps 513 bic x0, x0, #CPTR_EL2_TSM 514 msr cptr_el2, x0 515 .Lskip_set_cptr_sme_\@: 516 isb 517 518 mrs x1, sctlr_el2 519 orr x1, x1, #SCTLR_ELx_ENTP2 // Disable TPIDR2 traps 520 msr sctlr_el2, x1 521 isb 522 523 mov x0, #0 // SMCR controls 524 525 // Full FP in SM? 526 mrs_s x1, SYS_ID_AA64SMFR0_EL1 527 __check_override id_aa64smfr0, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, .Linit_sme_fa64_\@, .Lskip_sme_fa64_\@, x1, x2 528 529 .Linit_sme_fa64_\@: 530 orr x0, x0, SMCR_ELx_FA64_MASK 531 .Lskip_sme_fa64_\@: 532 533 // ZT0 available? 534 mrs_s x1, SYS_ID_AA64SMFR0_EL1 535 __check_override id_aa64smfr0, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, .Linit_sme_zt0_\@, .Lskip_sme_zt0_\@, x1, x2 536 .Linit_sme_zt0_\@: 537 orr x0, x0, SMCR_ELx_EZT0_MASK 538 .Lskip_sme_zt0_\@: 539 540 orr x0, x0, #SMCR_ELx_LEN_MASK // Enable full SME vector 541 msr_s SYS_SMCR_EL2, x0 // length for EL1. 542 543 mrs_s x1, SYS_SMIDR_EL1 // Priority mapping supported? 544 ubfx x1, x1, #SMIDR_EL1_SMPS_SHIFT, #1 545 cbz x1, .Lskip_sme_\@ 546 547 msr_s SYS_SMPRIMAP_EL2, xzr // Make all priorities equal 548 .Lskip_sme_\@: 549 .endm 550 551 #endif /* __ARM_KVM_INIT_H__ */ 552