1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #ifndef __ARM_KVM_INIT_H__ 8 #define __ARM_KVM_INIT_H__ 9 10 #ifndef __ASSEMBLY__ 11 #error Assembly-only header 12 #endif 13 14 #include <asm/kvm_arm.h> 15 #include <asm/ptrace.h> 16 #include <asm/sysreg.h> 17 #include <linux/irqchip/arm-gic-v3.h> 18 19 .macro init_el2_hcr val 20 mov_q x0, \val 21 22 /* 23 * Compliant CPUs advertise their VHE-onlyness with 24 * ID_AA64MMFR4_EL1.E2H0 < 0. On such CPUs HCR_EL2.E2H is RES1, but it 25 * can reset into an UNKNOWN state and might not read as 1 until it has 26 * been initialized explicitly. 27 * 28 * Fruity CPUs seem to have HCR_EL2.E2H set to RAO/WI, but 29 * don't advertise it (they predate this relaxation). 30 * 31 * Initalize HCR_EL2.E2H so that later code can rely upon HCR_EL2.E2H 32 * indicating whether the CPU is running in E2H mode. 33 */ 34 mrs_s x1, SYS_ID_AA64MMFR4_EL1 35 sbfx x1, x1, #ID_AA64MMFR4_EL1_E2H0_SHIFT, #ID_AA64MMFR4_EL1_E2H0_WIDTH 36 cmp x1, #0 37 b.ge .LnVHE_\@ 38 39 orr x0, x0, #HCR_E2H 40 .LnVHE_\@: 41 msr_hcr_el2 x0 42 isb 43 .endm 44 45 .macro __init_el2_sctlr 46 mov_q x0, INIT_SCTLR_EL2_MMU_OFF 47 msr sctlr_el2, x0 48 isb 49 .endm 50 51 .macro __init_el2_hcrx 52 mrs x0, id_aa64mmfr1_el1 53 ubfx x0, x0, #ID_AA64MMFR1_EL1_HCX_SHIFT, #4 54 cbz x0, .Lskip_hcrx_\@ 55 mov_q x0, (HCRX_EL2_MSCEn | HCRX_EL2_TCR2En | HCRX_EL2_EnFPM) 56 57 /* Enable GCS if supported */ 58 mrs_s x1, SYS_ID_AA64PFR1_EL1 59 ubfx x1, x1, #ID_AA64PFR1_EL1_GCS_SHIFT, #4 60 cbz x1, .Lset_hcrx_\@ 61 orr x0, x0, #HCRX_EL2_GCSEn 62 63 .Lset_hcrx_\@: 64 msr_s SYS_HCRX_EL2, x0 65 .Lskip_hcrx_\@: 66 .endm 67 68 /* Check if running in host at EL2 mode, i.e., (h)VHE. Jump to fail if not. */ 69 .macro __check_hvhe fail, tmp 70 mrs \tmp, hcr_el2 71 and \tmp, \tmp, #HCR_E2H 72 cbz \tmp, \fail 73 .endm 74 75 /* 76 * Allow Non-secure EL1 and EL0 to access physical timer and counter. 77 * This is not necessary for VHE, since the host kernel runs in EL2, 78 * and EL0 accesses are configured in the later stage of boot process. 79 * Note that when HCR_EL2.E2H == 1, CNTHCTL_EL2 has the same bit layout 80 * as CNTKCTL_EL1, and CNTKCTL_EL1 accessing instructions are redefined 81 * to access CNTHCTL_EL2. This allows the kernel designed to run at EL1 82 * to transparently mess with the EL0 bits via CNTKCTL_EL1 access in 83 * EL2. 84 */ 85 .macro __init_el2_timers 86 mov x0, #3 // Enable EL1 physical timers 87 __check_hvhe .LnVHE_\@, x1 88 lsl x0, x0, #10 89 .LnVHE_\@: 90 msr cnthctl_el2, x0 91 msr cntvoff_el2, xzr // Clear virtual offset 92 .endm 93 94 .macro __init_el2_debug 95 mrs x1, id_aa64dfr0_el1 96 ubfx x0, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4 97 cmp x0, #ID_AA64DFR0_EL1_PMUVer_NI 98 ccmp x0, #ID_AA64DFR0_EL1_PMUVer_IMP_DEF, #4, ne 99 b.eq .Lskip_pmu_\@ // Skip if no PMU present or IMP_DEF 100 mrs x0, pmcr_el0 // Disable debug access traps 101 ubfx x0, x0, #11, #5 // to EL2 and allow access to 102 .Lskip_pmu_\@: 103 csel x2, xzr, x0, eq // all PMU counters from EL1 104 105 /* Statistical profiling */ 106 ubfx x0, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4 107 cbz x0, .Lskip_spe_\@ // Skip if SPE not present 108 109 mrs_s x0, SYS_PMBIDR_EL1 // If SPE available at EL2, 110 and x0, x0, #(1 << PMBIDR_EL1_P_SHIFT) 111 cbnz x0, .Lskip_spe_el2_\@ // then permit sampling of physical 112 mov x0, #(1 << PMSCR_EL2_PCT_SHIFT | \ 113 1 << PMSCR_EL2_PA_SHIFT) 114 msr_s SYS_PMSCR_EL2, x0 // addresses and physical counter 115 .Lskip_spe_el2_\@: 116 mov x0, #MDCR_EL2_E2PB_MASK 117 orr x2, x2, x0 // If we don't have VHE, then 118 // use EL1&0 translation. 119 120 .Lskip_spe_\@: 121 /* Trace buffer */ 122 ubfx x0, x1, #ID_AA64DFR0_EL1_TraceBuffer_SHIFT, #4 123 cbz x0, .Lskip_trace_\@ // Skip if TraceBuffer is not present 124 125 mrs_s x0, SYS_TRBIDR_EL1 126 and x0, x0, TRBIDR_EL1_P 127 cbnz x0, .Lskip_trace_\@ // If TRBE is available at EL2 128 129 mov x0, #MDCR_EL2_E2TB_MASK 130 orr x2, x2, x0 // allow the EL1&0 translation 131 // to own it. 132 133 .Lskip_trace_\@: 134 msr mdcr_el2, x2 // Configure debug traps 135 .endm 136 137 /* LORegions */ 138 .macro __init_el2_lor 139 mrs x1, id_aa64mmfr1_el1 140 ubfx x0, x1, #ID_AA64MMFR1_EL1_LO_SHIFT, 4 141 cbz x0, .Lskip_lor_\@ 142 msr_s SYS_LORC_EL1, xzr 143 .Lskip_lor_\@: 144 .endm 145 146 /* Stage-2 translation */ 147 .macro __init_el2_stage2 148 msr vttbr_el2, xzr 149 .endm 150 151 /* GICv3 system register access */ 152 .macro __init_el2_gicv3 153 mrs x0, id_aa64pfr0_el1 154 ubfx x0, x0, #ID_AA64PFR0_EL1_GIC_SHIFT, #4 155 cbz x0, .Lskip_gicv3_\@ 156 157 mrs_s x0, SYS_ICC_SRE_EL2 158 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1 159 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1 160 msr_s SYS_ICC_SRE_EL2, x0 161 isb // Make sure SRE is now set 162 mrs_s x0, SYS_ICC_SRE_EL2 // Read SRE back, 163 tbz x0, #0, .Lskip_gicv3_\@ // and check that it sticks 164 msr_s SYS_ICH_HCR_EL2, xzr // Reset ICH_HCR_EL2 to defaults 165 .Lskip_gicv3_\@: 166 .endm 167 168 .macro __init_el2_hstr 169 msr hstr_el2, xzr // Disable CP15 traps to EL2 170 .endm 171 172 /* Virtual CPU ID registers */ 173 .macro __init_el2_nvhe_idregs 174 mrs x0, midr_el1 175 mrs x1, mpidr_el1 176 msr vpidr_el2, x0 177 msr vmpidr_el2, x1 178 .endm 179 180 /* Coprocessor traps */ 181 .macro __init_el2_cptr 182 __check_hvhe .LnVHE_\@, x1 183 mov x0, #CPACR_EL1_FPEN 184 msr cpacr_el1, x0 185 b .Lskip_set_cptr_\@ 186 .LnVHE_\@: 187 mov x0, #0x33ff 188 msr cptr_el2, x0 // Disable copro. traps to EL2 189 .Lskip_set_cptr_\@: 190 .endm 191 192 /* 193 * Configure BRBE to permit recording cycle counts and branch mispredicts. 194 * 195 * At any EL, to record cycle counts BRBE requires that both BRBCR_EL2.CC=1 and 196 * BRBCR_EL1.CC=1. 197 * 198 * At any EL, to record branch mispredicts BRBE requires that both 199 * BRBCR_EL2.MPRED=1 and BRBCR_EL1.MPRED=1. 200 * 201 * Set {CC,MPRED} in BRBCR_EL2 in case nVHE mode is used and we are 202 * executing in EL1. 203 */ 204 .macro __init_el2_brbe 205 mrs x1, id_aa64dfr0_el1 206 ubfx x1, x1, #ID_AA64DFR0_EL1_BRBE_SHIFT, #4 207 cbz x1, .Lskip_brbe_\@ 208 209 mov_q x0, BRBCR_ELx_CC | BRBCR_ELx_MPRED 210 msr_s SYS_BRBCR_EL2, x0 211 .Lskip_brbe_\@: 212 .endm 213 214 /* Disable any fine grained traps */ 215 .macro __init_el2_fgt 216 mrs x1, id_aa64mmfr0_el1 217 ubfx x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4 218 cbz x1, .Lskip_fgt_\@ 219 220 mov x0, xzr 221 mov x2, xzr 222 mrs x1, id_aa64dfr0_el1 223 ubfx x1, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4 224 cmp x1, #3 225 b.lt .Lskip_spe_fgt_\@ 226 /* Disable PMSNEVFR_EL1 read and write traps */ 227 orr x0, x0, #HDFGRTR_EL2_nPMSNEVFR_EL1_MASK 228 orr x2, x2, #HDFGWTR_EL2_nPMSNEVFR_EL1_MASK 229 230 .Lskip_spe_fgt_\@: 231 mrs x1, id_aa64dfr0_el1 232 ubfx x1, x1, #ID_AA64DFR0_EL1_BRBE_SHIFT, #4 233 cbz x1, .Lskip_brbe_fgt_\@ 234 235 /* 236 * Disable read traps for the following registers 237 * 238 * [BRBSRC|BRBTGT|RBINF]_EL1 239 * [BRBSRCINJ|BRBTGTINJ|BRBINFINJ|BRBTS]_EL1 240 */ 241 orr x0, x0, #HDFGRTR_EL2_nBRBDATA_MASK 242 243 /* 244 * Disable write traps for the following registers 245 * 246 * [BRBSRCINJ|BRBTGTINJ|BRBINFINJ|BRBTS]_EL1 247 */ 248 orr x2, x2, #HDFGWTR_EL2_nBRBDATA_MASK 249 250 /* Disable read and write traps for [BRBCR|BRBFCR]_EL1 */ 251 orr x0, x0, #HDFGRTR_EL2_nBRBCTL_MASK 252 orr x2, x2, #HDFGWTR_EL2_nBRBCTL_MASK 253 254 /* Disable read traps for BRBIDR_EL1 */ 255 orr x0, x0, #HDFGRTR_EL2_nBRBIDR_MASK 256 257 .Lskip_brbe_fgt_\@: 258 259 .Lset_debug_fgt_\@: 260 msr_s SYS_HDFGRTR_EL2, x0 261 msr_s SYS_HDFGWTR_EL2, x2 262 263 mov x0, xzr 264 mov x2, xzr 265 266 mrs x1, id_aa64dfr0_el1 267 ubfx x1, x1, #ID_AA64DFR0_EL1_BRBE_SHIFT, #4 268 cbz x1, .Lskip_brbe_insn_fgt_\@ 269 270 /* Disable traps for BRBIALL instruction */ 271 orr x2, x2, #HFGITR_EL2_nBRBIALL_MASK 272 273 /* Disable traps for BRBINJ instruction */ 274 orr x2, x2, #HFGITR_EL2_nBRBINJ_MASK 275 276 .Lskip_brbe_insn_fgt_\@: 277 mrs x1, id_aa64pfr1_el1 278 ubfx x1, x1, #ID_AA64PFR1_EL1_SME_SHIFT, #4 279 cbz x1, .Lskip_sme_fgt_\@ 280 281 /* Disable nVHE traps of TPIDR2 and SMPRI */ 282 orr x0, x0, #HFGRTR_EL2_nSMPRI_EL1_MASK 283 orr x0, x0, #HFGRTR_EL2_nTPIDR2_EL0_MASK 284 285 .Lskip_sme_fgt_\@: 286 mrs_s x1, SYS_ID_AA64MMFR3_EL1 287 ubfx x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4 288 cbz x1, .Lskip_pie_fgt_\@ 289 290 /* Disable trapping of PIR_EL1 / PIRE0_EL1 */ 291 orr x0, x0, #HFGRTR_EL2_nPIR_EL1 292 orr x0, x0, #HFGRTR_EL2_nPIRE0_EL1 293 294 .Lskip_pie_fgt_\@: 295 mrs_s x1, SYS_ID_AA64MMFR3_EL1 296 ubfx x1, x1, #ID_AA64MMFR3_EL1_S1POE_SHIFT, #4 297 cbz x1, .Lskip_poe_fgt_\@ 298 299 /* Disable trapping of POR_EL0 */ 300 orr x0, x0, #HFGRTR_EL2_nPOR_EL0 301 302 .Lskip_poe_fgt_\@: 303 /* GCS depends on PIE so we don't check it if PIE is absent */ 304 mrs_s x1, SYS_ID_AA64PFR1_EL1 305 ubfx x1, x1, #ID_AA64PFR1_EL1_GCS_SHIFT, #4 306 cbz x1, .Lskip_gce_fgt_\@ 307 308 /* Disable traps of access to GCS registers at EL0 and EL1 */ 309 orr x0, x0, #HFGRTR_EL2_nGCS_EL1_MASK 310 orr x0, x0, #HFGRTR_EL2_nGCS_EL0_MASK 311 312 .Lskip_gce_fgt_\@: 313 314 .Lset_fgt_\@: 315 msr_s SYS_HFGRTR_EL2, x0 316 msr_s SYS_HFGWTR_EL2, x0 317 msr_s SYS_HFGITR_EL2, x2 318 319 mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU 320 ubfx x1, x1, #ID_AA64PFR0_EL1_AMU_SHIFT, #4 321 cbz x1, .Lskip_amu_fgt_\@ 322 323 msr_s SYS_HAFGRTR_EL2, xzr 324 325 .Lskip_amu_fgt_\@: 326 327 .Lskip_fgt_\@: 328 .endm 329 330 .macro __init_el2_fgt2 331 mrs x1, id_aa64mmfr0_el1 332 ubfx x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4 333 cmp x1, #ID_AA64MMFR0_EL1_FGT_FGT2 334 b.lt .Lskip_fgt2_\@ 335 336 mov x0, xzr 337 mrs x1, id_aa64dfr0_el1 338 ubfx x1, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4 339 cmp x1, #ID_AA64DFR0_EL1_PMUVer_V3P9 340 b.lt .Lskip_pmuv3p9_\@ 341 342 orr x0, x0, #HDFGRTR2_EL2_nPMICNTR_EL0 343 orr x0, x0, #HDFGRTR2_EL2_nPMICFILTR_EL0 344 orr x0, x0, #HDFGRTR2_EL2_nPMUACR_EL1 345 .Lskip_pmuv3p9_\@: 346 msr_s SYS_HDFGRTR2_EL2, x0 347 msr_s SYS_HDFGWTR2_EL2, x0 348 msr_s SYS_HFGRTR2_EL2, xzr 349 msr_s SYS_HFGWTR2_EL2, xzr 350 msr_s SYS_HFGITR2_EL2, xzr 351 .Lskip_fgt2_\@: 352 .endm 353 354 .macro __init_el2_gcs 355 mrs_s x1, SYS_ID_AA64PFR1_EL1 356 ubfx x1, x1, #ID_AA64PFR1_EL1_GCS_SHIFT, #4 357 cbz x1, .Lskip_gcs_\@ 358 359 /* Ensure GCS is not enabled when we start trying to do BLs */ 360 msr_s SYS_GCSCR_EL1, xzr 361 msr_s SYS_GCSCRE0_EL1, xzr 362 .Lskip_gcs_\@: 363 .endm 364 365 /** 366 * Initialize EL2 registers to sane values. This should be called early on all 367 * cores that were booted in EL2. Note that everything gets initialised as 368 * if VHE was not available. The kernel context will be upgraded to VHE 369 * if possible later on in the boot process 370 * 371 * Regs: x0, x1 and x2 are clobbered. 372 */ 373 .macro init_el2_state 374 __init_el2_sctlr 375 __init_el2_hcrx 376 __init_el2_timers 377 __init_el2_debug 378 __init_el2_brbe 379 __init_el2_lor 380 __init_el2_stage2 381 __init_el2_gicv3 382 __init_el2_hstr 383 __init_el2_nvhe_idregs 384 __init_el2_cptr 385 __init_el2_fgt 386 __init_el2_fgt2 387 __init_el2_gcs 388 .endm 389 390 #ifndef __KVM_NVHE_HYPERVISOR__ 391 // This will clobber tmp1 and tmp2, and expect tmp1 to contain 392 // the id register value as read from the HW 393 .macro __check_override idreg, fld, width, pass, fail, tmp1, tmp2 394 ubfx \tmp1, \tmp1, #\fld, #\width 395 cbz \tmp1, \fail 396 397 adr_l \tmp1, \idreg\()_override 398 ldr \tmp2, [\tmp1, FTR_OVR_VAL_OFFSET] 399 ldr \tmp1, [\tmp1, FTR_OVR_MASK_OFFSET] 400 ubfx \tmp2, \tmp2, #\fld, #\width 401 ubfx \tmp1, \tmp1, #\fld, #\width 402 cmp \tmp1, xzr 403 and \tmp2, \tmp2, \tmp1 404 csinv \tmp2, \tmp2, xzr, ne 405 cbnz \tmp2, \pass 406 b \fail 407 .endm 408 409 // This will clobber tmp1 and tmp2 410 .macro check_override idreg, fld, pass, fail, tmp1, tmp2 411 mrs \tmp1, \idreg\()_el1 412 __check_override \idreg \fld 4 \pass \fail \tmp1 \tmp2 413 .endm 414 #else 415 // This will clobber tmp 416 .macro __check_override idreg, fld, width, pass, fail, tmp, ignore 417 ldr_l \tmp, \idreg\()_el1_sys_val 418 ubfx \tmp, \tmp, #\fld, #\width 419 cbnz \tmp, \pass 420 b \fail 421 .endm 422 423 .macro check_override idreg, fld, pass, fail, tmp, ignore 424 __check_override \idreg \fld 4 \pass \fail \tmp \ignore 425 .endm 426 #endif 427 428 .macro finalise_el2_state 429 check_override id_aa64pfr0, ID_AA64PFR0_EL1_MPAM_SHIFT, .Linit_mpam_\@, .Lskip_mpam_\@, x1, x2 430 431 .Linit_mpam_\@: 432 msr_s SYS_MPAM2_EL2, xzr // use the default partition 433 // and disable lower traps 434 mrs_s x0, SYS_MPAMIDR_EL1 435 tbz x0, #MPAMIDR_EL1_HAS_HCR_SHIFT, .Lskip_mpam_\@ // skip if no MPAMHCR reg 436 msr_s SYS_MPAMHCR_EL2, xzr // clear TRAP_MPAMIDR_EL1 -> EL2 437 438 .Lskip_mpam_\@: 439 check_override id_aa64pfr0, ID_AA64PFR0_EL1_SVE_SHIFT, .Linit_sve_\@, .Lskip_sve_\@, x1, x2 440 441 .Linit_sve_\@: /* SVE register access */ 442 __check_hvhe .Lcptr_nvhe_\@, x1 443 444 // (h)VHE case 445 mrs x0, cpacr_el1 // Disable SVE traps 446 orr x0, x0, #CPACR_EL1_ZEN 447 msr cpacr_el1, x0 448 b .Lskip_set_cptr_\@ 449 450 .Lcptr_nvhe_\@: // nVHE case 451 mrs x0, cptr_el2 // Disable SVE traps 452 bic x0, x0, #CPTR_EL2_TZ 453 msr cptr_el2, x0 454 .Lskip_set_cptr_\@: 455 isb 456 mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector 457 msr_s SYS_ZCR_EL2, x1 // length for EL1. 458 459 .Lskip_sve_\@: 460 check_override id_aa64pfr1, ID_AA64PFR1_EL1_SME_SHIFT, .Linit_sme_\@, .Lskip_sme_\@, x1, x2 461 462 .Linit_sme_\@: /* SME register access and priority mapping */ 463 __check_hvhe .Lcptr_nvhe_sme_\@, x1 464 465 // (h)VHE case 466 mrs x0, cpacr_el1 // Disable SME traps 467 orr x0, x0, #CPACR_EL1_SMEN 468 msr cpacr_el1, x0 469 b .Lskip_set_cptr_sme_\@ 470 471 .Lcptr_nvhe_sme_\@: // nVHE case 472 mrs x0, cptr_el2 // Disable SME traps 473 bic x0, x0, #CPTR_EL2_TSM 474 msr cptr_el2, x0 475 .Lskip_set_cptr_sme_\@: 476 isb 477 478 mrs x1, sctlr_el2 479 orr x1, x1, #SCTLR_ELx_ENTP2 // Disable TPIDR2 traps 480 msr sctlr_el2, x1 481 isb 482 483 mov x0, #0 // SMCR controls 484 485 // Full FP in SM? 486 mrs_s x1, SYS_ID_AA64SMFR0_EL1 487 __check_override id_aa64smfr0, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, .Linit_sme_fa64_\@, .Lskip_sme_fa64_\@, x1, x2 488 489 .Linit_sme_fa64_\@: 490 orr x0, x0, SMCR_ELx_FA64_MASK 491 .Lskip_sme_fa64_\@: 492 493 // ZT0 available? 494 mrs_s x1, SYS_ID_AA64SMFR0_EL1 495 __check_override id_aa64smfr0, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, .Linit_sme_zt0_\@, .Lskip_sme_zt0_\@, x1, x2 496 .Linit_sme_zt0_\@: 497 orr x0, x0, SMCR_ELx_EZT0_MASK 498 .Lskip_sme_zt0_\@: 499 500 orr x0, x0, #SMCR_ELx_LEN_MASK // Enable full SME vector 501 msr_s SYS_SMCR_EL2, x0 // length for EL1. 502 503 mrs_s x1, SYS_SMIDR_EL1 // Priority mapping supported? 504 ubfx x1, x1, #SMIDR_EL1_SMPS_SHIFT, #1 505 cbz x1, .Lskip_sme_\@ 506 507 msr_s SYS_SMPRIMAP_EL2, xzr // Make all priorities equal 508 .Lskip_sme_\@: 509 .endm 510 511 #endif /* __ARM_KVM_INIT_H__ */ 512