1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S 4 * 5 * Copyright (C) 1996-2000 Russell King 6 * Copyright (C) 2012 ARM Ltd. 7 */ 8 #ifndef __ASSEMBLER__ 9 #error "Only include this from assembly code" 10 #endif 11 12 #ifndef __ASM_ASSEMBLER_H 13 #define __ASM_ASSEMBLER_H 14 15 #include <linux/export.h> 16 17 #include <asm/alternative.h> 18 #include <asm/asm-bug.h> 19 #include <asm/asm-extable.h> 20 #include <asm/asm-offsets.h> 21 #include <asm/cpufeature.h> 22 #include <asm/cputype.h> 23 #include <asm/debug-monitors.h> 24 #include <asm/page.h> 25 #include <asm/pgtable-hwdef.h> 26 #include <asm/ptrace.h> 27 #include <asm/thread_info.h> 28 29 /* 30 * Provide a wxN alias for each wN register so what we can paste a xN 31 * reference after a 'w' to obtain the 32-bit version. 32 */ 33 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 34 wx\n .req w\n 35 .endr 36 37 .macro disable_daif 38 msr daifset, #0xf 39 .endm 40 41 /* 42 * Save/restore interrupts. 43 */ 44 .macro save_and_disable_daif, flags 45 mrs \flags, daif 46 msr daifset, #0xf 47 .endm 48 49 .macro save_and_disable_irq, flags 50 mrs \flags, daif 51 msr daifset, #3 52 .endm 53 54 .macro restore_irq, flags 55 msr daif, \flags 56 .endm 57 58 .macro disable_step_tsk, flgs, tmp 59 tbz \flgs, #TIF_SINGLESTEP, 9990f 60 mrs \tmp, mdscr_el1 61 bic \tmp, \tmp, #MDSCR_EL1_SS 62 msr mdscr_el1, \tmp 63 isb // Take effect before a subsequent clear of DAIF.D 64 9990: 65 .endm 66 67 /* call with daif masked */ 68 .macro enable_step_tsk, flgs, tmp 69 tbz \flgs, #TIF_SINGLESTEP, 9990f 70 mrs \tmp, mdscr_el1 71 orr \tmp, \tmp, #MDSCR_EL1_SS 72 msr mdscr_el1, \tmp 73 9990: 74 .endm 75 76 /* 77 * RAS Error Synchronization barrier 78 */ 79 .macro esb 80 #ifdef CONFIG_ARM64_RAS_EXTN 81 hint #16 82 #else 83 nop 84 #endif 85 .endm 86 87 /* 88 * Value prediction barrier 89 */ 90 .macro csdb 91 hint #20 92 .endm 93 94 /* 95 * Clear Branch History instruction 96 */ 97 .macro clearbhb 98 hint #22 99 .endm 100 101 /* 102 * Speculation barrier 103 */ 104 .macro sb 105 alternative_if_not ARM64_HAS_SB 106 dsb nsh 107 isb 108 alternative_else 109 SB_BARRIER_INSN 110 nop 111 alternative_endif 112 .endm 113 114 /* 115 * NOP sequence 116 */ 117 .macro nops, num 118 .rept \num 119 nop 120 .endr 121 .endm 122 123 /* 124 * Register aliases. 125 */ 126 lr .req x30 // link register 127 128 /* 129 * Vector entry 130 */ 131 .macro ventry label 132 .align 7 133 b \label 134 .endm 135 136 /* 137 * Select code when configured for BE. 138 */ 139 #ifdef CONFIG_CPU_BIG_ENDIAN 140 #define CPU_BE(code...) code 141 #else 142 #define CPU_BE(code...) 143 #endif 144 145 /* 146 * Select code when configured for LE. 147 */ 148 #ifdef CONFIG_CPU_BIG_ENDIAN 149 #define CPU_LE(code...) 150 #else 151 #define CPU_LE(code...) code 152 #endif 153 154 /* 155 * Define a macro that constructs a 64-bit value by concatenating two 156 * 32-bit registers. Note that on big endian systems the order of the 157 * registers is swapped. 158 */ 159 #ifndef CONFIG_CPU_BIG_ENDIAN 160 .macro regs_to_64, rd, lbits, hbits 161 #else 162 .macro regs_to_64, rd, hbits, lbits 163 #endif 164 orr \rd, \lbits, \hbits, lsl #32 165 .endm 166 167 /* 168 * Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where 169 * <symbol> is within the range +/- 4 GB of the PC. 170 */ 171 /* 172 * @dst: destination register (64 bit wide) 173 * @sym: name of the symbol 174 */ 175 .macro adr_l, dst, sym 176 adrp \dst, \sym 177 add \dst, \dst, :lo12:\sym 178 .endm 179 180 /* 181 * @dst: destination register (32 or 64 bit wide) 182 * @sym: name of the symbol 183 * @tmp: optional 64-bit scratch register to be used if <dst> is a 184 * 32-bit wide register, in which case it cannot be used to hold 185 * the address 186 */ 187 .macro ldr_l, dst, sym, tmp= 188 .ifb \tmp 189 adrp \dst, \sym 190 ldr \dst, [\dst, :lo12:\sym] 191 .else 192 adrp \tmp, \sym 193 ldr \dst, [\tmp, :lo12:\sym] 194 .endif 195 .endm 196 197 /* 198 * @src: source register (32 or 64 bit wide) 199 * @sym: name of the symbol 200 * @tmp: mandatory 64-bit scratch register to calculate the address 201 * while <src> needs to be preserved. 202 */ 203 .macro str_l, src, sym, tmp 204 adrp \tmp, \sym 205 str \src, [\tmp, :lo12:\sym] 206 .endm 207 208 /* 209 * @dst: destination register 210 */ 211 #if defined(__KVM_NVHE_HYPERVISOR__) || defined(__KVM_VHE_HYPERVISOR__) 212 .macro get_this_cpu_offset, dst 213 mrs \dst, tpidr_el2 214 .endm 215 #else 216 .macro get_this_cpu_offset, dst 217 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN 218 mrs \dst, tpidr_el1 219 alternative_else 220 mrs \dst, tpidr_el2 221 alternative_endif 222 .endm 223 224 .macro set_this_cpu_offset, src 225 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN 226 msr tpidr_el1, \src 227 alternative_else 228 msr tpidr_el2, \src 229 alternative_endif 230 .endm 231 #endif 232 233 /* 234 * @dst: Result of per_cpu(sym, smp_processor_id()) (can be SP) 235 * @sym: The name of the per-cpu variable 236 * @tmp: scratch register 237 */ 238 .macro adr_this_cpu, dst, sym, tmp 239 adrp \tmp, \sym 240 add \dst, \tmp, #:lo12:\sym 241 get_this_cpu_offset \tmp 242 add \dst, \dst, \tmp 243 .endm 244 245 /* 246 * @dst: Result of READ_ONCE(per_cpu(sym, smp_processor_id())) 247 * @sym: The name of the per-cpu variable 248 * @tmp: scratch register 249 */ 250 .macro ldr_this_cpu dst, sym, tmp 251 adr_l \dst, \sym 252 get_this_cpu_offset \tmp 253 ldr \dst, [\dst, \tmp] 254 .endm 255 256 /* 257 * read_ctr - read CTR_EL0. If the system has mismatched register fields, 258 * provide the system wide safe value from arm64_ftr_reg_ctrel0.sys_val 259 */ 260 .macro read_ctr, reg 261 #ifndef __KVM_NVHE_HYPERVISOR__ 262 alternative_if_not ARM64_MISMATCHED_CACHE_TYPE 263 mrs \reg, ctr_el0 // read CTR 264 nop 265 alternative_else 266 ldr_l \reg, arm64_ftr_reg_ctrel0 + ARM64_FTR_SYSVAL 267 alternative_endif 268 #else 269 alternative_if_not ARM64_KVM_PROTECTED_MODE 270 ASM_BUG() 271 alternative_else_nop_endif 272 alternative_cb ARM64_ALWAYS_SYSTEM, kvm_compute_final_ctr_el0 273 movz \reg, #0 274 movk \reg, #0, lsl #16 275 movk \reg, #0, lsl #32 276 movk \reg, #0, lsl #48 277 alternative_cb_end 278 #endif 279 .endm 280 281 282 /* 283 * raw_dcache_line_size - get the minimum D-cache line size on this CPU 284 * from the CTR register. 285 */ 286 .macro raw_dcache_line_size, reg, tmp 287 mrs \tmp, ctr_el0 // read CTR 288 ubfm \tmp, \tmp, #16, #19 // cache line size encoding 289 mov \reg, #4 // bytes per word 290 lsl \reg, \reg, \tmp // actual cache line size 291 .endm 292 293 /* 294 * dcache_line_size - get the safe D-cache line size across all CPUs 295 */ 296 .macro dcache_line_size, reg, tmp 297 read_ctr \tmp 298 ubfm \tmp, \tmp, #16, #19 // cache line size encoding 299 mov \reg, #4 // bytes per word 300 lsl \reg, \reg, \tmp // actual cache line size 301 .endm 302 303 /* 304 * raw_icache_line_size - get the minimum I-cache line size on this CPU 305 * from the CTR register. 306 */ 307 .macro raw_icache_line_size, reg, tmp 308 mrs \tmp, ctr_el0 // read CTR 309 and \tmp, \tmp, #0xf // cache line size encoding 310 mov \reg, #4 // bytes per word 311 lsl \reg, \reg, \tmp // actual cache line size 312 .endm 313 314 /* 315 * icache_line_size - get the safe I-cache line size across all CPUs 316 */ 317 .macro icache_line_size, reg, tmp 318 read_ctr \tmp 319 and \tmp, \tmp, #0xf // cache line size encoding 320 mov \reg, #4 // bytes per word 321 lsl \reg, \reg, \tmp // actual cache line size 322 .endm 323 324 /* 325 * tcr_set_t0sz - update TCR.T0SZ so that we can load the ID map 326 */ 327 .macro tcr_set_t0sz, valreg, t0sz 328 bfi \valreg, \t0sz, #TCR_EL1_T0SZ_SHIFT, #TCR_EL1_T0SZ_WIDTH 329 .endm 330 331 /* 332 * tcr_set_t1sz - update TCR.T1SZ 333 */ 334 .macro tcr_set_t1sz, valreg, t1sz 335 bfi \valreg, \t1sz, #TCR_EL1_T1SZ_SHIFT, #TCR_EL1_T1SZ_WIDTH 336 .endm 337 338 /* 339 * tcr_compute_pa_size - set TCR.(I)PS to the highest supported 340 * ID_AA64MMFR0_EL1.PARange value 341 * 342 * tcr: register with the TCR_ELx value to be updated 343 * pos: IPS or PS bitfield position 344 * tmp{0,1}: temporary registers 345 */ 346 .macro tcr_compute_pa_size, tcr, pos, tmp0, tmp1 347 mrs \tmp0, ID_AA64MMFR0_EL1 348 // Narrow PARange to fit the PS field in TCR_ELx 349 ubfx \tmp0, \tmp0, #ID_AA64MMFR0_EL1_PARANGE_SHIFT, #3 350 mov \tmp1, #ID_AA64MMFR0_EL1_PARANGE_MAX 351 #ifdef CONFIG_ARM64_LPA2 352 alternative_if_not ARM64_HAS_VA52 353 mov \tmp1, #ID_AA64MMFR0_EL1_PARANGE_48 354 alternative_else_nop_endif 355 #endif 356 cmp \tmp0, \tmp1 357 csel \tmp0, \tmp1, \tmp0, hi 358 bfi \tcr, \tmp0, \pos, #3 359 .endm 360 361 .macro __dcache_op_workaround_clean_cache, op, addr 362 alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE 363 dc \op, \addr 364 alternative_else 365 dc civac, \addr 366 alternative_endif 367 .endm 368 369 /* 370 * Macro to perform a data cache maintenance for the interval 371 * [start, end) with dcache line size explicitly provided. 372 * 373 * op: operation passed to dc instruction 374 * domain: domain used in dsb instruction 375 * start: starting virtual address of the region 376 * end: end virtual address of the region 377 * linesz: dcache line size 378 * fixup: optional label to branch to on user fault 379 * Corrupts: start, end, tmp 380 */ 381 .macro dcache_by_myline_op op, domain, start, end, linesz, tmp, fixup 382 sub \tmp, \linesz, #1 383 bic \start, \start, \tmp 384 alternative_if ARM64_WORKAROUND_4311569 385 mov \tmp, \start 386 alternative_else_nop_endif 387 .Ldcache_op\@: 388 .ifc \op, cvau 389 __dcache_op_workaround_clean_cache \op, \start 390 .else 391 .ifc \op, cvac 392 __dcache_op_workaround_clean_cache \op, \start 393 .else 394 .ifc \op, cvap 395 sys 3, c7, c12, 1, \start // dc cvap 396 .else 397 .ifc \op, cvadp 398 sys 3, c7, c13, 1, \start // dc cvadp 399 .else 400 dc \op, \start 401 .endif 402 .endif 403 .endif 404 .endif 405 add \start, \start, \linesz 406 cmp \start, \end 407 b.lo .Ldcache_op\@ 408 alternative_if ARM64_WORKAROUND_4311569 409 .ifnc \op, cvau 410 mov \start, \tmp 411 mov \tmp, xzr 412 cbnz \start, .Ldcache_op\@ 413 .endif 414 alternative_else_nop_endif 415 dsb \domain 416 417 _cond_uaccess_extable .Ldcache_op\@, \fixup 418 .endm 419 420 /* 421 * Macro to perform a data cache maintenance for the interval 422 * [start, end) 423 * 424 * op: operation passed to dc instruction 425 * domain: domain used in dsb instruction 426 * start: starting virtual address of the region 427 * end: end virtual address of the region 428 * fixup: optional label to branch to on user fault 429 * Corrupts: start, end, tmp1, tmp2 430 */ 431 .macro dcache_by_line_op op, domain, start, end, tmp1, tmp2, fixup 432 dcache_line_size \tmp1, \tmp2 433 dcache_by_myline_op \op, \domain, \start, \end, \tmp1, \tmp2, \fixup 434 .endm 435 436 /* 437 * Macro to perform an instruction cache maintenance for the interval 438 * [start, end) 439 * 440 * start, end: virtual addresses describing the region 441 * fixup: optional label to branch to on user fault 442 * Corrupts: tmp1, tmp2 443 */ 444 .macro invalidate_icache_by_line start, end, tmp1, tmp2, fixup 445 icache_line_size \tmp1, \tmp2 446 sub \tmp2, \tmp1, #1 447 bic \tmp2, \start, \tmp2 448 .Licache_op\@: 449 ic ivau, \tmp2 // invalidate I line PoU 450 add \tmp2, \tmp2, \tmp1 451 cmp \tmp2, \end 452 b.lo .Licache_op\@ 453 dsb ish 454 isb 455 456 _cond_uaccess_extable .Licache_op\@, \fixup 457 .endm 458 459 /* 460 * load_ttbr1 - install @pgtbl as a TTBR1 page table 461 * pgtbl preserved 462 * tmp1/tmp2 clobbered, either may overlap with pgtbl 463 */ 464 .macro load_ttbr1, pgtbl, tmp1, tmp2 465 phys_to_ttbr \tmp1, \pgtbl 466 offset_ttbr1 \tmp1, \tmp2 467 msr ttbr1_el1, \tmp1 468 isb 469 .endm 470 471 /* 472 * To prevent the possibility of old and new partial table walks being visible 473 * in the tlb, switch the ttbr to a zero page when we invalidate the old 474 * records. D4.7.1 'General TLB maintenance requirements' in ARM DDI 0487A.i 475 * Even switching to our copied tables will cause a changed output address at 476 * each stage of the walk. 477 */ 478 .macro break_before_make_ttbr_switch zero_page, page_table, tmp, tmp2 479 phys_to_ttbr \tmp, \zero_page 480 msr ttbr1_el1, \tmp 481 isb 482 tlbi vmalle1 483 dsb nsh 484 load_ttbr1 \page_table, \tmp, \tmp2 485 .endm 486 487 /* 488 * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present 489 */ 490 .macro reset_pmuserenr_el0, tmpreg 491 mrs \tmpreg, id_aa64dfr0_el1 492 ubfx \tmpreg, \tmpreg, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4 493 cmp \tmpreg, #ID_AA64DFR0_EL1_PMUVer_NI 494 ccmp \tmpreg, #ID_AA64DFR0_EL1_PMUVer_IMP_DEF, #4, ne 495 b.eq 9000f // Skip if no PMU present or IMP_DEF 496 msr pmuserenr_el0, xzr // Disable PMU access from EL0 497 9000: 498 .endm 499 500 /* 501 * reset_amuserenr_el0 - reset AMUSERENR_EL0 if AMUv1 present 502 */ 503 .macro reset_amuserenr_el0, tmpreg 504 mrs \tmpreg, id_aa64pfr0_el1 // Check ID_AA64PFR0_EL1 505 ubfx \tmpreg, \tmpreg, #ID_AA64PFR0_EL1_AMU_SHIFT, #4 506 cbz \tmpreg, .Lskip_\@ // Skip if no AMU present 507 msr_s SYS_AMUSERENR_EL0, xzr // Disable AMU access from EL0 508 .Lskip_\@: 509 .endm 510 /* 511 * copy_page - copy src to dest using temp registers t1-t8 512 */ 513 .macro copy_page dest:req src:req t1:req t2:req t3:req t4:req t5:req t6:req t7:req t8:req 514 9998: ldp \t1, \t2, [\src] 515 ldp \t3, \t4, [\src, #16] 516 ldp \t5, \t6, [\src, #32] 517 ldp \t7, \t8, [\src, #48] 518 add \src, \src, #64 519 stnp \t1, \t2, [\dest] 520 stnp \t3, \t4, [\dest, #16] 521 stnp \t5, \t6, [\dest, #32] 522 stnp \t7, \t8, [\dest, #48] 523 add \dest, \dest, #64 524 tst \src, #(PAGE_SIZE - 1) 525 b.ne 9998b 526 .endm 527 528 /* 529 * Annotate a function as being unsuitable for kprobes. 530 */ 531 #ifdef CONFIG_KPROBES 532 #define NOKPROBE(x) \ 533 .pushsection "_kprobe_blacklist", "aw"; \ 534 .quad x; \ 535 .popsection; 536 #else 537 #define NOKPROBE(x) 538 #endif 539 540 #if defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS) 541 #define EXPORT_SYMBOL_NOKASAN(name) 542 #else 543 #define EXPORT_SYMBOL_NOKASAN(name) EXPORT_SYMBOL(name) 544 #endif 545 546 /* 547 * Emit a 64-bit absolute little endian symbol reference in a way that 548 * ensures that it will be resolved at build time, even when building a 549 * PIE binary. This requires cooperation from the linker script, which 550 * must emit the lo32/hi32 halves individually. 551 */ 552 .macro le64sym, sym 553 .long \sym\()_lo32 554 .long \sym\()_hi32 555 .endm 556 557 /* 558 * mov_q - move an immediate constant into a 64-bit register using 559 * between 2 and 4 movz/movk instructions (depending on the 560 * magnitude and sign of the operand) 561 */ 562 .macro mov_q, reg, val 563 .if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff) 564 movz \reg, :abs_g1_s:\val 565 .else 566 .if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff) 567 movz \reg, :abs_g2_s:\val 568 .else 569 movz \reg, :abs_g3:\val 570 movk \reg, :abs_g2_nc:\val 571 .endif 572 movk \reg, :abs_g1_nc:\val 573 .endif 574 movk \reg, :abs_g0_nc:\val 575 .endm 576 577 /* 578 * Return the current task_struct. 579 */ 580 .macro get_current_task, rd 581 mrs \rd, sp_el0 582 .endm 583 584 /* 585 * If the kernel is built for 52-bit virtual addressing but the hardware only 586 * supports 48 bits, we cannot program the pgdir address into TTBR1 directly, 587 * but we have to add an offset so that the TTBR1 address corresponds with the 588 * pgdir entry that covers the lowest 48-bit addressable VA. 589 * 590 * Note that this trick is only used for LVA/64k pages - LPA2/4k pages uses an 591 * additional paging level, and on LPA2/16k pages, we would end up with a root 592 * level table with only 2 entries, which is suboptimal in terms of TLB 593 * utilization, so there we fall back to 47 bits of translation if LPA2 is not 594 * supported. 595 * 596 * orr is used as it can cover the immediate value (and is idempotent). 597 * ttbr: Value of ttbr to set, modified. 598 */ 599 .macro offset_ttbr1, ttbr, tmp 600 #if defined(CONFIG_ARM64_VA_BITS_52) && !defined(CONFIG_ARM64_LPA2) 601 mrs \tmp, tcr_el1 602 and \tmp, \tmp, #TCR_EL1_T1SZ_MASK 603 cmp \tmp, #TCR_T1SZ(VA_BITS_MIN) 604 orr \tmp, \ttbr, #TTBR1_BADDR_4852_OFFSET 605 csel \ttbr, \tmp, \ttbr, eq 606 #endif 607 .endm 608 609 /* 610 * Arrange a physical address in a TTBR register, taking care of 52-bit 611 * addresses. 612 * 613 * phys: physical address, preserved 614 * ttbr: returns the TTBR value 615 */ 616 .macro phys_to_ttbr, ttbr, phys 617 #ifdef CONFIG_ARM64_PA_BITS_52 618 orr \ttbr, \phys, \phys, lsr #46 619 and \ttbr, \ttbr, #TTBR_BADDR_MASK_52 620 #else 621 mov \ttbr, \phys 622 #endif 623 .endm 624 625 .macro phys_to_pte, pte, phys 626 #ifdef CONFIG_ARM64_PA_BITS_52 627 orr \pte, \phys, \phys, lsr #PTE_ADDR_HIGH_SHIFT 628 and \pte, \pte, #PHYS_TO_PTE_ADDR_MASK 629 #else 630 mov \pte, \phys 631 #endif 632 .endm 633 634 /* 635 * tcr_clear_errata_bits - Clear TCR bits that trigger an errata on this CPU. 636 */ 637 .macro tcr_clear_errata_bits, tcr, tmp1, tmp2 638 #ifdef CONFIG_FUJITSU_ERRATUM_010001 639 mrs \tmp1, midr_el1 640 641 mov_q \tmp2, MIDR_FUJITSU_ERRATUM_010001_MASK 642 and \tmp1, \tmp1, \tmp2 643 mov_q \tmp2, MIDR_FUJITSU_ERRATUM_010001 644 cmp \tmp1, \tmp2 645 b.ne 10f 646 647 mov_q \tmp2, TCR_CLEAR_FUJITSU_ERRATUM_010001 648 bic \tcr, \tcr, \tmp2 649 10: 650 #endif /* CONFIG_FUJITSU_ERRATUM_010001 */ 651 .endm 652 653 /** 654 * Errata workaround prior to disable MMU. Insert an ISB immediately prior 655 * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0. 656 */ 657 .macro pre_disable_mmu_workaround 658 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1041 659 isb 660 #endif 661 .endm 662 663 /* 664 * frame_push - Push @regcount callee saved registers to the stack, 665 * starting at x19, as well as x29/x30, and set x29 to 666 * the new value of sp. Add @extra bytes of stack space 667 * for locals. 668 */ 669 .macro frame_push, regcount:req, extra 670 __frame st, \regcount, \extra 671 .endm 672 673 /* 674 * frame_pop - Pop the callee saved registers from the stack that were 675 * pushed in the most recent call to frame_push, as well 676 * as x29/x30 and any extra stack space that may have been 677 * allocated. 678 */ 679 .macro frame_pop 680 __frame ld 681 .endm 682 683 .macro __frame_regs, reg1, reg2, op, num 684 .if .Lframe_regcount == \num 685 \op\()r \reg1, [sp, #(\num + 1) * 8] 686 .elseif .Lframe_regcount > \num 687 \op\()p \reg1, \reg2, [sp, #(\num + 1) * 8] 688 .endif 689 .endm 690 691 .macro __frame, op, regcount, extra=0 692 .ifc \op, st 693 .if (\regcount) < 0 || (\regcount) > 10 694 .error "regcount should be in the range [0 ... 10]" 695 .endif 696 .if ((\extra) % 16) != 0 697 .error "extra should be a multiple of 16 bytes" 698 .endif 699 .ifdef .Lframe_regcount 700 .if .Lframe_regcount != -1 701 .error "frame_push/frame_pop may not be nested" 702 .endif 703 .endif 704 .set .Lframe_regcount, \regcount 705 .set .Lframe_extra, \extra 706 .set .Lframe_local_offset, ((\regcount + 3) / 2) * 16 707 stp x29, x30, [sp, #-.Lframe_local_offset - .Lframe_extra]! 708 mov x29, sp 709 .endif 710 711 __frame_regs x19, x20, \op, 1 712 __frame_regs x21, x22, \op, 3 713 __frame_regs x23, x24, \op, 5 714 __frame_regs x25, x26, \op, 7 715 __frame_regs x27, x28, \op, 9 716 717 .ifc \op, ld 718 .if .Lframe_regcount == -1 719 .error "frame_push/frame_pop may not be nested" 720 .endif 721 ldp x29, x30, [sp], #.Lframe_local_offset + .Lframe_extra 722 .set .Lframe_regcount, -1 723 .endif 724 .endm 725 726 /* 727 * Set SCTLR_ELx to the @reg value, and invalidate the local icache 728 * in the process. This is called when setting the MMU on. 729 */ 730 .macro set_sctlr, sreg, reg 731 msr \sreg, \reg 732 isb 733 /* 734 * Invalidate the local I-cache so that any instructions fetched 735 * speculatively from the PoC are discarded, since they may have 736 * been dynamically patched at the PoU. 737 */ 738 ic iallu 739 dsb nsh 740 isb 741 .endm 742 743 .macro set_sctlr_el1, reg 744 set_sctlr sctlr_el1, \reg 745 .endm 746 747 .macro set_sctlr_el2, reg 748 set_sctlr sctlr_el2, \reg 749 .endm 750 751 /* 752 * Check whether asm code should yield as soon as it is able. This is 753 * the case if we are currently running in task context, and the 754 * TIF_NEED_RESCHED flag is set. (Note that the TIF_NEED_RESCHED flag 755 * is stored negated in the top word of the thread_info::preempt_count 756 * field) 757 */ 758 .macro cond_yield, lbl:req, tmp:req, tmp2 759 #ifdef CONFIG_PREEMPT_VOLUNTARY 760 get_current_task \tmp 761 ldr \tmp, [\tmp, #TSK_TI_PREEMPT] 762 /* 763 * If we are serving a softirq, there is no point in yielding: the 764 * softirq will not be preempted no matter what we do, so we should 765 * run to completion as quickly as we can. The preempt_count field will 766 * have BIT(SOFTIRQ_SHIFT) set in this case, so the zero check will 767 * catch this case too. 768 */ 769 cbz \tmp, \lbl 770 #endif 771 .endm 772 773 /* 774 * Branch Target Identifier (BTI) 775 */ 776 .macro bti, targets 777 .equ .L__bti_targets_c, 34 778 .equ .L__bti_targets_j, 36 779 .equ .L__bti_targets_jc,38 780 hint #.L__bti_targets_\targets 781 .endm 782 783 /* 784 * This macro emits a program property note section identifying 785 * architecture features which require special handling, mainly for 786 * use in assembly files included in the VDSO. 787 */ 788 789 #define NT_GNU_PROPERTY_TYPE_0 5 790 #define GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000 791 792 #define GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1U << 0) 793 #define GNU_PROPERTY_AARCH64_FEATURE_1_PAC (1U << 1) 794 795 #ifdef CONFIG_ARM64_BTI_KERNEL 796 #define GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT \ 797 ((GNU_PROPERTY_AARCH64_FEATURE_1_BTI | \ 798 GNU_PROPERTY_AARCH64_FEATURE_1_PAC)) 799 #endif 800 801 #ifdef GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT 802 .macro emit_aarch64_feature_1_and, feat=GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT 803 .pushsection .note.gnu.property, "a" 804 .align 3 805 .long 2f - 1f 806 .long 6f - 3f 807 .long NT_GNU_PROPERTY_TYPE_0 808 1: .string "GNU" 809 2: 810 .align 3 811 3: .long GNU_PROPERTY_AARCH64_FEATURE_1_AND 812 .long 5f - 4f 813 4: 814 /* 815 * This is described with an array of char in the Linux API 816 * spec but the text and all other usage (including binutils, 817 * clang and GCC) treat this as a 32 bit value so no swizzling 818 * is required for big endian. 819 */ 820 .long \feat 821 5: 822 .align 3 823 6: 824 .popsection 825 .endm 826 827 #else 828 .macro emit_aarch64_feature_1_and, feat=0 829 .endm 830 831 #endif /* GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT */ 832 833 .macro __mitigate_spectre_bhb_loop tmp 834 #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY 835 alternative_cb ARM64_ALWAYS_SYSTEM, spectre_bhb_patch_loop_iter 836 mov \tmp, #32 // Patched to correct the immediate 837 alternative_cb_end 838 .Lspectre_bhb_loop\@: 839 b . + 4 840 subs \tmp, \tmp, #1 841 b.ne .Lspectre_bhb_loop\@ 842 sb 843 #endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ 844 .endm 845 846 .macro mitigate_spectre_bhb_loop tmp 847 #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY 848 alternative_cb ARM64_ALWAYS_SYSTEM, spectre_bhb_patch_loop_mitigation_enable 849 b .L_spectre_bhb_loop_done\@ // Patched to NOP 850 alternative_cb_end 851 __mitigate_spectre_bhb_loop \tmp 852 .L_spectre_bhb_loop_done\@: 853 #endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ 854 .endm 855 856 /* Save/restores x0-x3 to the stack */ 857 .macro __mitigate_spectre_bhb_fw 858 #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY 859 stp x0, x1, [sp, #-16]! 860 stp x2, x3, [sp, #-16]! 861 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_3 862 alternative_cb ARM64_ALWAYS_SYSTEM, smccc_patch_fw_mitigation_conduit 863 nop // Patched to SMC/HVC #0 864 alternative_cb_end 865 ldp x2, x3, [sp], #16 866 ldp x0, x1, [sp], #16 867 #endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ 868 .endm 869 870 .macro mitigate_spectre_bhb_clear_insn 871 #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY 872 alternative_cb ARM64_ALWAYS_SYSTEM, spectre_bhb_patch_clearbhb 873 /* Patched to NOP when not supported */ 874 clearbhb 875 isb 876 alternative_cb_end 877 #endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ 878 .endm 879 #endif /* __ASM_ASSEMBLER_H */ 880