1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP 4 * 5 * (C) Copyright 2014 - 2021, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@amd.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 */ 14 15#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/interrupt-controller/irq.h> 19#include <dt-bindings/power/xlnx-zynqmp-power.h> 20#include <dt-bindings/reset/xlnx-zynqmp-resets.h> 21#include <dt-bindings/thermal/thermal.h> 22 23/ { 24 compatible = "xlnx,zynqmp"; 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 options { 29 u-boot { 30 compatible = "u-boot,config"; 31 bootscr-address = /bits/ 64 <0x20000000>; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu0: cpu@0 { 40 #cooling-cells = <2>; 41 compatible = "arm,cortex-a53"; 42 device_type = "cpu"; 43 enable-method = "psci"; 44 operating-points-v2 = <&cpu_opp_table>; 45 reg = <0x0>; 46 cpu-idle-states = <&CPU_SLEEP_0>; 47 next-level-cache = <&L2>; 48 }; 49 50 cpu1: cpu@1 { 51 #cooling-cells = <2>; 52 compatible = "arm,cortex-a53"; 53 device_type = "cpu"; 54 enable-method = "psci"; 55 reg = <0x1>; 56 operating-points-v2 = <&cpu_opp_table>; 57 cpu-idle-states = <&CPU_SLEEP_0>; 58 next-level-cache = <&L2>; 59 }; 60 61 cpu2: cpu@2 { 62 #cooling-cells = <2>; 63 compatible = "arm,cortex-a53"; 64 device_type = "cpu"; 65 enable-method = "psci"; 66 reg = <0x2>; 67 operating-points-v2 = <&cpu_opp_table>; 68 cpu-idle-states = <&CPU_SLEEP_0>; 69 next-level-cache = <&L2>; 70 }; 71 72 cpu3: cpu@3 { 73 #cooling-cells = <2>; 74 compatible = "arm,cortex-a53"; 75 device_type = "cpu"; 76 enable-method = "psci"; 77 reg = <0x3>; 78 operating-points-v2 = <&cpu_opp_table>; 79 cpu-idle-states = <&CPU_SLEEP_0>; 80 next-level-cache = <&L2>; 81 }; 82 83 L2: l2-cache { 84 compatible = "cache"; 85 cache-level = <2>; 86 cache-unified; 87 }; 88 89 idle-states { 90 entry-method = "psci"; 91 92 CPU_SLEEP_0: cpu-sleep-0 { 93 compatible = "arm,idle-state"; 94 arm,psci-suspend-param = <0x40000000>; 95 local-timer-stop; 96 entry-latency-us = <300>; 97 exit-latency-us = <600>; 98 min-residency-us = <10000>; 99 }; 100 }; 101 }; 102 103 cpu_opp_table: opp-table-cpu { 104 compatible = "operating-points-v2"; 105 opp-shared; 106 opp00 { 107 opp-hz = /bits/ 64 <1199999988>; 108 opp-microvolt = <1000000>; 109 clock-latency-ns = <500000>; 110 }; 111 opp01 { 112 opp-hz = /bits/ 64 <599999994>; 113 opp-microvolt = <1000000>; 114 clock-latency-ns = <500000>; 115 }; 116 opp02 { 117 opp-hz = /bits/ 64 <399999996>; 118 opp-microvolt = <1000000>; 119 clock-latency-ns = <500000>; 120 }; 121 opp03 { 122 opp-hz = /bits/ 64 <299999997>; 123 opp-microvolt = <1000000>; 124 clock-latency-ns = <500000>; 125 }; 126 }; 127 128 reserved-memory { 129 #address-cells = <2>; 130 #size-cells = <2>; 131 ranges; 132 133 rproc_0_fw_image: memory@3ed00000 { 134 no-map; 135 reg = <0x0 0x3ed00000 0x0 0x40000>; 136 }; 137 138 rproc_1_fw_image: memory@3ef00000 { 139 no-map; 140 reg = <0x0 0x3ef00000 0x0 0x40000>; 141 }; 142 }; 143 144 zynqmp_ipi: zynqmp-ipi { 145 bootph-all; 146 compatible = "xlnx,zynqmp-ipi-mailbox"; 147 interrupt-parent = <&gic>; 148 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 149 xlnx,ipi-id = <0>; 150 #address-cells = <2>; 151 #size-cells = <2>; 152 ranges; 153 154 ipi_mailbox_pmu1: mailbox@ff9905c0 { 155 bootph-all; 156 compatible = "xlnx,zynqmp-ipi-dest-mailbox"; 157 reg = <0x0 0xff9905c0 0x0 0x20>, 158 <0x0 0xff9905e0 0x0 0x20>, 159 <0x0 0xff990e80 0x0 0x20>, 160 <0x0 0xff990ea0 0x0 0x20>; 161 reg-names = "local_request_region", 162 "local_response_region", 163 "remote_request_region", 164 "remote_response_region"; 165 #mbox-cells = <1>; 166 xlnx,ipi-id = <4>; 167 }; 168 }; 169 170 dcc: dcc { 171 compatible = "arm,dcc"; 172 status = "disabled"; 173 bootph-all; 174 }; 175 176 pmu { 177 compatible = "arm,cortex-a53-pmu"; 178 interrupt-parent = <&gic>; 179 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 183 interrupt-affinity = <&cpu0>, 184 <&cpu1>, 185 <&cpu2>, 186 <&cpu3>; 187 }; 188 189 psci { 190 compatible = "arm,psci-1.0", "arm,psci-0.2"; 191 method = "smc"; 192 }; 193 194 firmware { 195 optee: optee { 196 compatible = "linaro,optee-tz"; 197 method = "smc"; 198 }; 199 200 zynqmp_firmware: zynqmp-firmware { 201 compatible = "xlnx,zynqmp-firmware"; 202 #power-domain-cells = <1>; 203 method = "smc"; 204 bootph-all; 205 206 zynqmp_power: power-management { 207 bootph-all; 208 compatible = "xlnx,zynqmp-power"; 209 interrupt-parent = <&gic>; 210 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 211 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; 212 mbox-names = "tx", "rx"; 213 }; 214 215 soc-nvmem { 216 compatible = "xlnx,zynqmp-nvmem-fw"; 217 nvmem-layout { 218 compatible = "fixed-layout"; 219 #address-cells = <1>; 220 #size-cells = <1>; 221 222 soc_revision: soc-revision@0 { 223 reg = <0x0 0x4>; 224 }; 225 /* efuse access */ 226 efuse_dna: efuse-dna@c { 227 reg = <0xc 0xc>; 228 }; 229 efuse_usr0: efuse-usr0@20 { 230 reg = <0x20 0x4>; 231 }; 232 efuse_usr1: efuse-usr1@24 { 233 reg = <0x24 0x4>; 234 }; 235 efuse_usr2: efuse-usr2@28 { 236 reg = <0x28 0x4>; 237 }; 238 efuse_usr3: efuse-usr3@2c { 239 reg = <0x2c 0x4>; 240 }; 241 efuse_usr4: efuse-usr4@30 { 242 reg = <0x30 0x4>; 243 }; 244 efuse_usr5: efuse-usr5@34 { 245 reg = <0x34 0x4>; 246 }; 247 efuse_usr6: efuse-usr6@38 { 248 reg = <0x38 0x4>; 249 }; 250 efuse_usr7: efuse-usr7@3c { 251 reg = <0x3c 0x4>; 252 }; 253 efuse_miscusr: efuse-miscusr@40 { 254 reg = <0x40 0x4>; 255 }; 256 efuse_chash: efuse-chash@50 { 257 reg = <0x50 0x4>; 258 }; 259 efuse_pufmisc: efuse-pufmisc@54 { 260 reg = <0x54 0x4>; 261 }; 262 efuse_sec: efuse-sec@58 { 263 reg = <0x58 0x4>; 264 }; 265 efuse_spkid: efuse-spkid@5c { 266 reg = <0x5c 0x4>; 267 }; 268 efuse_aeskey: efuse-aeskey@60 { 269 reg = <0x60 0x20>; 270 }; 271 efuse_ppk0hash: efuse-ppk0hash@a0 { 272 reg = <0xa0 0x30>; 273 }; 274 efuse_ppk1hash: efuse-ppk1hash@d0 { 275 reg = <0xd0 0x30>; 276 }; 277 efuse_pufuser: efuse-pufuser@100 { 278 reg = <0x100 0x7F>; 279 }; 280 }; 281 }; 282 283 zynqmp_pcap: pcap { 284 compatible = "xlnx,zynqmp-pcap-fpga"; 285 }; 286 287 xlnx_aes: zynqmp-aes { 288 compatible = "xlnx,zynqmp-aes"; 289 }; 290 291 zynqmp_reset: reset-controller { 292 compatible = "xlnx,zynqmp-reset"; 293 #reset-cells = <1>; 294 }; 295 296 pinctrl0: pinctrl { 297 compatible = "xlnx,zynqmp-pinctrl"; 298 status = "disabled"; 299 }; 300 301 modepin_gpio: gpio { 302 compatible = "xlnx,zynqmp-gpio-modepin"; 303 gpio-controller; 304 #gpio-cells = <2>; 305 }; 306 }; 307 }; 308 309 timer { 310 compatible = "arm,armv8-timer"; 311 interrupt-parent = <&gic>; 312 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 313 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 314 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 315 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 316 }; 317 318 fpga_full: fpga-region { 319 compatible = "fpga-region"; 320 fpga-mgr = <&zynqmp_pcap>; 321 #address-cells = <2>; 322 #size-cells = <2>; 323 ranges; 324 }; 325 326 rproc_lockstep: remoteproc@ffe00000 { 327 compatible = "xlnx,zynqmp-r5fss"; 328 xlnx,cluster-mode = <1>; 329 xlnx,tcm-mode = <1>; 330 331 #address-cells = <2>; 332 #size-cells = <2>; 333 334 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>, 335 <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>, 336 <0x0 0x10000 0x0 0xffe10000 0x0 0x10000>, 337 <0x0 0x30000 0x0 0xffe30000 0x0 0x10000>; 338 339 r5f@0 { 340 compatible = "xlnx,zynqmp-r5f"; 341 reg = <0x0 0x0 0x0 0x10000>, 342 <0x0 0x20000 0x0 0x10000>, 343 <0x0 0x10000 0x0 0x10000>, 344 <0x0 0x30000 0x0 0x10000>; 345 reg-names = "atcm0", "btcm0", "atcm1", "btcm1"; 346 power-domains = <&zynqmp_firmware PD_RPU_0>, 347 <&zynqmp_firmware PD_R5_0_ATCM>, 348 <&zynqmp_firmware PD_R5_0_BTCM>, 349 <&zynqmp_firmware PD_R5_1_ATCM>, 350 <&zynqmp_firmware PD_R5_1_BTCM>; 351 memory-region = <&rproc_0_fw_image>; 352 }; 353 354 r5f@1 { 355 compatible = "xlnx,zynqmp-r5f"; 356 reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>; 357 reg-names = "atcm0", "btcm0"; 358 power-domains = <&zynqmp_firmware PD_RPU_1>, 359 <&zynqmp_firmware PD_R5_1_ATCM>, 360 <&zynqmp_firmware PD_R5_1_BTCM>; 361 memory-region = <&rproc_1_fw_image>; 362 }; 363 }; 364 365 rproc_split: remoteproc-split@ffe00000 { 366 status = "disabled"; 367 compatible = "xlnx,zynqmp-r5fss"; 368 xlnx,cluster-mode = <0>; 369 xlnx,tcm-mode = <0>; 370 371 #address-cells = <2>; 372 #size-cells = <2>; 373 374 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>, 375 <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>, 376 <0x1 0x0 0x0 0xffe90000 0x0 0x10000>, 377 <0x1 0x20000 0x0 0xffeb0000 0x0 0x10000>; 378 379 r5f@0 { 380 compatible = "xlnx,zynqmp-r5f"; 381 reg = <0x0 0x0 0x0 0x10000>, <0x0 0x20000 0x0 0x10000>; 382 reg-names = "atcm0", "btcm0"; 383 power-domains = <&zynqmp_firmware PD_RPU_0>, 384 <&zynqmp_firmware PD_R5_0_ATCM>, 385 <&zynqmp_firmware PD_R5_0_BTCM>; 386 memory-region = <&rproc_0_fw_image>; 387 }; 388 389 r5f@1 { 390 compatible = "xlnx,zynqmp-r5f"; 391 reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>; 392 reg-names = "atcm0", "btcm0"; 393 power-domains = <&zynqmp_firmware PD_RPU_1>, 394 <&zynqmp_firmware PD_R5_1_ATCM>, 395 <&zynqmp_firmware PD_R5_1_BTCM>; 396 memory-region = <&rproc_1_fw_image>; 397 }; 398 }; 399 400 ams { 401 compatible = "iio-hwmon"; 402 io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, 403 <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, 404 <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, 405 <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, 406 <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>, 407 <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>, 408 <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>, 409 <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>, 410 <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, 411 <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; 412 }; 413 414 415 tsens_apu: thermal-sensor-apu { 416 compatible = "generic-adc-thermal"; 417 #thermal-sensor-cells = <0>; 418 io-channels = <&xilinx_ams 7>; 419 io-channel-names = "sensor-channel"; 420 }; 421 422 tsens_rpu: thermal-sensor-rpu { 423 compatible = "generic-adc-thermal"; 424 #thermal-sensor-cells = <0>; 425 io-channels = <&xilinx_ams 8>; 426 io-channel-names = "sensor-channel"; 427 }; 428 429 tsens_pl: thermal-sensor-pl { 430 compatible = "generic-adc-thermal"; 431 #thermal-sensor-cells = <0>; 432 io-channels = <&xilinx_ams 20>; 433 io-channel-names = "sensor-channel"; 434 }; 435 436 thermal-zones { 437 apu-thermal { 438 polling-delay-passive = <1000>; 439 polling-delay = <5000>; 440 thermal-sensors = <&tsens_apu>; 441 442 trips { 443 apu_passive: passive { 444 temperature = <93000>; 445 hysteresis = <3500>; 446 type = "passive"; 447 }; 448 449 apu_critical: critical { 450 temperature = <96500>; 451 hysteresis = <3500>; 452 type = "critical"; 453 }; 454 }; 455 456 cooling-maps { 457 map { 458 trip = <&apu_passive>; 459 cooling-device = 460 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 461 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 462 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 463 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 464 }; 465 }; 466 }; 467 468 rpu-thermal { 469 polling-delay = <10000>; 470 thermal-sensors = <&tsens_rpu>; 471 472 trips { 473 critical { 474 temperature = <96500>; 475 hysteresis = <3500>; 476 type = "critical"; 477 }; 478 }; 479 }; 480 481 pl-thermal { 482 polling-delay = <10000>; 483 thermal-sensors = <&tsens_pl>; 484 485 trips { 486 critical { 487 temperature = <96500>; 488 hysteresis = <3500>; 489 type = "critical"; 490 }; 491 }; 492 }; 493 }; 494 495 amba: axi { 496 compatible = "simple-bus"; 497 bootph-all; 498 #address-cells = <2>; 499 #size-cells = <2>; 500 ranges; 501 502 can0: can@ff060000 { 503 compatible = "xlnx,zynq-can-1.0"; 504 status = "disabled"; 505 clock-names = "can_clk", "pclk"; 506 reg = <0x0 0xff060000 0x0 0x1000>; 507 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 508 interrupt-parent = <&gic>; 509 tx-fifo-depth = <0x40>; 510 rx-fifo-depth = <0x40>; 511 resets = <&zynqmp_reset ZYNQMP_RESET_CAN0>; 512 power-domains = <&zynqmp_firmware PD_CAN_0>; 513 }; 514 515 can1: can@ff070000 { 516 compatible = "xlnx,zynq-can-1.0"; 517 status = "disabled"; 518 clock-names = "can_clk", "pclk"; 519 reg = <0x0 0xff070000 0x0 0x1000>; 520 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 521 interrupt-parent = <&gic>; 522 tx-fifo-depth = <0x40>; 523 rx-fifo-depth = <0x40>; 524 resets = <&zynqmp_reset ZYNQMP_RESET_CAN1>; 525 power-domains = <&zynqmp_firmware PD_CAN_1>; 526 }; 527 528 cci: cci@fd6e0000 { 529 compatible = "arm,cci-400"; 530 status = "disabled"; 531 reg = <0x0 0xfd6e0000 0x0 0x9000>; 532 ranges = <0x0 0x0 0xfd6e0000 0x10000>; 533 #address-cells = <1>; 534 #size-cells = <1>; 535 536 pmu@9000 { 537 compatible = "arm,cci-400-pmu,r1"; 538 reg = <0x9000 0x5000>; 539 interrupt-parent = <&gic>; 540 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 545 }; 546 }; 547 548 cpu0_debug: debug@fec10000 { 549 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 550 reg = <0x0 0xfec10000 0x0 0x1000>; 551 clock-names = "apb_pclk"; 552 cpu = <&cpu0>; 553 status = "disabled"; 554 }; 555 556 cpu1_debug: debug@fed10000 { 557 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 558 reg = <0x0 0xfed10000 0x0 0x1000>; 559 clock-names = "apb_pclk"; 560 cpu = <&cpu1>; 561 status = "disabled"; 562 }; 563 564 cpu2_debug: debug@fee10000 { 565 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 566 reg = <0x0 0xfee10000 0x0 0x1000>; 567 clock-names = "apb_pclk"; 568 cpu = <&cpu2>; 569 status = "disabled"; 570 }; 571 572 cpu3_debug: debug@fef10000 { 573 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 574 reg = <0x0 0xfef10000 0x0 0x1000>; 575 clock-names = "apb_pclk"; 576 cpu = <&cpu3>; 577 status = "disabled"; 578 }; 579 580 /* GDMA */ 581 fpd_dma_chan1: dma-controller@fd500000 { 582 status = "disabled"; 583 compatible = "xlnx,zynqmp-dma-1.0"; 584 reg = <0x0 0xfd500000 0x0 0x1000>; 585 interrupt-parent = <&gic>; 586 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 587 clock-names = "clk_main", "clk_apb"; 588 #dma-cells = <1>; 589 xlnx,bus-width = <128>; 590 /* iommus = <&smmu 0x14e8>; */ 591 power-domains = <&zynqmp_firmware PD_GDMA>; 592 }; 593 594 fpd_dma_chan2: dma-controller@fd510000 { 595 status = "disabled"; 596 compatible = "xlnx,zynqmp-dma-1.0"; 597 reg = <0x0 0xfd510000 0x0 0x1000>; 598 interrupt-parent = <&gic>; 599 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 600 clock-names = "clk_main", "clk_apb"; 601 #dma-cells = <1>; 602 xlnx,bus-width = <128>; 603 /* iommus = <&smmu 0x14e9>; */ 604 power-domains = <&zynqmp_firmware PD_GDMA>; 605 }; 606 607 fpd_dma_chan3: dma-controller@fd520000 { 608 status = "disabled"; 609 compatible = "xlnx,zynqmp-dma-1.0"; 610 reg = <0x0 0xfd520000 0x0 0x1000>; 611 interrupt-parent = <&gic>; 612 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 613 clock-names = "clk_main", "clk_apb"; 614 #dma-cells = <1>; 615 xlnx,bus-width = <128>; 616 /* iommus = <&smmu 0x14ea>; */ 617 power-domains = <&zynqmp_firmware PD_GDMA>; 618 }; 619 620 fpd_dma_chan4: dma-controller@fd530000 { 621 status = "disabled"; 622 compatible = "xlnx,zynqmp-dma-1.0"; 623 reg = <0x0 0xfd530000 0x0 0x1000>; 624 interrupt-parent = <&gic>; 625 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 626 clock-names = "clk_main", "clk_apb"; 627 #dma-cells = <1>; 628 xlnx,bus-width = <128>; 629 /* iommus = <&smmu 0x14eb>; */ 630 power-domains = <&zynqmp_firmware PD_GDMA>; 631 }; 632 633 fpd_dma_chan5: dma-controller@fd540000 { 634 status = "disabled"; 635 compatible = "xlnx,zynqmp-dma-1.0"; 636 reg = <0x0 0xfd540000 0x0 0x1000>; 637 interrupt-parent = <&gic>; 638 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 639 clock-names = "clk_main", "clk_apb"; 640 #dma-cells = <1>; 641 xlnx,bus-width = <128>; 642 /* iommus = <&smmu 0x14ec>; */ 643 power-domains = <&zynqmp_firmware PD_GDMA>; 644 }; 645 646 fpd_dma_chan6: dma-controller@fd550000 { 647 status = "disabled"; 648 compatible = "xlnx,zynqmp-dma-1.0"; 649 reg = <0x0 0xfd550000 0x0 0x1000>; 650 interrupt-parent = <&gic>; 651 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 652 clock-names = "clk_main", "clk_apb"; 653 #dma-cells = <1>; 654 xlnx,bus-width = <128>; 655 /* iommus = <&smmu 0x14ed>; */ 656 power-domains = <&zynqmp_firmware PD_GDMA>; 657 }; 658 659 fpd_dma_chan7: dma-controller@fd560000 { 660 status = "disabled"; 661 compatible = "xlnx,zynqmp-dma-1.0"; 662 reg = <0x0 0xfd560000 0x0 0x1000>; 663 interrupt-parent = <&gic>; 664 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 665 clock-names = "clk_main", "clk_apb"; 666 #dma-cells = <1>; 667 xlnx,bus-width = <128>; 668 /* iommus = <&smmu 0x14ee>; */ 669 power-domains = <&zynqmp_firmware PD_GDMA>; 670 }; 671 672 fpd_dma_chan8: dma-controller@fd570000 { 673 status = "disabled"; 674 compatible = "xlnx,zynqmp-dma-1.0"; 675 reg = <0x0 0xfd570000 0x0 0x1000>; 676 interrupt-parent = <&gic>; 677 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 678 clock-names = "clk_main", "clk_apb"; 679 #dma-cells = <1>; 680 xlnx,bus-width = <128>; 681 /* iommus = <&smmu 0x14ef>; */ 682 power-domains = <&zynqmp_firmware PD_GDMA>; 683 }; 684 685 gic: interrupt-controller@f9010000 { 686 compatible = "arm,gic-400"; 687 #interrupt-cells = <3>; 688 reg = <0x0 0xf9010000 0x0 0x10000>, 689 <0x0 0xf9020000 0x0 0x20000>, 690 <0x0 0xf9040000 0x0 0x20000>, 691 <0x0 0xf9060000 0x0 0x20000>; 692 interrupt-controller; 693 interrupt-parent = <&gic>; 694 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 695 }; 696 697 gpu: gpu@fd4b0000 { 698 status = "disabled"; 699 compatible = "xlnx,zynqmp-mali", "arm,mali-400"; 700 reg = <0x0 0xfd4b0000 0x0 0x10000>; 701 interrupt-parent = <&gic>; 702 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 708 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1"; 709 clock-names = "bus", "core"; 710 power-domains = <&zynqmp_firmware PD_GPU>; 711 }; 712 713 /* LPDDMA default allows only secured access. inorder to enable 714 * These dma channels, Users should ensure that these dma 715 * Channels are allowed for non secure access. 716 */ 717 lpd_dma_chan1: dma-controller@ffa80000 { 718 status = "disabled"; 719 compatible = "xlnx,zynqmp-dma-1.0"; 720 reg = <0x0 0xffa80000 0x0 0x1000>; 721 interrupt-parent = <&gic>; 722 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 723 clock-names = "clk_main", "clk_apb"; 724 #dma-cells = <1>; 725 xlnx,bus-width = <64>; 726 /* iommus = <&smmu 0x868>; */ 727 power-domains = <&zynqmp_firmware PD_ADMA>; 728 }; 729 730 lpd_dma_chan2: dma-controller@ffa90000 { 731 status = "disabled"; 732 compatible = "xlnx,zynqmp-dma-1.0"; 733 reg = <0x0 0xffa90000 0x0 0x1000>; 734 interrupt-parent = <&gic>; 735 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 736 clock-names = "clk_main", "clk_apb"; 737 #dma-cells = <1>; 738 xlnx,bus-width = <64>; 739 /* iommus = <&smmu 0x869>; */ 740 power-domains = <&zynqmp_firmware PD_ADMA>; 741 }; 742 743 lpd_dma_chan3: dma-controller@ffaa0000 { 744 status = "disabled"; 745 compatible = "xlnx,zynqmp-dma-1.0"; 746 reg = <0x0 0xffaa0000 0x0 0x1000>; 747 interrupt-parent = <&gic>; 748 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 749 clock-names = "clk_main", "clk_apb"; 750 #dma-cells = <1>; 751 xlnx,bus-width = <64>; 752 /* iommus = <&smmu 0x86a>; */ 753 power-domains = <&zynqmp_firmware PD_ADMA>; 754 }; 755 756 lpd_dma_chan4: dma-controller@ffab0000 { 757 status = "disabled"; 758 compatible = "xlnx,zynqmp-dma-1.0"; 759 reg = <0x0 0xffab0000 0x0 0x1000>; 760 interrupt-parent = <&gic>; 761 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 762 clock-names = "clk_main", "clk_apb"; 763 #dma-cells = <1>; 764 xlnx,bus-width = <64>; 765 /* iommus = <&smmu 0x86b>; */ 766 power-domains = <&zynqmp_firmware PD_ADMA>; 767 }; 768 769 lpd_dma_chan5: dma-controller@ffac0000 { 770 status = "disabled"; 771 compatible = "xlnx,zynqmp-dma-1.0"; 772 reg = <0x0 0xffac0000 0x0 0x1000>; 773 interrupt-parent = <&gic>; 774 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 775 clock-names = "clk_main", "clk_apb"; 776 #dma-cells = <1>; 777 xlnx,bus-width = <64>; 778 /* iommus = <&smmu 0x86c>; */ 779 power-domains = <&zynqmp_firmware PD_ADMA>; 780 }; 781 782 lpd_dma_chan6: dma-controller@ffad0000 { 783 status = "disabled"; 784 compatible = "xlnx,zynqmp-dma-1.0"; 785 reg = <0x0 0xffad0000 0x0 0x1000>; 786 interrupt-parent = <&gic>; 787 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 788 clock-names = "clk_main", "clk_apb"; 789 #dma-cells = <1>; 790 xlnx,bus-width = <64>; 791 /* iommus = <&smmu 0x86d>; */ 792 power-domains = <&zynqmp_firmware PD_ADMA>; 793 }; 794 795 lpd_dma_chan7: dma-controller@ffae0000 { 796 status = "disabled"; 797 compatible = "xlnx,zynqmp-dma-1.0"; 798 reg = <0x0 0xffae0000 0x0 0x1000>; 799 interrupt-parent = <&gic>; 800 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 801 clock-names = "clk_main", "clk_apb"; 802 #dma-cells = <1>; 803 xlnx,bus-width = <64>; 804 /* iommus = <&smmu 0x86e>; */ 805 power-domains = <&zynqmp_firmware PD_ADMA>; 806 }; 807 808 lpd_dma_chan8: dma-controller@ffaf0000 { 809 status = "disabled"; 810 compatible = "xlnx,zynqmp-dma-1.0"; 811 reg = <0x0 0xffaf0000 0x0 0x1000>; 812 interrupt-parent = <&gic>; 813 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 814 clock-names = "clk_main", "clk_apb"; 815 #dma-cells = <1>; 816 xlnx,bus-width = <64>; 817 /* iommus = <&smmu 0x86f>; */ 818 power-domains = <&zynqmp_firmware PD_ADMA>; 819 }; 820 821 mc: memory-controller@fd070000 { 822 compatible = "xlnx,zynqmp-ddrc-2.40a"; 823 reg = <0x0 0xfd070000 0x0 0x30000>; 824 interrupt-parent = <&gic>; 825 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 826 }; 827 828 nand0: nand-controller@ff100000 { 829 compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10"; 830 status = "disabled"; 831 reg = <0x0 0xff100000 0x0 0x1000>; 832 clock-names = "controller", "bus"; 833 interrupt-parent = <&gic>; 834 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 835 #address-cells = <1>; 836 #size-cells = <0>; 837 /* iommus = <&smmu 0x872>; */ 838 power-domains = <&zynqmp_firmware PD_NAND>; 839 }; 840 841 gem0: ethernet@ff0b0000 { 842 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 843 status = "disabled"; 844 interrupt-parent = <&gic>; 845 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 846 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 847 reg = <0x0 0xff0b0000 0x0 0x1000>; 848 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 849 /* iommus = <&smmu 0x874>; */ 850 power-domains = <&zynqmp_firmware PD_ETH_0>; 851 resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; 852 reset-names = "gem0_rst"; 853 }; 854 855 gem1: ethernet@ff0c0000 { 856 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 857 status = "disabled"; 858 interrupt-parent = <&gic>; 859 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 861 reg = <0x0 0xff0c0000 0x0 0x1000>; 862 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 863 /* iommus = <&smmu 0x875>; */ 864 power-domains = <&zynqmp_firmware PD_ETH_1>; 865 resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; 866 reset-names = "gem1_rst"; 867 }; 868 869 gem2: ethernet@ff0d0000 { 870 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 871 status = "disabled"; 872 interrupt-parent = <&gic>; 873 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 874 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 875 reg = <0x0 0xff0d0000 0x0 0x1000>; 876 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 877 /* iommus = <&smmu 0x876>; */ 878 power-domains = <&zynqmp_firmware PD_ETH_2>; 879 resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; 880 reset-names = "gem2_rst"; 881 }; 882 883 gem3: ethernet@ff0e0000 { 884 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 885 status = "disabled"; 886 interrupt-parent = <&gic>; 887 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 889 reg = <0x0 0xff0e0000 0x0 0x1000>; 890 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 891 /* iommus = <&smmu 0x877>; */ 892 power-domains = <&zynqmp_firmware PD_ETH_3>; 893 resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>; 894 reset-names = "gem3_rst"; 895 }; 896 897 gpio: gpio@ff0a0000 { 898 compatible = "xlnx,zynqmp-gpio-1.0"; 899 status = "disabled"; 900 #gpio-cells = <0x2>; 901 gpio-controller; 902 interrupt-parent = <&gic>; 903 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 904 interrupt-controller; 905 #interrupt-cells = <2>; 906 reg = <0x0 0xff0a0000 0x0 0x1000>; 907 power-domains = <&zynqmp_firmware PD_GPIO>; 908 }; 909 910 i2c0: i2c@ff020000 { 911 compatible = "cdns,i2c-r1p14"; 912 status = "disabled"; 913 interrupt-parent = <&gic>; 914 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 915 clock-frequency = <400000>; 916 reg = <0x0 0xff020000 0x0 0x1000>; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 power-domains = <&zynqmp_firmware PD_I2C_0>; 920 }; 921 922 i2c1: i2c@ff030000 { 923 compatible = "cdns,i2c-r1p14"; 924 status = "disabled"; 925 interrupt-parent = <&gic>; 926 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 927 clock-frequency = <400000>; 928 reg = <0x0 0xff030000 0x0 0x1000>; 929 #address-cells = <1>; 930 #size-cells = <0>; 931 power-domains = <&zynqmp_firmware PD_I2C_1>; 932 }; 933 934 ocm: memory-controller@ff960000 { 935 compatible = "xlnx,zynqmp-ocmc-1.0"; 936 reg = <0x0 0xff960000 0x0 0x1000>; 937 interrupt-parent = <&gic>; 938 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 939 }; 940 941 pcie: pcie@fd0e0000 { 942 compatible = "xlnx,nwl-pcie-2.11"; 943 status = "disabled"; 944 #address-cells = <3>; 945 #size-cells = <2>; 946 #interrupt-cells = <1>; 947 msi-controller; 948 device_type = "pci"; 949 interrupt-parent = <&gic>; 950 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, /* MSI_1 [63...32] */ 954 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; /* MSI_0 [31...0] */ 955 interrupt-names = "misc", "dummy", "intx", 956 "msi1", "msi0"; 957 msi-parent = <&pcie>; 958 reg = <0x0 0xfd0e0000 0x0 0x1000>, 959 <0x0 0xfd480000 0x0 0x1000>, 960 <0x80 0x00000000 0x0 0x10000000>; 961 reg-names = "breg", "pcireg", "cfg"; 962 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */ 963 <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ 964 bus-range = <0x00 0xff>; 965 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 966 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, 967 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, 968 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, 969 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; 970 /* iommus = <&smmu 0x4d0>; */ 971 power-domains = <&zynqmp_firmware PD_PCIE>; 972 pcie_intc: legacy-interrupt-controller { 973 interrupt-controller; 974 #address-cells = <0>; 975 #interrupt-cells = <1>; 976 }; 977 }; 978 979 qspi: spi@ff0f0000 { 980 bootph-all; 981 compatible = "xlnx,zynqmp-qspi-1.0"; 982 status = "disabled"; 983 clock-names = "ref_clk", "pclk"; 984 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 985 interrupt-parent = <&gic>; 986 num-cs = <1>; 987 reg = <0x0 0xff0f0000 0x0 0x1000>, 988 <0x0 0xc0000000 0x0 0x8000000>; 989 #address-cells = <1>; 990 #size-cells = <0>; 991 /* iommus = <&smmu 0x873>; */ 992 power-domains = <&zynqmp_firmware PD_QSPI>; 993 }; 994 995 psgtr: phy@fd400000 { 996 compatible = "xlnx,zynqmp-psgtr-v1.1"; 997 status = "disabled"; 998 reg = <0x0 0xfd400000 0x0 0x40000>, 999 <0x0 0xfd3d0000 0x0 0x1000>; 1000 reg-names = "serdes", "siou"; 1001 #phy-cells = <4>; 1002 }; 1003 1004 rtc: rtc@ffa60000 { 1005 compatible = "xlnx,zynqmp-rtc"; 1006 status = "disabled"; 1007 reg = <0x0 0xffa60000 0x0 0x100>; 1008 interrupt-parent = <&gic>; 1009 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1010 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1011 interrupt-names = "alarm", "sec"; 1012 calibration = <0x7FFF>; 1013 }; 1014 1015 sata: ahci@fd0c0000 { 1016 compatible = "ceva,ahci-1v84"; 1017 status = "disabled"; 1018 reg = <0x0 0xfd0c0000 0x0 0x2000>; 1019 interrupt-parent = <&gic>; 1020 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1021 power-domains = <&zynqmp_firmware PD_SATA>; 1022 resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; 1023 /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; */ 1024 }; 1025 1026 sdhci0: mmc@ff160000 { 1027 bootph-all; 1028 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 1029 status = "disabled"; 1030 interrupt-parent = <&gic>; 1031 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1032 reg = <0x0 0xff160000 0x0 0x1000>; 1033 clock-names = "clk_xin", "clk_ahb"; 1034 /* iommus = <&smmu 0x870>; */ 1035 #clock-cells = <1>; 1036 clock-output-names = "clk_out_sd0", "clk_in_sd0"; 1037 power-domains = <&zynqmp_firmware PD_SD_0>; 1038 resets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>; 1039 }; 1040 1041 sdhci1: mmc@ff170000 { 1042 bootph-all; 1043 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 1044 status = "disabled"; 1045 interrupt-parent = <&gic>; 1046 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1047 reg = <0x0 0xff170000 0x0 0x1000>; 1048 clock-names = "clk_xin", "clk_ahb"; 1049 /* iommus = <&smmu 0x871>; */ 1050 #clock-cells = <1>; 1051 clock-output-names = "clk_out_sd1", "clk_in_sd1"; 1052 power-domains = <&zynqmp_firmware PD_SD_1>; 1053 resets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>; 1054 }; 1055 1056 smmu: iommu@fd800000 { 1057 compatible = "arm,mmu-500"; 1058 reg = <0x0 0xfd800000 0x0 0x20000>; 1059 #iommu-cells = <1>; 1060 status = "disabled"; 1061 #global-interrupts = <1>; 1062 interrupt-parent = <&gic>; 1063 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1066 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1067 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1068 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1071 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1073 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1074 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1075 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1076 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1077 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1080 }; 1081 1082 spi0: spi@ff040000 { 1083 compatible = "cdns,spi-r1p6"; 1084 status = "disabled"; 1085 interrupt-parent = <&gic>; 1086 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1087 reg = <0x0 0xff040000 0x0 0x1000>; 1088 clock-names = "ref_clk", "pclk"; 1089 #address-cells = <1>; 1090 #size-cells = <0>; 1091 power-domains = <&zynqmp_firmware PD_SPI_0>; 1092 }; 1093 1094 spi1: spi@ff050000 { 1095 compatible = "cdns,spi-r1p6"; 1096 status = "disabled"; 1097 interrupt-parent = <&gic>; 1098 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1099 reg = <0x0 0xff050000 0x0 0x1000>; 1100 clock-names = "ref_clk", "pclk"; 1101 #address-cells = <1>; 1102 #size-cells = <0>; 1103 power-domains = <&zynqmp_firmware PD_SPI_1>; 1104 }; 1105 1106 ttc0: timer@ff110000 { 1107 compatible = "cdns,ttc"; 1108 status = "disabled"; 1109 interrupt-parent = <&gic>; 1110 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1113 reg = <0x0 0xff110000 0x0 0x1000>; 1114 timer-width = <32>; 1115 power-domains = <&zynqmp_firmware PD_TTC_0>; 1116 }; 1117 1118 ttc1: timer@ff120000 { 1119 compatible = "cdns,ttc"; 1120 status = "disabled"; 1121 interrupt-parent = <&gic>; 1122 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1125 reg = <0x0 0xff120000 0x0 0x1000>; 1126 timer-width = <32>; 1127 power-domains = <&zynqmp_firmware PD_TTC_1>; 1128 }; 1129 1130 ttc2: timer@ff130000 { 1131 compatible = "cdns,ttc"; 1132 status = "disabled"; 1133 interrupt-parent = <&gic>; 1134 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1135 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1136 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1137 reg = <0x0 0xff130000 0x0 0x1000>; 1138 timer-width = <32>; 1139 power-domains = <&zynqmp_firmware PD_TTC_2>; 1140 }; 1141 1142 ttc3: timer@ff140000 { 1143 compatible = "cdns,ttc"; 1144 status = "disabled"; 1145 interrupt-parent = <&gic>; 1146 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1147 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1149 reg = <0x0 0xff140000 0x0 0x1000>; 1150 timer-width = <32>; 1151 power-domains = <&zynqmp_firmware PD_TTC_3>; 1152 }; 1153 1154 uart0: serial@ff000000 { 1155 bootph-all; 1156 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; 1157 status = "disabled"; 1158 interrupt-parent = <&gic>; 1159 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1160 reg = <0x0 0xff000000 0x0 0x1000>; 1161 clock-names = "uart_clk", "pclk"; 1162 power-domains = <&zynqmp_firmware PD_UART_0>; 1163 resets = <&zynqmp_reset ZYNQMP_RESET_UART0>; 1164 }; 1165 1166 uart1: serial@ff010000 { 1167 bootph-all; 1168 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; 1169 status = "disabled"; 1170 interrupt-parent = <&gic>; 1171 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1172 reg = <0x0 0xff010000 0x0 0x1000>; 1173 clock-names = "uart_clk", "pclk"; 1174 power-domains = <&zynqmp_firmware PD_UART_1>; 1175 resets = <&zynqmp_reset ZYNQMP_RESET_UART1>; 1176 }; 1177 1178 usb0: usb@ff9d0000 { 1179 #address-cells = <2>; 1180 #size-cells = <2>; 1181 status = "disabled"; 1182 compatible = "xlnx,zynqmp-dwc3"; 1183 reg = <0x0 0xff9d0000 0x0 0x100>; 1184 clock-names = "bus_clk", "ref_clk"; 1185 power-domains = <&zynqmp_firmware PD_USB_0>; 1186 resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, 1187 <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, 1188 <&zynqmp_reset ZYNQMP_RESET_USB0_APB>; 1189 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; 1190 reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; 1191 ranges; 1192 1193 dwc3_0: usb@fe200000 { 1194 compatible = "snps,dwc3"; 1195 status = "disabled"; 1196 reg = <0x0 0xfe200000 0x0 0x40000>; 1197 interrupt-parent = <&gic>; 1198 interrupt-names = "host", "peripheral", "otg", "wakeup"; 1199 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1203 clock-names = "ref"; 1204 /* iommus = <&smmu 0x860>; */ 1205 snps,quirk-frame-length-adjustment = <0x20>; 1206 snps,resume-hs-terminations; 1207 /* dma-coherent; */ 1208 }; 1209 }; 1210 1211 usb1: usb@ff9e0000 { 1212 #address-cells = <2>; 1213 #size-cells = <2>; 1214 status = "disabled"; 1215 compatible = "xlnx,zynqmp-dwc3"; 1216 reg = <0x0 0xff9e0000 0x0 0x100>; 1217 clock-names = "bus_clk", "ref_clk"; 1218 power-domains = <&zynqmp_firmware PD_USB_1>; 1219 resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, 1220 <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, 1221 <&zynqmp_reset ZYNQMP_RESET_USB1_APB>; 1222 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; 1223 ranges; 1224 1225 dwc3_1: usb@fe300000 { 1226 compatible = "snps,dwc3"; 1227 status = "disabled"; 1228 reg = <0x0 0xfe300000 0x0 0x40000>; 1229 interrupt-parent = <&gic>; 1230 interrupt-names = "host", "peripheral", "otg", "wakeup"; 1231 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1235 clock-names = "ref"; 1236 /* iommus = <&smmu 0x861>; */ 1237 snps,quirk-frame-length-adjustment = <0x20>; 1238 snps,resume-hs-terminations; 1239 /* dma-coherent; */ 1240 }; 1241 }; 1242 1243 watchdog0: watchdog@fd4d0000 { 1244 compatible = "cdns,wdt-r1p2"; 1245 status = "disabled"; 1246 interrupt-parent = <&gic>; 1247 interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>; 1248 reg = <0x0 0xfd4d0000 0x0 0x1000>; 1249 timeout-sec = <60>; 1250 reset-on-timeout; 1251 }; 1252 1253 lpd_watchdog: watchdog@ff150000 { 1254 compatible = "cdns,wdt-r1p2"; 1255 status = "disabled"; 1256 interrupt-parent = <&gic>; 1257 interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>; 1258 reg = <0x0 0xff150000 0x0 0x1000>; 1259 timeout-sec = <10>; 1260 }; 1261 1262 xilinx_ams: ams@ffa50000 { 1263 compatible = "xlnx,zynqmp-ams"; 1264 interrupt-parent = <&gic>; 1265 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1266 reg = <0x0 0xffa50000 0x0 0x800>; 1267 #address-cells = <1>; 1268 #size-cells = <1>; 1269 #io-channel-cells = <1>; 1270 ranges = <0 0 0xffa50800 0x800>; 1271 1272 ams_ps: ams-ps@0 { 1273 compatible = "xlnx,zynqmp-ams-ps"; 1274 status = "disabled"; 1275 reg = <0x0 0x400>; 1276 }; 1277 1278 ams_pl: ams-pl@400 { 1279 compatible = "xlnx,zynqmp-ams-pl"; 1280 status = "disabled"; 1281 reg = <0x400 0x400>; 1282 }; 1283 }; 1284 1285 zynqmp_dpdma: dma-controller@fd4c0000 { 1286 compatible = "xlnx,zynqmp-dpdma"; 1287 status = "disabled"; 1288 reg = <0x0 0xfd4c0000 0x0 0x1000>; 1289 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1290 interrupt-parent = <&gic>; 1291 clock-names = "axi_clk"; 1292 power-domains = <&zynqmp_firmware PD_DP>; 1293 /* iommus = <&smmu 0xce4>; */ 1294 #dma-cells = <1>; 1295 }; 1296 1297 zynqmp_dpsub: display@fd4a0000 { 1298 bootph-all; 1299 compatible = "xlnx,zynqmp-dpsub-1.7"; 1300 status = "disabled"; 1301 reg = <0x0 0xfd4a0000 0x0 0x1000>, 1302 <0x0 0xfd4aa000 0x0 0x1000>, 1303 <0x0 0xfd4ab000 0x0 0x1000>, 1304 <0x0 0xfd4ac000 0x0 0x1000>; 1305 reg-names = "dp", "blend", "av_buf", "aud"; 1306 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1307 interrupt-parent = <&gic>; 1308 /* iommus = <&smmu 0xce3>; */ 1309 clock-names = "dp_apb_clk", "dp_aud_clk", 1310 "dp_vtc_pixel_clk_in"; 1311 power-domains = <&zynqmp_firmware PD_DP>; 1312 resets = <&zynqmp_reset ZYNQMP_RESET_DP>; 1313 dma-names = "vid0", "vid1", "vid2", "gfx0", 1314 "aud0", "aud1"; 1315 dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>, 1316 <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>, 1317 <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>, 1318 <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>, 1319 <&zynqmp_dpdma ZYNQMP_DPDMA_AUDIO0>, 1320 <&zynqmp_dpdma ZYNQMP_DPDMA_AUDIO1>; 1321 1322 ports { 1323 #address-cells = <1>; 1324 #size-cells = <0>; 1325 1326 live_video: port@0 { 1327 reg = <0>; 1328 }; 1329 live_gfx: port@1 { 1330 reg = <1>; 1331 }; 1332 live_audio: port@2 { 1333 reg = <2>; 1334 }; 1335 out_video: port@3 { 1336 reg = <3>; 1337 }; 1338 out_audio: port@4 { 1339 reg = <4>; 1340 }; 1341 out_dp: port@5 { 1342 reg = <5>; 1343 }; 1344 }; 1345 }; 1346 }; 1347}; 1348