1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP 4 * 5 * (C) Copyright 2014 - 2021, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 */ 14 15#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> 16#include <dt-bindings/power/xlnx-zynqmp-power.h> 17#include <dt-bindings/reset/xlnx-zynqmp-resets.h> 18 19/ { 20 compatible = "xlnx,zynqmp"; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 cpu0: cpu@0 { 29 compatible = "arm,cortex-a53"; 30 device_type = "cpu"; 31 enable-method = "psci"; 32 operating-points-v2 = <&cpu_opp_table>; 33 reg = <0x0>; 34 cpu-idle-states = <&CPU_SLEEP_0>; 35 }; 36 37 cpu1: cpu@1 { 38 compatible = "arm,cortex-a53"; 39 device_type = "cpu"; 40 enable-method = "psci"; 41 reg = <0x1>; 42 operating-points-v2 = <&cpu_opp_table>; 43 cpu-idle-states = <&CPU_SLEEP_0>; 44 }; 45 46 cpu2: cpu@2 { 47 compatible = "arm,cortex-a53"; 48 device_type = "cpu"; 49 enable-method = "psci"; 50 reg = <0x2>; 51 operating-points-v2 = <&cpu_opp_table>; 52 cpu-idle-states = <&CPU_SLEEP_0>; 53 }; 54 55 cpu3: cpu@3 { 56 compatible = "arm,cortex-a53"; 57 device_type = "cpu"; 58 enable-method = "psci"; 59 reg = <0x3>; 60 operating-points-v2 = <&cpu_opp_table>; 61 cpu-idle-states = <&CPU_SLEEP_0>; 62 }; 63 64 idle-states { 65 entry-method = "psci"; 66 67 CPU_SLEEP_0: cpu-sleep-0 { 68 compatible = "arm,idle-state"; 69 arm,psci-suspend-param = <0x40000000>; 70 local-timer-stop; 71 entry-latency-us = <300>; 72 exit-latency-us = <600>; 73 min-residency-us = <10000>; 74 }; 75 }; 76 }; 77 78 cpu_opp_table: cpu-opp-table { 79 compatible = "operating-points-v2"; 80 opp-shared; 81 opp00 { 82 opp-hz = /bits/ 64 <1199999988>; 83 opp-microvolt = <1000000>; 84 clock-latency-ns = <500000>; 85 }; 86 opp01 { 87 opp-hz = /bits/ 64 <599999994>; 88 opp-microvolt = <1000000>; 89 clock-latency-ns = <500000>; 90 }; 91 opp02 { 92 opp-hz = /bits/ 64 <399999996>; 93 opp-microvolt = <1000000>; 94 clock-latency-ns = <500000>; 95 }; 96 opp03 { 97 opp-hz = /bits/ 64 <299999997>; 98 opp-microvolt = <1000000>; 99 clock-latency-ns = <500000>; 100 }; 101 }; 102 103 zynqmp_ipi: zynqmp_ipi { 104 compatible = "xlnx,zynqmp-ipi-mailbox"; 105 interrupt-parent = <&gic>; 106 interrupts = <0 35 4>; 107 xlnx,ipi-id = <0>; 108 #address-cells = <2>; 109 #size-cells = <2>; 110 ranges; 111 112 ipi_mailbox_pmu1: mailbox@ff990400 { 113 reg = <0x0 0xff9905c0 0x0 0x20>, 114 <0x0 0xff9905e0 0x0 0x20>, 115 <0x0 0xff990e80 0x0 0x20>, 116 <0x0 0xff990ea0 0x0 0x20>; 117 reg-names = "local_request_region", 118 "local_response_region", 119 "remote_request_region", 120 "remote_response_region"; 121 #mbox-cells = <1>; 122 xlnx,ipi-id = <4>; 123 }; 124 }; 125 126 dcc: dcc { 127 compatible = "arm,dcc"; 128 status = "disabled"; 129 }; 130 131 pmu { 132 compatible = "arm,armv8-pmuv3"; 133 interrupt-parent = <&gic>; 134 interrupts = <0 143 4>, 135 <0 144 4>, 136 <0 145 4>, 137 <0 146 4>; 138 }; 139 140 psci { 141 compatible = "arm,psci-0.2"; 142 method = "smc"; 143 }; 144 145 firmware { 146 zynqmp_firmware: zynqmp-firmware { 147 compatible = "xlnx,zynqmp-firmware"; 148 #power-domain-cells = <1>; 149 method = "smc"; 150 151 zynqmp_power: zynqmp-power { 152 compatible = "xlnx,zynqmp-power"; 153 interrupt-parent = <&gic>; 154 interrupts = <0 35 4>; 155 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; 156 mbox-names = "tx", "rx"; 157 }; 158 159 nvmem_firmware { 160 compatible = "xlnx,zynqmp-nvmem-fw"; 161 #address-cells = <1>; 162 #size-cells = <1>; 163 164 soc_revision: soc_revision@0 { 165 reg = <0x0 0x4>; 166 }; 167 }; 168 169 zynqmp_pcap: pcap { 170 compatible = "xlnx,zynqmp-pcap-fpga"; 171 }; 172 173 xlnx_aes: zynqmp-aes { 174 compatible = "xlnx,zynqmp-aes"; 175 }; 176 177 zynqmp_reset: reset-controller { 178 compatible = "xlnx,zynqmp-reset"; 179 #reset-cells = <1>; 180 }; 181 182 pinctrl0: pinctrl { 183 compatible = "xlnx,zynqmp-pinctrl"; 184 status = "disabled"; 185 }; 186 }; 187 }; 188 189 timer { 190 compatible = "arm,armv8-timer"; 191 interrupt-parent = <&gic>; 192 interrupts = <1 13 0xf08>, 193 <1 14 0xf08>, 194 <1 11 0xf08>, 195 <1 10 0xf08>; 196 }; 197 198 fpga_full: fpga-full { 199 compatible = "fpga-region"; 200 fpga-mgr = <&zynqmp_pcap>; 201 #address-cells = <2>; 202 #size-cells = <2>; 203 ranges; 204 }; 205 206 amba: axi { 207 compatible = "simple-bus"; 208 #address-cells = <2>; 209 #size-cells = <2>; 210 ranges; 211 212 can0: can@ff060000 { 213 compatible = "xlnx,zynq-can-1.0"; 214 status = "disabled"; 215 clock-names = "can_clk", "pclk"; 216 reg = <0x0 0xff060000 0x0 0x1000>; 217 interrupts = <0 23 4>; 218 interrupt-parent = <&gic>; 219 tx-fifo-depth = <0x40>; 220 rx-fifo-depth = <0x40>; 221 power-domains = <&zynqmp_firmware PD_CAN_0>; 222 }; 223 224 can1: can@ff070000 { 225 compatible = "xlnx,zynq-can-1.0"; 226 status = "disabled"; 227 clock-names = "can_clk", "pclk"; 228 reg = <0x0 0xff070000 0x0 0x1000>; 229 interrupts = <0 24 4>; 230 interrupt-parent = <&gic>; 231 tx-fifo-depth = <0x40>; 232 rx-fifo-depth = <0x40>; 233 power-domains = <&zynqmp_firmware PD_CAN_1>; 234 }; 235 236 cci: cci@fd6e0000 { 237 compatible = "arm,cci-400"; 238 status = "disabled"; 239 reg = <0x0 0xfd6e0000 0x0 0x9000>; 240 ranges = <0x0 0x0 0xfd6e0000 0x10000>; 241 #address-cells = <1>; 242 #size-cells = <1>; 243 244 pmu@9000 { 245 compatible = "arm,cci-400-pmu,r1"; 246 reg = <0x9000 0x5000>; 247 interrupt-parent = <&gic>; 248 interrupts = <0 123 4>, 249 <0 123 4>, 250 <0 123 4>, 251 <0 123 4>, 252 <0 123 4>; 253 }; 254 }; 255 256 /* GDMA */ 257 fpd_dma_chan1: dma-controller@fd500000 { 258 status = "disabled"; 259 compatible = "xlnx,zynqmp-dma-1.0"; 260 reg = <0x0 0xfd500000 0x0 0x1000>; 261 interrupt-parent = <&gic>; 262 interrupts = <0 124 4>; 263 clock-names = "clk_main", "clk_apb"; 264 #dma-cells = <1>; 265 xlnx,bus-width = <128>; 266 iommus = <&smmu 0x14e8>; 267 power-domains = <&zynqmp_firmware PD_GDMA>; 268 }; 269 270 fpd_dma_chan2: dma-controller@fd510000 { 271 status = "disabled"; 272 compatible = "xlnx,zynqmp-dma-1.0"; 273 reg = <0x0 0xfd510000 0x0 0x1000>; 274 interrupt-parent = <&gic>; 275 interrupts = <0 125 4>; 276 clock-names = "clk_main", "clk_apb"; 277 #dma-cells = <1>; 278 xlnx,bus-width = <128>; 279 iommus = <&smmu 0x14e9>; 280 power-domains = <&zynqmp_firmware PD_GDMA>; 281 }; 282 283 fpd_dma_chan3: dma-controller@fd520000 { 284 status = "disabled"; 285 compatible = "xlnx,zynqmp-dma-1.0"; 286 reg = <0x0 0xfd520000 0x0 0x1000>; 287 interrupt-parent = <&gic>; 288 interrupts = <0 126 4>; 289 clock-names = "clk_main", "clk_apb"; 290 #dma-cells = <1>; 291 xlnx,bus-width = <128>; 292 iommus = <&smmu 0x14ea>; 293 power-domains = <&zynqmp_firmware PD_GDMA>; 294 }; 295 296 fpd_dma_chan4: dma-controller@fd530000 { 297 status = "disabled"; 298 compatible = "xlnx,zynqmp-dma-1.0"; 299 reg = <0x0 0xfd530000 0x0 0x1000>; 300 interrupt-parent = <&gic>; 301 interrupts = <0 127 4>; 302 clock-names = "clk_main", "clk_apb"; 303 #dma-cells = <1>; 304 xlnx,bus-width = <128>; 305 iommus = <&smmu 0x14eb>; 306 power-domains = <&zynqmp_firmware PD_GDMA>; 307 }; 308 309 fpd_dma_chan5: dma-controller@fd540000 { 310 status = "disabled"; 311 compatible = "xlnx,zynqmp-dma-1.0"; 312 reg = <0x0 0xfd540000 0x0 0x1000>; 313 interrupt-parent = <&gic>; 314 interrupts = <0 128 4>; 315 clock-names = "clk_main", "clk_apb"; 316 #dma-cells = <1>; 317 xlnx,bus-width = <128>; 318 iommus = <&smmu 0x14ec>; 319 power-domains = <&zynqmp_firmware PD_GDMA>; 320 }; 321 322 fpd_dma_chan6: dma-controller@fd550000 { 323 status = "disabled"; 324 compatible = "xlnx,zynqmp-dma-1.0"; 325 reg = <0x0 0xfd550000 0x0 0x1000>; 326 interrupt-parent = <&gic>; 327 interrupts = <0 129 4>; 328 clock-names = "clk_main", "clk_apb"; 329 #dma-cells = <1>; 330 xlnx,bus-width = <128>; 331 iommus = <&smmu 0x14ed>; 332 power-domains = <&zynqmp_firmware PD_GDMA>; 333 }; 334 335 fpd_dma_chan7: dma-controller@fd560000 { 336 status = "disabled"; 337 compatible = "xlnx,zynqmp-dma-1.0"; 338 reg = <0x0 0xfd560000 0x0 0x1000>; 339 interrupt-parent = <&gic>; 340 interrupts = <0 130 4>; 341 clock-names = "clk_main", "clk_apb"; 342 #dma-cells = <1>; 343 xlnx,bus-width = <128>; 344 iommus = <&smmu 0x14ee>; 345 power-domains = <&zynqmp_firmware PD_GDMA>; 346 }; 347 348 fpd_dma_chan8: dma-controller@fd570000 { 349 status = "disabled"; 350 compatible = "xlnx,zynqmp-dma-1.0"; 351 reg = <0x0 0xfd570000 0x0 0x1000>; 352 interrupt-parent = <&gic>; 353 interrupts = <0 131 4>; 354 clock-names = "clk_main", "clk_apb"; 355 #dma-cells = <1>; 356 xlnx,bus-width = <128>; 357 iommus = <&smmu 0x14ef>; 358 power-domains = <&zynqmp_firmware PD_GDMA>; 359 }; 360 361 gic: interrupt-controller@f9010000 { 362 compatible = "arm,gic-400"; 363 #address-cells = <0>; 364 #interrupt-cells = <3>; 365 reg = <0x0 0xf9010000 0x0 0x10000>, 366 <0x0 0xf9020000 0x0 0x20000>, 367 <0x0 0xf9040000 0x0 0x20000>, 368 <0x0 0xf9060000 0x0 0x20000>; 369 interrupt-controller; 370 interrupt-parent = <&gic>; 371 interrupts = <1 9 0xf04>; 372 }; 373 374 /* LPDDMA default allows only secured access. inorder to enable 375 * These dma channels, Users should ensure that these dma 376 * Channels are allowed for non secure access. 377 */ 378 lpd_dma_chan1: dma-controller@ffa80000 { 379 status = "disabled"; 380 compatible = "xlnx,zynqmp-dma-1.0"; 381 reg = <0x0 0xffa80000 0x0 0x1000>; 382 interrupt-parent = <&gic>; 383 interrupts = <0 77 4>; 384 clock-names = "clk_main", "clk_apb"; 385 #dma-cells = <1>; 386 xlnx,bus-width = <64>; 387 iommus = <&smmu 0x868>; 388 power-domains = <&zynqmp_firmware PD_ADMA>; 389 }; 390 391 lpd_dma_chan2: dma-controller@ffa90000 { 392 status = "disabled"; 393 compatible = "xlnx,zynqmp-dma-1.0"; 394 reg = <0x0 0xffa90000 0x0 0x1000>; 395 interrupt-parent = <&gic>; 396 interrupts = <0 78 4>; 397 clock-names = "clk_main", "clk_apb"; 398 #dma-cells = <1>; 399 xlnx,bus-width = <64>; 400 iommus = <&smmu 0x869>; 401 power-domains = <&zynqmp_firmware PD_ADMA>; 402 }; 403 404 lpd_dma_chan3: dma-controller@ffaa0000 { 405 status = "disabled"; 406 compatible = "xlnx,zynqmp-dma-1.0"; 407 reg = <0x0 0xffaa0000 0x0 0x1000>; 408 interrupt-parent = <&gic>; 409 interrupts = <0 79 4>; 410 clock-names = "clk_main", "clk_apb"; 411 #dma-cells = <1>; 412 xlnx,bus-width = <64>; 413 iommus = <&smmu 0x86a>; 414 power-domains = <&zynqmp_firmware PD_ADMA>; 415 }; 416 417 lpd_dma_chan4: dma-controller@ffab0000 { 418 status = "disabled"; 419 compatible = "xlnx,zynqmp-dma-1.0"; 420 reg = <0x0 0xffab0000 0x0 0x1000>; 421 interrupt-parent = <&gic>; 422 interrupts = <0 80 4>; 423 clock-names = "clk_main", "clk_apb"; 424 #dma-cells = <1>; 425 xlnx,bus-width = <64>; 426 iommus = <&smmu 0x86b>; 427 power-domains = <&zynqmp_firmware PD_ADMA>; 428 }; 429 430 lpd_dma_chan5: dma-controller@ffac0000 { 431 status = "disabled"; 432 compatible = "xlnx,zynqmp-dma-1.0"; 433 reg = <0x0 0xffac0000 0x0 0x1000>; 434 interrupt-parent = <&gic>; 435 interrupts = <0 81 4>; 436 clock-names = "clk_main", "clk_apb"; 437 #dma-cells = <1>; 438 xlnx,bus-width = <64>; 439 iommus = <&smmu 0x86c>; 440 power-domains = <&zynqmp_firmware PD_ADMA>; 441 }; 442 443 lpd_dma_chan6: dma-controller@ffad0000 { 444 status = "disabled"; 445 compatible = "xlnx,zynqmp-dma-1.0"; 446 reg = <0x0 0xffad0000 0x0 0x1000>; 447 interrupt-parent = <&gic>; 448 interrupts = <0 82 4>; 449 clock-names = "clk_main", "clk_apb"; 450 #dma-cells = <1>; 451 xlnx,bus-width = <64>; 452 iommus = <&smmu 0x86d>; 453 power-domains = <&zynqmp_firmware PD_ADMA>; 454 }; 455 456 lpd_dma_chan7: dma-controller@ffae0000 { 457 status = "disabled"; 458 compatible = "xlnx,zynqmp-dma-1.0"; 459 reg = <0x0 0xffae0000 0x0 0x1000>; 460 interrupt-parent = <&gic>; 461 interrupts = <0 83 4>; 462 clock-names = "clk_main", "clk_apb"; 463 #dma-cells = <1>; 464 xlnx,bus-width = <64>; 465 iommus = <&smmu 0x86e>; 466 power-domains = <&zynqmp_firmware PD_ADMA>; 467 }; 468 469 lpd_dma_chan8: dma-controller@ffaf0000 { 470 status = "disabled"; 471 compatible = "xlnx,zynqmp-dma-1.0"; 472 reg = <0x0 0xffaf0000 0x0 0x1000>; 473 interrupt-parent = <&gic>; 474 interrupts = <0 84 4>; 475 clock-names = "clk_main", "clk_apb"; 476 #dma-cells = <1>; 477 xlnx,bus-width = <64>; 478 iommus = <&smmu 0x86f>; 479 power-domains = <&zynqmp_firmware PD_ADMA>; 480 }; 481 482 mc: memory-controller@fd070000 { 483 compatible = "xlnx,zynqmp-ddrc-2.40a"; 484 reg = <0x0 0xfd070000 0x0 0x30000>; 485 interrupt-parent = <&gic>; 486 interrupts = <0 112 4>; 487 }; 488 489 nand0: nand-controller@ff100000 { 490 compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10"; 491 status = "disabled"; 492 reg = <0x0 0xff100000 0x0 0x1000>; 493 clock-names = "controller", "bus"; 494 interrupt-parent = <&gic>; 495 interrupts = <0 14 4>; 496 #address-cells = <1>; 497 #size-cells = <0>; 498 iommus = <&smmu 0x872>; 499 power-domains = <&zynqmp_firmware PD_NAND>; 500 }; 501 502 gem0: ethernet@ff0b0000 { 503 compatible = "cdns,zynqmp-gem", "cdns,gem"; 504 status = "disabled"; 505 interrupt-parent = <&gic>; 506 interrupts = <0 57 4>, <0 57 4>; 507 reg = <0x0 0xff0b0000 0x0 0x1000>; 508 clock-names = "pclk", "hclk", "tx_clk"; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 iommus = <&smmu 0x874>; 512 power-domains = <&zynqmp_firmware PD_ETH_0>; 513 resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; 514 reset-names = "gem0_rst"; 515 }; 516 517 gem1: ethernet@ff0c0000 { 518 compatible = "cdns,zynqmp-gem", "cdns,gem"; 519 status = "disabled"; 520 interrupt-parent = <&gic>; 521 interrupts = <0 59 4>, <0 59 4>; 522 reg = <0x0 0xff0c0000 0x0 0x1000>; 523 clock-names = "pclk", "hclk", "tx_clk"; 524 #address-cells = <1>; 525 #size-cells = <0>; 526 iommus = <&smmu 0x875>; 527 power-domains = <&zynqmp_firmware PD_ETH_1>; 528 resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; 529 reset-names = "gem1_rst"; 530 }; 531 532 gem2: ethernet@ff0d0000 { 533 compatible = "cdns,zynqmp-gem", "cdns,gem"; 534 status = "disabled"; 535 interrupt-parent = <&gic>; 536 interrupts = <0 61 4>, <0 61 4>; 537 reg = <0x0 0xff0d0000 0x0 0x1000>; 538 clock-names = "pclk", "hclk", "tx_clk"; 539 #address-cells = <1>; 540 #size-cells = <0>; 541 iommus = <&smmu 0x876>; 542 power-domains = <&zynqmp_firmware PD_ETH_2>; 543 resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; 544 reset-names = "gem2_rst"; 545 }; 546 547 gem3: ethernet@ff0e0000 { 548 compatible = "cdns,zynqmp-gem", "cdns,gem"; 549 status = "disabled"; 550 interrupt-parent = <&gic>; 551 interrupts = <0 63 4>, <0 63 4>; 552 reg = <0x0 0xff0e0000 0x0 0x1000>; 553 clock-names = "pclk", "hclk", "tx_clk"; 554 #address-cells = <1>; 555 #size-cells = <0>; 556 iommus = <&smmu 0x877>; 557 power-domains = <&zynqmp_firmware PD_ETH_3>; 558 resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>; 559 reset-names = "gem3_rst"; 560 }; 561 562 gpio: gpio@ff0a0000 { 563 compatible = "xlnx,zynqmp-gpio-1.0"; 564 status = "disabled"; 565 #address-cells = <0>; 566 #gpio-cells = <0x2>; 567 gpio-controller; 568 interrupt-parent = <&gic>; 569 interrupts = <0 16 4>; 570 interrupt-controller; 571 #interrupt-cells = <2>; 572 reg = <0x0 0xff0a0000 0x0 0x1000>; 573 power-domains = <&zynqmp_firmware PD_GPIO>; 574 }; 575 576 i2c0: i2c@ff020000 { 577 compatible = "cdns,i2c-r1p14"; 578 status = "disabled"; 579 interrupt-parent = <&gic>; 580 interrupts = <0 17 4>; 581 reg = <0x0 0xff020000 0x0 0x1000>; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 power-domains = <&zynqmp_firmware PD_I2C_0>; 585 }; 586 587 i2c1: i2c@ff030000 { 588 compatible = "cdns,i2c-r1p14"; 589 status = "disabled"; 590 interrupt-parent = <&gic>; 591 interrupts = <0 18 4>; 592 reg = <0x0 0xff030000 0x0 0x1000>; 593 #address-cells = <1>; 594 #size-cells = <0>; 595 power-domains = <&zynqmp_firmware PD_I2C_1>; 596 }; 597 598 pcie: pcie@fd0e0000 { 599 compatible = "xlnx,nwl-pcie-2.11"; 600 status = "disabled"; 601 #address-cells = <3>; 602 #size-cells = <2>; 603 #interrupt-cells = <1>; 604 msi-controller; 605 device_type = "pci"; 606 interrupt-parent = <&gic>; 607 interrupts = <0 118 4>, 608 <0 117 4>, 609 <0 116 4>, 610 <0 115 4>, /* MSI_1 [63...32] */ 611 <0 114 4>; /* MSI_0 [31...0] */ 612 interrupt-names = "misc", "dummy", "intx", 613 "msi1", "msi0"; 614 msi-parent = <&pcie>; 615 reg = <0x0 0xfd0e0000 0x0 0x1000>, 616 <0x0 0xfd480000 0x0 0x1000>, 617 <0x80 0x00000000 0x0 0x1000000>; 618 reg-names = "breg", "pcireg", "cfg"; 619 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */ 620 <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ 621 bus-range = <0x00 0xff>; 622 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 623 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, 624 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, 625 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, 626 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; 627 iommus = <&smmu 0x4d0>; 628 power-domains = <&zynqmp_firmware PD_PCIE>; 629 pcie_intc: legacy-interrupt-controller { 630 interrupt-controller; 631 #address-cells = <0>; 632 #interrupt-cells = <1>; 633 }; 634 }; 635 636 qspi: spi@ff0f0000 { 637 compatible = "xlnx,zynqmp-qspi-1.0"; 638 status = "disabled"; 639 clock-names = "ref_clk", "pclk"; 640 interrupts = <0 15 4>; 641 interrupt-parent = <&gic>; 642 num-cs = <1>; 643 reg = <0x0 0xff0f0000 0x0 0x1000>, 644 <0x0 0xc0000000 0x0 0x8000000>; 645 #address-cells = <1>; 646 #size-cells = <0>; 647 iommus = <&smmu 0x873>; 648 power-domains = <&zynqmp_firmware PD_QSPI>; 649 }; 650 651 psgtr: phy@fd400000 { 652 compatible = "xlnx,zynqmp-psgtr-v1.1"; 653 status = "disabled"; 654 reg = <0x0 0xfd400000 0x0 0x40000>, 655 <0x0 0xfd3d0000 0x0 0x1000>; 656 reg-names = "serdes", "siou"; 657 #phy-cells = <4>; 658 }; 659 660 rtc: rtc@ffa60000 { 661 compatible = "xlnx,zynqmp-rtc"; 662 status = "disabled"; 663 reg = <0x0 0xffa60000 0x0 0x100>; 664 interrupt-parent = <&gic>; 665 interrupts = <0 26 4>, <0 27 4>; 666 interrupt-names = "alarm", "sec"; 667 calibration = <0x7FFF>; 668 }; 669 670 sata: ahci@fd0c0000 { 671 compatible = "ceva,ahci-1v84"; 672 status = "disabled"; 673 reg = <0x0 0xfd0c0000 0x0 0x2000>; 674 interrupt-parent = <&gic>; 675 interrupts = <0 133 4>; 676 power-domains = <&zynqmp_firmware PD_SATA>; 677 resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; 678 iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, 679 <&smmu 0x4c2>, <&smmu 0x4c3>; 680 }; 681 682 sdhci0: mmc@ff160000 { 683 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 684 status = "disabled"; 685 interrupt-parent = <&gic>; 686 interrupts = <0 48 4>; 687 reg = <0x0 0xff160000 0x0 0x1000>; 688 clock-names = "clk_xin", "clk_ahb"; 689 iommus = <&smmu 0x870>; 690 #clock-cells = <1>; 691 clock-output-names = "clk_out_sd0", "clk_in_sd0"; 692 power-domains = <&zynqmp_firmware PD_SD_0>; 693 }; 694 695 sdhci1: mmc@ff170000 { 696 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 697 status = "disabled"; 698 interrupt-parent = <&gic>; 699 interrupts = <0 49 4>; 700 reg = <0x0 0xff170000 0x0 0x1000>; 701 clock-names = "clk_xin", "clk_ahb"; 702 iommus = <&smmu 0x871>; 703 #clock-cells = <1>; 704 clock-output-names = "clk_out_sd1", "clk_in_sd1"; 705 power-domains = <&zynqmp_firmware PD_SD_1>; 706 }; 707 708 smmu: iommu@fd800000 { 709 compatible = "arm,mmu-500"; 710 reg = <0x0 0xfd800000 0x0 0x20000>; 711 #iommu-cells = <1>; 712 status = "disabled"; 713 #global-interrupts = <1>; 714 interrupt-parent = <&gic>; 715 interrupts = <0 155 4>, 716 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 717 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 718 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 719 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; 720 }; 721 722 spi0: spi@ff040000 { 723 compatible = "cdns,spi-r1p6"; 724 status = "disabled"; 725 interrupt-parent = <&gic>; 726 interrupts = <0 19 4>; 727 reg = <0x0 0xff040000 0x0 0x1000>; 728 clock-names = "ref_clk", "pclk"; 729 #address-cells = <1>; 730 #size-cells = <0>; 731 power-domains = <&zynqmp_firmware PD_SPI_0>; 732 }; 733 734 spi1: spi@ff050000 { 735 compatible = "cdns,spi-r1p6"; 736 status = "disabled"; 737 interrupt-parent = <&gic>; 738 interrupts = <0 20 4>; 739 reg = <0x0 0xff050000 0x0 0x1000>; 740 clock-names = "ref_clk", "pclk"; 741 #address-cells = <1>; 742 #size-cells = <0>; 743 power-domains = <&zynqmp_firmware PD_SPI_1>; 744 }; 745 746 ttc0: timer@ff110000 { 747 compatible = "cdns,ttc"; 748 status = "disabled"; 749 interrupt-parent = <&gic>; 750 interrupts = <0 36 4>, <0 37 4>, <0 38 4>; 751 reg = <0x0 0xff110000 0x0 0x1000>; 752 timer-width = <32>; 753 power-domains = <&zynqmp_firmware PD_TTC_0>; 754 }; 755 756 ttc1: timer@ff120000 { 757 compatible = "cdns,ttc"; 758 status = "disabled"; 759 interrupt-parent = <&gic>; 760 interrupts = <0 39 4>, <0 40 4>, <0 41 4>; 761 reg = <0x0 0xff120000 0x0 0x1000>; 762 timer-width = <32>; 763 power-domains = <&zynqmp_firmware PD_TTC_1>; 764 }; 765 766 ttc2: timer@ff130000 { 767 compatible = "cdns,ttc"; 768 status = "disabled"; 769 interrupt-parent = <&gic>; 770 interrupts = <0 42 4>, <0 43 4>, <0 44 4>; 771 reg = <0x0 0xff130000 0x0 0x1000>; 772 timer-width = <32>; 773 power-domains = <&zynqmp_firmware PD_TTC_2>; 774 }; 775 776 ttc3: timer@ff140000 { 777 compatible = "cdns,ttc"; 778 status = "disabled"; 779 interrupt-parent = <&gic>; 780 interrupts = <0 45 4>, <0 46 4>, <0 47 4>; 781 reg = <0x0 0xff140000 0x0 0x1000>; 782 timer-width = <32>; 783 power-domains = <&zynqmp_firmware PD_TTC_3>; 784 }; 785 786 uart0: serial@ff000000 { 787 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; 788 status = "disabled"; 789 interrupt-parent = <&gic>; 790 interrupts = <0 21 4>; 791 reg = <0x0 0xff000000 0x0 0x1000>; 792 clock-names = "uart_clk", "pclk"; 793 power-domains = <&zynqmp_firmware PD_UART_0>; 794 }; 795 796 uart1: serial@ff010000 { 797 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; 798 status = "disabled"; 799 interrupt-parent = <&gic>; 800 interrupts = <0 22 4>; 801 reg = <0x0 0xff010000 0x0 0x1000>; 802 clock-names = "uart_clk", "pclk"; 803 power-domains = <&zynqmp_firmware PD_UART_1>; 804 }; 805 806 usb0: usb@ff9d0000 { 807 #address-cells = <2>; 808 #size-cells = <2>; 809 status = "disabled"; 810 compatible = "xlnx,zynqmp-dwc3"; 811 reg = <0x0 0xff9d0000 0x0 0x100>; 812 power-domains = <&zynqmp_firmware PD_USB_0>; 813 resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, 814 <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, 815 <&zynqmp_reset ZYNQMP_RESET_USB0_APB>; 816 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; 817 ranges; 818 819 dwc3_0: usb@fe200000 { 820 compatible = "snps,dwc3"; 821 reg = <0x0 0xfe200000 0x0 0x40000>; 822 interrupt-parent = <&gic>; 823 interrupt-names = "dwc_usb3", "otg"; 824 interrupts = <0 65 4>, <0 69 4>; 825 clock-names = "bus_early", "ref"; 826 iommus = <&smmu 0x860>; 827 snps,quirk-frame-length-adjustment = <0x20>; 828 /* dma-coherent; */ 829 }; 830 }; 831 832 usb1: usb@ff9e0000 { 833 #address-cells = <2>; 834 #size-cells = <2>; 835 status = "disabled"; 836 compatible = "xlnx,zynqmp-dwc3"; 837 reg = <0x0 0xff9e0000 0x0 0x100>; 838 power-domains = <&zynqmp_firmware PD_USB_1>; 839 resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, 840 <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, 841 <&zynqmp_reset ZYNQMP_RESET_USB1_APB>; 842 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; 843 ranges; 844 845 dwc3_1: usb@fe300000 { 846 compatible = "snps,dwc3"; 847 reg = <0x0 0xfe300000 0x0 0x40000>; 848 interrupt-parent = <&gic>; 849 interrupt-names = "dwc_usb3", "otg"; 850 interrupts = <0 70 4>, <0 74 4>; 851 clock-names = "bus_early", "ref"; 852 iommus = <&smmu 0x861>; 853 snps,quirk-frame-length-adjustment = <0x20>; 854 /* dma-coherent; */ 855 }; 856 }; 857 858 watchdog0: watchdog@fd4d0000 { 859 compatible = "cdns,wdt-r1p2"; 860 status = "disabled"; 861 interrupt-parent = <&gic>; 862 interrupts = <0 113 1>; 863 reg = <0x0 0xfd4d0000 0x0 0x1000>; 864 timeout-sec = <60>; 865 reset-on-timeout; 866 }; 867 868 lpd_watchdog: watchdog@ff150000 { 869 compatible = "cdns,wdt-r1p2"; 870 status = "disabled"; 871 interrupt-parent = <&gic>; 872 interrupts = <0 52 1>; 873 reg = <0x0 0xff150000 0x0 0x1000>; 874 timeout-sec = <10>; 875 }; 876 877 xilinx_ams: ams@ffa50000 { 878 compatible = "xlnx,zynqmp-ams"; 879 status = "disabled"; 880 interrupt-parent = <&gic>; 881 interrupts = <0 56 4>; 882 reg = <0x0 0xffa50000 0x0 0x800>; 883 #address-cells = <1>; 884 #size-cells = <1>; 885 #io-channel-cells = <1>; 886 ranges = <0 0 0xffa50800 0x800>; 887 888 ams_ps: ams_ps@0 { 889 compatible = "xlnx,zynqmp-ams-ps"; 890 status = "disabled"; 891 reg = <0x0 0x400>; 892 }; 893 894 ams_pl: ams_pl@400 { 895 compatible = "xlnx,zynqmp-ams-pl"; 896 status = "disabled"; 897 reg = <0x400 0x400>; 898 #address-cells = <1>; 899 #size-cells = <0>; 900 }; 901 }; 902 903 zynqmp_dpdma: dma-controller@fd4c0000 { 904 compatible = "xlnx,zynqmp-dpdma"; 905 status = "disabled"; 906 reg = <0x0 0xfd4c0000 0x0 0x1000>; 907 interrupts = <0 122 4>; 908 interrupt-parent = <&gic>; 909 clock-names = "axi_clk"; 910 power-domains = <&zynqmp_firmware PD_DP>; 911 #dma-cells = <1>; 912 }; 913 914 zynqmp_dpsub: display@fd4a0000 { 915 compatible = "xlnx,zynqmp-dpsub-1.7"; 916 status = "disabled"; 917 reg = <0x0 0xfd4a0000 0x0 0x1000>, 918 <0x0 0xfd4aa000 0x0 0x1000>, 919 <0x0 0xfd4ab000 0x0 0x1000>, 920 <0x0 0xfd4ac000 0x0 0x1000>; 921 reg-names = "dp", "blend", "av_buf", "aud"; 922 interrupts = <0 119 4>; 923 interrupt-parent = <&gic>; 924 clock-names = "dp_apb_clk", "dp_aud_clk", 925 "dp_vtc_pixel_clk_in"; 926 power-domains = <&zynqmp_firmware PD_DP>; 927 resets = <&zynqmp_reset ZYNQMP_RESET_DP>; 928 dma-names = "vid0", "vid1", "vid2", "gfx0"; 929 dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>, 930 <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>, 931 <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>, 932 <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>; 933 }; 934 }; 935}; 936