1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP 4 * 5 * (C) Copyright 2014 - 2021, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@amd.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 */ 14 15#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/interrupt-controller/irq.h> 19#include <dt-bindings/power/xlnx-zynqmp-power.h> 20#include <dt-bindings/reset/xlnx-zynqmp-resets.h> 21#include <dt-bindings/thermal/thermal.h> 22 23/ { 24 compatible = "xlnx,zynqmp"; 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 options { 29 u-boot { 30 compatible = "u-boot,config"; 31 bootscr-address = /bits/ 64 <0x20000000>; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu0: cpu@0 { 40 #cooling-cells = <2>; 41 compatible = "arm,cortex-a53"; 42 device_type = "cpu"; 43 enable-method = "psci"; 44 operating-points-v2 = <&cpu_opp_table>; 45 reg = <0x0>; 46 cpu-idle-states = <&CPU_SLEEP_0>; 47 next-level-cache = <&L2>; 48 }; 49 50 cpu1: cpu@1 { 51 #cooling-cells = <2>; 52 compatible = "arm,cortex-a53"; 53 device_type = "cpu"; 54 enable-method = "psci"; 55 reg = <0x1>; 56 operating-points-v2 = <&cpu_opp_table>; 57 cpu-idle-states = <&CPU_SLEEP_0>; 58 next-level-cache = <&L2>; 59 }; 60 61 cpu2: cpu@2 { 62 #cooling-cells = <2>; 63 compatible = "arm,cortex-a53"; 64 device_type = "cpu"; 65 enable-method = "psci"; 66 reg = <0x2>; 67 operating-points-v2 = <&cpu_opp_table>; 68 cpu-idle-states = <&CPU_SLEEP_0>; 69 next-level-cache = <&L2>; 70 }; 71 72 cpu3: cpu@3 { 73 #cooling-cells = <2>; 74 compatible = "arm,cortex-a53"; 75 device_type = "cpu"; 76 enable-method = "psci"; 77 reg = <0x3>; 78 operating-points-v2 = <&cpu_opp_table>; 79 cpu-idle-states = <&CPU_SLEEP_0>; 80 next-level-cache = <&L2>; 81 }; 82 83 L2: l2-cache { 84 compatible = "cache"; 85 cache-level = <2>; 86 cache-unified; 87 }; 88 89 idle-states { 90 entry-method = "psci"; 91 92 CPU_SLEEP_0: cpu-sleep-0 { 93 compatible = "arm,idle-state"; 94 arm,psci-suspend-param = <0x40000000>; 95 local-timer-stop; 96 entry-latency-us = <300>; 97 exit-latency-us = <600>; 98 min-residency-us = <10000>; 99 }; 100 }; 101 }; 102 103 cpu_opp_table: opp-table-cpu { 104 compatible = "operating-points-v2"; 105 opp-shared; 106 opp00 { 107 opp-hz = /bits/ 64 <1199999988>; 108 opp-microvolt = <1000000>; 109 clock-latency-ns = <500000>; 110 }; 111 opp01 { 112 opp-hz = /bits/ 64 <599999994>; 113 opp-microvolt = <1000000>; 114 clock-latency-ns = <500000>; 115 }; 116 opp02 { 117 opp-hz = /bits/ 64 <399999996>; 118 opp-microvolt = <1000000>; 119 clock-latency-ns = <500000>; 120 }; 121 opp03 { 122 opp-hz = /bits/ 64 <299999997>; 123 opp-microvolt = <1000000>; 124 clock-latency-ns = <500000>; 125 }; 126 }; 127 128 reserved-memory { 129 #address-cells = <2>; 130 #size-cells = <2>; 131 ranges; 132 133 rproc_0_fw_image: memory@3ed00000 { 134 no-map; 135 reg = <0x0 0x3ed00000 0x0 0x40000>; 136 }; 137 138 rproc_1_fw_image: memory@3ef00000 { 139 no-map; 140 reg = <0x0 0x3ef00000 0x0 0x40000>; 141 }; 142 }; 143 144 zynqmp_ipi: zynqmp-ipi { 145 bootph-all; 146 compatible = "xlnx,zynqmp-ipi-mailbox"; 147 interrupt-parent = <&gic>; 148 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 149 xlnx,ipi-id = <0>; 150 #address-cells = <2>; 151 #size-cells = <2>; 152 ranges; 153 154 ipi_mailbox_pmu1: mailbox@ff9905c0 { 155 bootph-all; 156 compatible = "xlnx,zynqmp-ipi-dest-mailbox"; 157 reg = <0x0 0xff9905c0 0x0 0x20>, 158 <0x0 0xff9905e0 0x0 0x20>, 159 <0x0 0xff990e80 0x0 0x20>, 160 <0x0 0xff990ea0 0x0 0x20>; 161 reg-names = "local_request_region", 162 "local_response_region", 163 "remote_request_region", 164 "remote_response_region"; 165 #mbox-cells = <1>; 166 xlnx,ipi-id = <4>; 167 }; 168 }; 169 170 dcc: dcc { 171 compatible = "arm,dcc"; 172 status = "disabled"; 173 bootph-all; 174 }; 175 176 pmu { 177 compatible = "arm,cortex-a53-pmu"; 178 interrupt-parent = <&gic>; 179 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 183 interrupt-affinity = <&cpu0>, 184 <&cpu1>, 185 <&cpu2>, 186 <&cpu3>; 187 }; 188 189 psci { 190 compatible = "arm,psci-0.2"; 191 method = "smc"; 192 }; 193 194 firmware { 195 optee: optee { 196 compatible = "linaro,optee-tz"; 197 method = "smc"; 198 }; 199 200 zynqmp_firmware: zynqmp-firmware { 201 compatible = "xlnx,zynqmp-firmware"; 202 #power-domain-cells = <1>; 203 method = "smc"; 204 bootph-all; 205 206 zynqmp_power: power-management { 207 bootph-all; 208 compatible = "xlnx,zynqmp-power"; 209 interrupt-parent = <&gic>; 210 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 211 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; 212 mbox-names = "tx", "rx"; 213 }; 214 215 soc-nvmem { 216 compatible = "xlnx,zynqmp-nvmem-fw"; 217 nvmem-layout { 218 compatible = "fixed-layout"; 219 #address-cells = <1>; 220 #size-cells = <1>; 221 222 soc_revision: soc-revision@0 { 223 reg = <0x0 0x4>; 224 }; 225 /* efuse access */ 226 efuse_dna: efuse-dna@c { 227 reg = <0xc 0xc>; 228 }; 229 efuse_usr0: efuse-usr0@20 { 230 reg = <0x20 0x4>; 231 }; 232 efuse_usr1: efuse-usr1@24 { 233 reg = <0x24 0x4>; 234 }; 235 efuse_usr2: efuse-usr2@28 { 236 reg = <0x28 0x4>; 237 }; 238 efuse_usr3: efuse-usr3@2c { 239 reg = <0x2c 0x4>; 240 }; 241 efuse_usr4: efuse-usr4@30 { 242 reg = <0x30 0x4>; 243 }; 244 efuse_usr5: efuse-usr5@34 { 245 reg = <0x34 0x4>; 246 }; 247 efuse_usr6: efuse-usr6@38 { 248 reg = <0x38 0x4>; 249 }; 250 efuse_usr7: efuse-usr7@3c { 251 reg = <0x3c 0x4>; 252 }; 253 efuse_miscusr: efuse-miscusr@40 { 254 reg = <0x40 0x4>; 255 }; 256 efuse_chash: efuse-chash@50 { 257 reg = <0x50 0x4>; 258 }; 259 efuse_pufmisc: efuse-pufmisc@54 { 260 reg = <0x54 0x4>; 261 }; 262 efuse_sec: efuse-sec@58 { 263 reg = <0x58 0x4>; 264 }; 265 efuse_spkid: efuse-spkid@5c { 266 reg = <0x5c 0x4>; 267 }; 268 efuse_aeskey: efuse-aeskey@60 { 269 reg = <0x60 0x20>; 270 }; 271 efuse_ppk0hash: efuse-ppk0hash@a0 { 272 reg = <0xa0 0x30>; 273 }; 274 efuse_ppk1hash: efuse-ppk1hash@d0 { 275 reg = <0xd0 0x30>; 276 }; 277 efuse_pufuser: efuse-pufuser@100 { 278 reg = <0x100 0x7F>; 279 }; 280 }; 281 }; 282 283 zynqmp_pcap: pcap { 284 compatible = "xlnx,zynqmp-pcap-fpga"; 285 }; 286 287 xlnx_aes: zynqmp-aes { 288 compatible = "xlnx,zynqmp-aes"; 289 }; 290 291 zynqmp_reset: reset-controller { 292 compatible = "xlnx,zynqmp-reset"; 293 #reset-cells = <1>; 294 }; 295 296 pinctrl0: pinctrl { 297 compatible = "xlnx,zynqmp-pinctrl"; 298 status = "disabled"; 299 }; 300 301 modepin_gpio: gpio { 302 compatible = "xlnx,zynqmp-gpio-modepin"; 303 gpio-controller; 304 #gpio-cells = <2>; 305 }; 306 }; 307 }; 308 309 timer { 310 compatible = "arm,armv8-timer"; 311 interrupt-parent = <&gic>; 312 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 313 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 314 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 315 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 316 }; 317 318 fpga_full: fpga-region { 319 compatible = "fpga-region"; 320 fpga-mgr = <&zynqmp_pcap>; 321 #address-cells = <2>; 322 #size-cells = <2>; 323 ranges; 324 }; 325 326 rproc_lockstep: remoteproc@ffe00000 { 327 compatible = "xlnx,zynqmp-r5fss"; 328 xlnx,cluster-mode = <1>; 329 xlnx,tcm-mode = <1>; 330 331 #address-cells = <2>; 332 #size-cells = <2>; 333 334 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>, 335 <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>, 336 <0x0 0x10000 0x0 0xffe10000 0x0 0x10000>, 337 <0x0 0x30000 0x0 0xffe30000 0x0 0x10000>; 338 339 r5f@0 { 340 compatible = "xlnx,zynqmp-r5f"; 341 reg = <0x0 0x0 0x0 0x10000>, 342 <0x0 0x20000 0x0 0x10000>, 343 <0x0 0x10000 0x0 0x10000>, 344 <0x0 0x30000 0x0 0x10000>; 345 reg-names = "atcm0", "btcm0", "atcm1", "btcm1"; 346 power-domains = <&zynqmp_firmware PD_RPU_0>, 347 <&zynqmp_firmware PD_R5_0_ATCM>, 348 <&zynqmp_firmware PD_R5_0_BTCM>, 349 <&zynqmp_firmware PD_R5_1_ATCM>, 350 <&zynqmp_firmware PD_R5_1_BTCM>; 351 memory-region = <&rproc_0_fw_image>; 352 }; 353 354 r5f@1 { 355 compatible = "xlnx,zynqmp-r5f"; 356 reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>; 357 reg-names = "atcm0", "btcm0"; 358 power-domains = <&zynqmp_firmware PD_RPU_1>, 359 <&zynqmp_firmware PD_R5_1_ATCM>, 360 <&zynqmp_firmware PD_R5_1_BTCM>; 361 memory-region = <&rproc_1_fw_image>; 362 }; 363 }; 364 365 rproc_split: remoteproc-split@ffe00000 { 366 status = "disabled"; 367 compatible = "xlnx,zynqmp-r5fss"; 368 xlnx,cluster-mode = <0>; 369 xlnx,tcm-mode = <0>; 370 371 #address-cells = <2>; 372 #size-cells = <2>; 373 374 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>, 375 <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>, 376 <0x1 0x0 0x0 0xffe90000 0x0 0x10000>, 377 <0x1 0x20000 0x0 0xffeb0000 0x0 0x10000>; 378 379 r5f@0 { 380 compatible = "xlnx,zynqmp-r5f"; 381 reg = <0x0 0x0 0x0 0x10000>, <0x0 0x20000 0x0 0x10000>; 382 reg-names = "atcm0", "btcm0"; 383 power-domains = <&zynqmp_firmware PD_RPU_0>, 384 <&zynqmp_firmware PD_R5_0_ATCM>, 385 <&zynqmp_firmware PD_R5_0_BTCM>; 386 memory-region = <&rproc_0_fw_image>; 387 }; 388 389 r5f@1 { 390 compatible = "xlnx,zynqmp-r5f"; 391 reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>; 392 reg-names = "atcm0", "btcm0"; 393 power-domains = <&zynqmp_firmware PD_RPU_1>, 394 <&zynqmp_firmware PD_R5_1_ATCM>, 395 <&zynqmp_firmware PD_R5_1_BTCM>; 396 memory-region = <&rproc_1_fw_image>; 397 }; 398 }; 399 400 ams { 401 compatible = "iio-hwmon"; 402 io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, 403 <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, 404 <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, 405 <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, 406 <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>, 407 <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>, 408 <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>, 409 <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>, 410 <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, 411 <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; 412 }; 413 414 415 tsens_apu: thermal-sensor-apu { 416 compatible = "generic-adc-thermal"; 417 #thermal-sensor-cells = <0>; 418 io-channels = <&xilinx_ams 7>; 419 io-channel-names = "sensor-channel"; 420 }; 421 422 tsens_rpu: thermal-sensor-rpu { 423 compatible = "generic-adc-thermal"; 424 #thermal-sensor-cells = <0>; 425 io-channels = <&xilinx_ams 8>; 426 io-channel-names = "sensor-channel"; 427 }; 428 429 tsens_pl: thermal-sensor-pl { 430 compatible = "generic-adc-thermal"; 431 #thermal-sensor-cells = <0>; 432 io-channels = <&xilinx_ams 20>; 433 io-channel-names = "sensor-channel"; 434 }; 435 436 thermal-zones { 437 apu-thermal { 438 polling-delay-passive = <1000>; 439 polling-delay = <5000>; 440 thermal-sensors = <&tsens_apu>; 441 442 trips { 443 apu_passive: passive { 444 temperature = <93000>; 445 hysteresis = <3500>; 446 type = "passive"; 447 }; 448 449 apu_critical: critical { 450 temperature = <96500>; 451 hysteresis = <3500>; 452 type = "critical"; 453 }; 454 }; 455 456 cooling-maps { 457 map { 458 trip = <&apu_passive>; 459 cooling-device = 460 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 461 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 462 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 463 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 464 }; 465 }; 466 }; 467 468 rpu-thermal { 469 polling-delay = <10000>; 470 thermal-sensors = <&tsens_rpu>; 471 472 trips { 473 critical { 474 temperature = <96500>; 475 hysteresis = <3500>; 476 type = "critical"; 477 }; 478 }; 479 }; 480 481 pl-thermal { 482 polling-delay = <10000>; 483 thermal-sensors = <&tsens_pl>; 484 485 trips { 486 critical { 487 temperature = <96500>; 488 hysteresis = <3500>; 489 type = "critical"; 490 }; 491 }; 492 }; 493 }; 494 495 amba: axi { 496 compatible = "simple-bus"; 497 bootph-all; 498 #address-cells = <2>; 499 #size-cells = <2>; 500 ranges; 501 502 can0: can@ff060000 { 503 compatible = "xlnx,zynq-can-1.0"; 504 status = "disabled"; 505 clock-names = "can_clk", "pclk"; 506 reg = <0x0 0xff060000 0x0 0x1000>; 507 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 508 interrupt-parent = <&gic>; 509 tx-fifo-depth = <0x40>; 510 rx-fifo-depth = <0x40>; 511 resets = <&zynqmp_reset ZYNQMP_RESET_CAN0>; 512 power-domains = <&zynqmp_firmware PD_CAN_0>; 513 }; 514 515 can1: can@ff070000 { 516 compatible = "xlnx,zynq-can-1.0"; 517 status = "disabled"; 518 clock-names = "can_clk", "pclk"; 519 reg = <0x0 0xff070000 0x0 0x1000>; 520 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 521 interrupt-parent = <&gic>; 522 tx-fifo-depth = <0x40>; 523 rx-fifo-depth = <0x40>; 524 resets = <&zynqmp_reset ZYNQMP_RESET_CAN1>; 525 power-domains = <&zynqmp_firmware PD_CAN_1>; 526 }; 527 528 cci: cci@fd6e0000 { 529 compatible = "arm,cci-400"; 530 status = "disabled"; 531 reg = <0x0 0xfd6e0000 0x0 0x9000>; 532 ranges = <0x0 0x0 0xfd6e0000 0x10000>; 533 #address-cells = <1>; 534 #size-cells = <1>; 535 536 pmu@9000 { 537 compatible = "arm,cci-400-pmu,r1"; 538 reg = <0x9000 0x5000>; 539 interrupt-parent = <&gic>; 540 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 545 }; 546 }; 547 548 cpu0_debug: debug@fec10000 { 549 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 550 reg = <0x0 0xfec10000 0x0 0x1000>; 551 clock-names = "apb_pclk"; 552 cpu = <&cpu0>; 553 }; 554 555 cpu1_debug: debug@fed10000 { 556 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 557 reg = <0x0 0xfed10000 0x0 0x1000>; 558 clock-names = "apb_pclk"; 559 cpu = <&cpu1>; 560 }; 561 562 cpu2_debug: debug@fee10000 { 563 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 564 reg = <0x0 0xfee10000 0x0 0x1000>; 565 clock-names = "apb_pclk"; 566 cpu = <&cpu2>; 567 }; 568 569 cpu3_debug: debug@fef10000 { 570 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 571 reg = <0x0 0xfef10000 0x0 0x1000>; 572 clock-names = "apb_pclk"; 573 cpu = <&cpu3>; 574 }; 575 576 /* GDMA */ 577 fpd_dma_chan1: dma-controller@fd500000 { 578 status = "disabled"; 579 compatible = "xlnx,zynqmp-dma-1.0"; 580 reg = <0x0 0xfd500000 0x0 0x1000>; 581 interrupt-parent = <&gic>; 582 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 583 clock-names = "clk_main", "clk_apb"; 584 #dma-cells = <1>; 585 xlnx,bus-width = <128>; 586 /* iommus = <&smmu 0x14e8>; */ 587 power-domains = <&zynqmp_firmware PD_GDMA>; 588 }; 589 590 fpd_dma_chan2: dma-controller@fd510000 { 591 status = "disabled"; 592 compatible = "xlnx,zynqmp-dma-1.0"; 593 reg = <0x0 0xfd510000 0x0 0x1000>; 594 interrupt-parent = <&gic>; 595 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 596 clock-names = "clk_main", "clk_apb"; 597 #dma-cells = <1>; 598 xlnx,bus-width = <128>; 599 /* iommus = <&smmu 0x14e9>; */ 600 power-domains = <&zynqmp_firmware PD_GDMA>; 601 }; 602 603 fpd_dma_chan3: dma-controller@fd520000 { 604 status = "disabled"; 605 compatible = "xlnx,zynqmp-dma-1.0"; 606 reg = <0x0 0xfd520000 0x0 0x1000>; 607 interrupt-parent = <&gic>; 608 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 609 clock-names = "clk_main", "clk_apb"; 610 #dma-cells = <1>; 611 xlnx,bus-width = <128>; 612 /* iommus = <&smmu 0x14ea>; */ 613 power-domains = <&zynqmp_firmware PD_GDMA>; 614 }; 615 616 fpd_dma_chan4: dma-controller@fd530000 { 617 status = "disabled"; 618 compatible = "xlnx,zynqmp-dma-1.0"; 619 reg = <0x0 0xfd530000 0x0 0x1000>; 620 interrupt-parent = <&gic>; 621 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 622 clock-names = "clk_main", "clk_apb"; 623 #dma-cells = <1>; 624 xlnx,bus-width = <128>; 625 /* iommus = <&smmu 0x14eb>; */ 626 power-domains = <&zynqmp_firmware PD_GDMA>; 627 }; 628 629 fpd_dma_chan5: dma-controller@fd540000 { 630 status = "disabled"; 631 compatible = "xlnx,zynqmp-dma-1.0"; 632 reg = <0x0 0xfd540000 0x0 0x1000>; 633 interrupt-parent = <&gic>; 634 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 635 clock-names = "clk_main", "clk_apb"; 636 #dma-cells = <1>; 637 xlnx,bus-width = <128>; 638 /* iommus = <&smmu 0x14ec>; */ 639 power-domains = <&zynqmp_firmware PD_GDMA>; 640 }; 641 642 fpd_dma_chan6: dma-controller@fd550000 { 643 status = "disabled"; 644 compatible = "xlnx,zynqmp-dma-1.0"; 645 reg = <0x0 0xfd550000 0x0 0x1000>; 646 interrupt-parent = <&gic>; 647 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 648 clock-names = "clk_main", "clk_apb"; 649 #dma-cells = <1>; 650 xlnx,bus-width = <128>; 651 /* iommus = <&smmu 0x14ed>; */ 652 power-domains = <&zynqmp_firmware PD_GDMA>; 653 }; 654 655 fpd_dma_chan7: dma-controller@fd560000 { 656 status = "disabled"; 657 compatible = "xlnx,zynqmp-dma-1.0"; 658 reg = <0x0 0xfd560000 0x0 0x1000>; 659 interrupt-parent = <&gic>; 660 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 661 clock-names = "clk_main", "clk_apb"; 662 #dma-cells = <1>; 663 xlnx,bus-width = <128>; 664 /* iommus = <&smmu 0x14ee>; */ 665 power-domains = <&zynqmp_firmware PD_GDMA>; 666 }; 667 668 fpd_dma_chan8: dma-controller@fd570000 { 669 status = "disabled"; 670 compatible = "xlnx,zynqmp-dma-1.0"; 671 reg = <0x0 0xfd570000 0x0 0x1000>; 672 interrupt-parent = <&gic>; 673 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 674 clock-names = "clk_main", "clk_apb"; 675 #dma-cells = <1>; 676 xlnx,bus-width = <128>; 677 /* iommus = <&smmu 0x14ef>; */ 678 power-domains = <&zynqmp_firmware PD_GDMA>; 679 }; 680 681 gic: interrupt-controller@f9010000 { 682 compatible = "arm,gic-400"; 683 #interrupt-cells = <3>; 684 reg = <0x0 0xf9010000 0x0 0x10000>, 685 <0x0 0xf9020000 0x0 0x20000>, 686 <0x0 0xf9040000 0x0 0x20000>, 687 <0x0 0xf9060000 0x0 0x20000>; 688 interrupt-controller; 689 interrupt-parent = <&gic>; 690 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 691 }; 692 693 gpu: gpu@fd4b0000 { 694 status = "disabled"; 695 compatible = "xlnx,zynqmp-mali", "arm,mali-400"; 696 reg = <0x0 0xfd4b0000 0x0 0x10000>; 697 interrupt-parent = <&gic>; 698 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 704 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1"; 705 clock-names = "bus", "core"; 706 power-domains = <&zynqmp_firmware PD_GPU>; 707 }; 708 709 /* LPDDMA default allows only secured access. inorder to enable 710 * These dma channels, Users should ensure that these dma 711 * Channels are allowed for non secure access. 712 */ 713 lpd_dma_chan1: dma-controller@ffa80000 { 714 status = "disabled"; 715 compatible = "xlnx,zynqmp-dma-1.0"; 716 reg = <0x0 0xffa80000 0x0 0x1000>; 717 interrupt-parent = <&gic>; 718 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 719 clock-names = "clk_main", "clk_apb"; 720 #dma-cells = <1>; 721 xlnx,bus-width = <64>; 722 /* iommus = <&smmu 0x868>; */ 723 power-domains = <&zynqmp_firmware PD_ADMA>; 724 }; 725 726 lpd_dma_chan2: dma-controller@ffa90000 { 727 status = "disabled"; 728 compatible = "xlnx,zynqmp-dma-1.0"; 729 reg = <0x0 0xffa90000 0x0 0x1000>; 730 interrupt-parent = <&gic>; 731 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 732 clock-names = "clk_main", "clk_apb"; 733 #dma-cells = <1>; 734 xlnx,bus-width = <64>; 735 /* iommus = <&smmu 0x869>; */ 736 power-domains = <&zynqmp_firmware PD_ADMA>; 737 }; 738 739 lpd_dma_chan3: dma-controller@ffaa0000 { 740 status = "disabled"; 741 compatible = "xlnx,zynqmp-dma-1.0"; 742 reg = <0x0 0xffaa0000 0x0 0x1000>; 743 interrupt-parent = <&gic>; 744 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 745 clock-names = "clk_main", "clk_apb"; 746 #dma-cells = <1>; 747 xlnx,bus-width = <64>; 748 /* iommus = <&smmu 0x86a>; */ 749 power-domains = <&zynqmp_firmware PD_ADMA>; 750 }; 751 752 lpd_dma_chan4: dma-controller@ffab0000 { 753 status = "disabled"; 754 compatible = "xlnx,zynqmp-dma-1.0"; 755 reg = <0x0 0xffab0000 0x0 0x1000>; 756 interrupt-parent = <&gic>; 757 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 758 clock-names = "clk_main", "clk_apb"; 759 #dma-cells = <1>; 760 xlnx,bus-width = <64>; 761 /* iommus = <&smmu 0x86b>; */ 762 power-domains = <&zynqmp_firmware PD_ADMA>; 763 }; 764 765 lpd_dma_chan5: dma-controller@ffac0000 { 766 status = "disabled"; 767 compatible = "xlnx,zynqmp-dma-1.0"; 768 reg = <0x0 0xffac0000 0x0 0x1000>; 769 interrupt-parent = <&gic>; 770 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 771 clock-names = "clk_main", "clk_apb"; 772 #dma-cells = <1>; 773 xlnx,bus-width = <64>; 774 /* iommus = <&smmu 0x86c>; */ 775 power-domains = <&zynqmp_firmware PD_ADMA>; 776 }; 777 778 lpd_dma_chan6: dma-controller@ffad0000 { 779 status = "disabled"; 780 compatible = "xlnx,zynqmp-dma-1.0"; 781 reg = <0x0 0xffad0000 0x0 0x1000>; 782 interrupt-parent = <&gic>; 783 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 784 clock-names = "clk_main", "clk_apb"; 785 #dma-cells = <1>; 786 xlnx,bus-width = <64>; 787 /* iommus = <&smmu 0x86d>; */ 788 power-domains = <&zynqmp_firmware PD_ADMA>; 789 }; 790 791 lpd_dma_chan7: dma-controller@ffae0000 { 792 status = "disabled"; 793 compatible = "xlnx,zynqmp-dma-1.0"; 794 reg = <0x0 0xffae0000 0x0 0x1000>; 795 interrupt-parent = <&gic>; 796 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 797 clock-names = "clk_main", "clk_apb"; 798 #dma-cells = <1>; 799 xlnx,bus-width = <64>; 800 /* iommus = <&smmu 0x86e>; */ 801 power-domains = <&zynqmp_firmware PD_ADMA>; 802 }; 803 804 lpd_dma_chan8: dma-controller@ffaf0000 { 805 status = "disabled"; 806 compatible = "xlnx,zynqmp-dma-1.0"; 807 reg = <0x0 0xffaf0000 0x0 0x1000>; 808 interrupt-parent = <&gic>; 809 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 810 clock-names = "clk_main", "clk_apb"; 811 #dma-cells = <1>; 812 xlnx,bus-width = <64>; 813 /* iommus = <&smmu 0x86f>; */ 814 power-domains = <&zynqmp_firmware PD_ADMA>; 815 }; 816 817 mc: memory-controller@fd070000 { 818 compatible = "xlnx,zynqmp-ddrc-2.40a"; 819 reg = <0x0 0xfd070000 0x0 0x30000>; 820 interrupt-parent = <&gic>; 821 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 822 }; 823 824 nand0: nand-controller@ff100000 { 825 compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10"; 826 status = "disabled"; 827 reg = <0x0 0xff100000 0x0 0x1000>; 828 clock-names = "controller", "bus"; 829 interrupt-parent = <&gic>; 830 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 831 #address-cells = <1>; 832 #size-cells = <0>; 833 /* iommus = <&smmu 0x872>; */ 834 power-domains = <&zynqmp_firmware PD_NAND>; 835 }; 836 837 gem0: ethernet@ff0b0000 { 838 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 839 status = "disabled"; 840 interrupt-parent = <&gic>; 841 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 842 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 843 reg = <0x0 0xff0b0000 0x0 0x1000>; 844 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 845 /* iommus = <&smmu 0x874>; */ 846 power-domains = <&zynqmp_firmware PD_ETH_0>; 847 resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; 848 reset-names = "gem0_rst"; 849 }; 850 851 gem1: ethernet@ff0c0000 { 852 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 853 status = "disabled"; 854 interrupt-parent = <&gic>; 855 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 857 reg = <0x0 0xff0c0000 0x0 0x1000>; 858 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 859 /* iommus = <&smmu 0x875>; */ 860 power-domains = <&zynqmp_firmware PD_ETH_1>; 861 resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; 862 reset-names = "gem1_rst"; 863 }; 864 865 gem2: ethernet@ff0d0000 { 866 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 867 status = "disabled"; 868 interrupt-parent = <&gic>; 869 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 870 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 871 reg = <0x0 0xff0d0000 0x0 0x1000>; 872 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 873 /* iommus = <&smmu 0x876>; */ 874 power-domains = <&zynqmp_firmware PD_ETH_2>; 875 resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; 876 reset-names = "gem2_rst"; 877 }; 878 879 gem3: ethernet@ff0e0000 { 880 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 881 status = "disabled"; 882 interrupt-parent = <&gic>; 883 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 885 reg = <0x0 0xff0e0000 0x0 0x1000>; 886 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 887 /* iommus = <&smmu 0x877>; */ 888 power-domains = <&zynqmp_firmware PD_ETH_3>; 889 resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>; 890 reset-names = "gem3_rst"; 891 }; 892 893 gpio: gpio@ff0a0000 { 894 compatible = "xlnx,zynqmp-gpio-1.0"; 895 status = "disabled"; 896 #gpio-cells = <0x2>; 897 gpio-controller; 898 interrupt-parent = <&gic>; 899 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 900 interrupt-controller; 901 #interrupt-cells = <2>; 902 reg = <0x0 0xff0a0000 0x0 0x1000>; 903 power-domains = <&zynqmp_firmware PD_GPIO>; 904 }; 905 906 i2c0: i2c@ff020000 { 907 compatible = "cdns,i2c-r1p14"; 908 status = "disabled"; 909 interrupt-parent = <&gic>; 910 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 911 clock-frequency = <400000>; 912 reg = <0x0 0xff020000 0x0 0x1000>; 913 #address-cells = <1>; 914 #size-cells = <0>; 915 power-domains = <&zynqmp_firmware PD_I2C_0>; 916 }; 917 918 i2c1: i2c@ff030000 { 919 compatible = "cdns,i2c-r1p14"; 920 status = "disabled"; 921 interrupt-parent = <&gic>; 922 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 923 clock-frequency = <400000>; 924 reg = <0x0 0xff030000 0x0 0x1000>; 925 #address-cells = <1>; 926 #size-cells = <0>; 927 power-domains = <&zynqmp_firmware PD_I2C_1>; 928 }; 929 930 ocm: memory-controller@ff960000 { 931 compatible = "xlnx,zynqmp-ocmc-1.0"; 932 reg = <0x0 0xff960000 0x0 0x1000>; 933 interrupt-parent = <&gic>; 934 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 935 }; 936 937 pcie: pcie@fd0e0000 { 938 compatible = "xlnx,nwl-pcie-2.11"; 939 status = "disabled"; 940 #address-cells = <3>; 941 #size-cells = <2>; 942 #interrupt-cells = <1>; 943 msi-controller; 944 device_type = "pci"; 945 interrupt-parent = <&gic>; 946 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, /* MSI_1 [63...32] */ 950 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; /* MSI_0 [31...0] */ 951 interrupt-names = "misc", "dummy", "intx", 952 "msi1", "msi0"; 953 msi-parent = <&pcie>; 954 reg = <0x0 0xfd0e0000 0x0 0x1000>, 955 <0x0 0xfd480000 0x0 0x1000>, 956 <0x80 0x00000000 0x0 0x10000000>; 957 reg-names = "breg", "pcireg", "cfg"; 958 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */ 959 <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ 960 bus-range = <0x00 0xff>; 961 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 962 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, 963 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, 964 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, 965 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; 966 /* iommus = <&smmu 0x4d0>; */ 967 power-domains = <&zynqmp_firmware PD_PCIE>; 968 pcie_intc: legacy-interrupt-controller { 969 interrupt-controller; 970 #address-cells = <0>; 971 #interrupt-cells = <1>; 972 }; 973 }; 974 975 qspi: spi@ff0f0000 { 976 bootph-all; 977 compatible = "xlnx,zynqmp-qspi-1.0"; 978 status = "disabled"; 979 clock-names = "ref_clk", "pclk"; 980 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 981 interrupt-parent = <&gic>; 982 num-cs = <1>; 983 reg = <0x0 0xff0f0000 0x0 0x1000>, 984 <0x0 0xc0000000 0x0 0x8000000>; 985 #address-cells = <1>; 986 #size-cells = <0>; 987 /* iommus = <&smmu 0x873>; */ 988 power-domains = <&zynqmp_firmware PD_QSPI>; 989 }; 990 991 psgtr: phy@fd400000 { 992 compatible = "xlnx,zynqmp-psgtr-v1.1"; 993 status = "disabled"; 994 reg = <0x0 0xfd400000 0x0 0x40000>, 995 <0x0 0xfd3d0000 0x0 0x1000>; 996 reg-names = "serdes", "siou"; 997 #phy-cells = <4>; 998 }; 999 1000 rtc: rtc@ffa60000 { 1001 compatible = "xlnx,zynqmp-rtc"; 1002 status = "disabled"; 1003 reg = <0x0 0xffa60000 0x0 0x100>; 1004 interrupt-parent = <&gic>; 1005 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1006 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1007 interrupt-names = "alarm", "sec"; 1008 calibration = <0x7FFF>; 1009 }; 1010 1011 sata: ahci@fd0c0000 { 1012 compatible = "ceva,ahci-1v84"; 1013 status = "disabled"; 1014 reg = <0x0 0xfd0c0000 0x0 0x2000>; 1015 interrupt-parent = <&gic>; 1016 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1017 power-domains = <&zynqmp_firmware PD_SATA>; 1018 resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; 1019 /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; */ 1020 }; 1021 1022 sdhci0: mmc@ff160000 { 1023 bootph-all; 1024 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 1025 status = "disabled"; 1026 interrupt-parent = <&gic>; 1027 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1028 reg = <0x0 0xff160000 0x0 0x1000>; 1029 clock-names = "clk_xin", "clk_ahb"; 1030 /* iommus = <&smmu 0x870>; */ 1031 #clock-cells = <1>; 1032 clock-output-names = "clk_out_sd0", "clk_in_sd0"; 1033 power-domains = <&zynqmp_firmware PD_SD_0>; 1034 resets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>; 1035 }; 1036 1037 sdhci1: mmc@ff170000 { 1038 bootph-all; 1039 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 1040 status = "disabled"; 1041 interrupt-parent = <&gic>; 1042 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1043 reg = <0x0 0xff170000 0x0 0x1000>; 1044 clock-names = "clk_xin", "clk_ahb"; 1045 /* iommus = <&smmu 0x871>; */ 1046 #clock-cells = <1>; 1047 clock-output-names = "clk_out_sd1", "clk_in_sd1"; 1048 power-domains = <&zynqmp_firmware PD_SD_1>; 1049 resets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>; 1050 }; 1051 1052 smmu: iommu@fd800000 { 1053 compatible = "arm,mmu-500"; 1054 reg = <0x0 0xfd800000 0x0 0x20000>; 1055 #iommu-cells = <1>; 1056 status = "disabled"; 1057 #global-interrupts = <1>; 1058 interrupt-parent = <&gic>; 1059 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1060 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1061 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1062 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1063 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1066 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1067 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1068 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1071 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1073 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1074 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1075 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1076 }; 1077 1078 spi0: spi@ff040000 { 1079 compatible = "cdns,spi-r1p6"; 1080 status = "disabled"; 1081 interrupt-parent = <&gic>; 1082 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1083 reg = <0x0 0xff040000 0x0 0x1000>; 1084 clock-names = "ref_clk", "pclk"; 1085 #address-cells = <1>; 1086 #size-cells = <0>; 1087 power-domains = <&zynqmp_firmware PD_SPI_0>; 1088 }; 1089 1090 spi1: spi@ff050000 { 1091 compatible = "cdns,spi-r1p6"; 1092 status = "disabled"; 1093 interrupt-parent = <&gic>; 1094 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1095 reg = <0x0 0xff050000 0x0 0x1000>; 1096 clock-names = "ref_clk", "pclk"; 1097 #address-cells = <1>; 1098 #size-cells = <0>; 1099 power-domains = <&zynqmp_firmware PD_SPI_1>; 1100 }; 1101 1102 ttc0: timer@ff110000 { 1103 compatible = "cdns,ttc"; 1104 status = "disabled"; 1105 interrupt-parent = <&gic>; 1106 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1109 reg = <0x0 0xff110000 0x0 0x1000>; 1110 timer-width = <32>; 1111 power-domains = <&zynqmp_firmware PD_TTC_0>; 1112 }; 1113 1114 ttc1: timer@ff120000 { 1115 compatible = "cdns,ttc"; 1116 status = "disabled"; 1117 interrupt-parent = <&gic>; 1118 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1121 reg = <0x0 0xff120000 0x0 0x1000>; 1122 timer-width = <32>; 1123 power-domains = <&zynqmp_firmware PD_TTC_1>; 1124 }; 1125 1126 ttc2: timer@ff130000 { 1127 compatible = "cdns,ttc"; 1128 status = "disabled"; 1129 interrupt-parent = <&gic>; 1130 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1133 reg = <0x0 0xff130000 0x0 0x1000>; 1134 timer-width = <32>; 1135 power-domains = <&zynqmp_firmware PD_TTC_2>; 1136 }; 1137 1138 ttc3: timer@ff140000 { 1139 compatible = "cdns,ttc"; 1140 status = "disabled"; 1141 interrupt-parent = <&gic>; 1142 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1143 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1144 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1145 reg = <0x0 0xff140000 0x0 0x1000>; 1146 timer-width = <32>; 1147 power-domains = <&zynqmp_firmware PD_TTC_3>; 1148 }; 1149 1150 uart0: serial@ff000000 { 1151 bootph-all; 1152 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; 1153 status = "disabled"; 1154 interrupt-parent = <&gic>; 1155 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1156 reg = <0x0 0xff000000 0x0 0x1000>; 1157 clock-names = "uart_clk", "pclk"; 1158 power-domains = <&zynqmp_firmware PD_UART_0>; 1159 resets = <&zynqmp_reset ZYNQMP_RESET_UART0>; 1160 }; 1161 1162 uart1: serial@ff010000 { 1163 bootph-all; 1164 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; 1165 status = "disabled"; 1166 interrupt-parent = <&gic>; 1167 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1168 reg = <0x0 0xff010000 0x0 0x1000>; 1169 clock-names = "uart_clk", "pclk"; 1170 power-domains = <&zynqmp_firmware PD_UART_1>; 1171 resets = <&zynqmp_reset ZYNQMP_RESET_UART1>; 1172 }; 1173 1174 usb0: usb@ff9d0000 { 1175 #address-cells = <2>; 1176 #size-cells = <2>; 1177 status = "disabled"; 1178 compatible = "xlnx,zynqmp-dwc3"; 1179 reg = <0x0 0xff9d0000 0x0 0x100>; 1180 clock-names = "bus_clk", "ref_clk"; 1181 power-domains = <&zynqmp_firmware PD_USB_0>; 1182 resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, 1183 <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, 1184 <&zynqmp_reset ZYNQMP_RESET_USB0_APB>; 1185 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; 1186 reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; 1187 ranges; 1188 1189 dwc3_0: usb@fe200000 { 1190 compatible = "snps,dwc3"; 1191 status = "disabled"; 1192 reg = <0x0 0xfe200000 0x0 0x40000>; 1193 interrupt-parent = <&gic>; 1194 interrupt-names = "host", "peripheral", "otg", "wakeup"; 1195 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1199 clock-names = "ref"; 1200 /* iommus = <&smmu 0x860>; */ 1201 snps,quirk-frame-length-adjustment = <0x20>; 1202 snps,resume-hs-terminations; 1203 /* dma-coherent; */ 1204 }; 1205 }; 1206 1207 usb1: usb@ff9e0000 { 1208 #address-cells = <2>; 1209 #size-cells = <2>; 1210 status = "disabled"; 1211 compatible = "xlnx,zynqmp-dwc3"; 1212 reg = <0x0 0xff9e0000 0x0 0x100>; 1213 clock-names = "bus_clk", "ref_clk"; 1214 power-domains = <&zynqmp_firmware PD_USB_1>; 1215 resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, 1216 <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, 1217 <&zynqmp_reset ZYNQMP_RESET_USB1_APB>; 1218 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; 1219 ranges; 1220 1221 dwc3_1: usb@fe300000 { 1222 compatible = "snps,dwc3"; 1223 status = "disabled"; 1224 reg = <0x0 0xfe300000 0x0 0x40000>; 1225 interrupt-parent = <&gic>; 1226 interrupt-names = "host", "peripheral", "otg", "wakeup"; 1227 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1231 clock-names = "ref"; 1232 /* iommus = <&smmu 0x861>; */ 1233 snps,quirk-frame-length-adjustment = <0x20>; 1234 snps,resume-hs-terminations; 1235 /* dma-coherent; */ 1236 }; 1237 }; 1238 1239 watchdog0: watchdog@fd4d0000 { 1240 compatible = "cdns,wdt-r1p2"; 1241 status = "disabled"; 1242 interrupt-parent = <&gic>; 1243 interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>; 1244 reg = <0x0 0xfd4d0000 0x0 0x1000>; 1245 timeout-sec = <60>; 1246 reset-on-timeout; 1247 }; 1248 1249 lpd_watchdog: watchdog@ff150000 { 1250 compatible = "cdns,wdt-r1p2"; 1251 status = "disabled"; 1252 interrupt-parent = <&gic>; 1253 interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>; 1254 reg = <0x0 0xff150000 0x0 0x1000>; 1255 timeout-sec = <10>; 1256 }; 1257 1258 xilinx_ams: ams@ffa50000 { 1259 compatible = "xlnx,zynqmp-ams"; 1260 interrupt-parent = <&gic>; 1261 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1262 reg = <0x0 0xffa50000 0x0 0x800>; 1263 #address-cells = <1>; 1264 #size-cells = <1>; 1265 #io-channel-cells = <1>; 1266 ranges = <0 0 0xffa50800 0x800>; 1267 1268 ams_ps: ams-ps@0 { 1269 compatible = "xlnx,zynqmp-ams-ps"; 1270 status = "disabled"; 1271 reg = <0x0 0x400>; 1272 }; 1273 1274 ams_pl: ams-pl@400 { 1275 compatible = "xlnx,zynqmp-ams-pl"; 1276 status = "disabled"; 1277 reg = <0x400 0x400>; 1278 }; 1279 }; 1280 1281 zynqmp_dpdma: dma-controller@fd4c0000 { 1282 compatible = "xlnx,zynqmp-dpdma"; 1283 status = "disabled"; 1284 reg = <0x0 0xfd4c0000 0x0 0x1000>; 1285 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1286 interrupt-parent = <&gic>; 1287 clock-names = "axi_clk"; 1288 power-domains = <&zynqmp_firmware PD_DP>; 1289 /* iommus = <&smmu 0xce4>; */ 1290 #dma-cells = <1>; 1291 }; 1292 1293 zynqmp_dpsub: display@fd4a0000 { 1294 bootph-all; 1295 compatible = "xlnx,zynqmp-dpsub-1.7"; 1296 status = "disabled"; 1297 reg = <0x0 0xfd4a0000 0x0 0x1000>, 1298 <0x0 0xfd4aa000 0x0 0x1000>, 1299 <0x0 0xfd4ab000 0x0 0x1000>, 1300 <0x0 0xfd4ac000 0x0 0x1000>; 1301 reg-names = "dp", "blend", "av_buf", "aud"; 1302 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1303 interrupt-parent = <&gic>; 1304 /* iommus = <&smmu 0xce3>; */ 1305 clock-names = "dp_apb_clk", "dp_aud_clk", 1306 "dp_vtc_pixel_clk_in"; 1307 power-domains = <&zynqmp_firmware PD_DP>; 1308 resets = <&zynqmp_reset ZYNQMP_RESET_DP>; 1309 dma-names = "vid0", "vid1", "vid2", "gfx0"; 1310 dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>, 1311 <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>, 1312 <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>, 1313 <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>; 1314 1315 ports { 1316 #address-cells = <1>; 1317 #size-cells = <0>; 1318 1319 port@0 { 1320 reg = <0>; 1321 }; 1322 port@1 { 1323 reg = <1>; 1324 }; 1325 port@2 { 1326 reg = <2>; 1327 }; 1328 port@3 { 1329 reg = <3>; 1330 }; 1331 port@4 { 1332 reg = <4>; 1333 }; 1334 port@5 { 1335 reg = <5>; 1336 }; 1337 }; 1338 }; 1339 }; 1340}; 1341