1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP 4 * 5 * (C) Copyright 2014 - 2021, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@amd.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 */ 14 15#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/interrupt-controller/irq.h> 19#include <dt-bindings/power/xlnx-zynqmp-power.h> 20#include <dt-bindings/reset/xlnx-zynqmp-resets.h> 21 22/ { 23 compatible = "xlnx,zynqmp"; 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 options { 28 u-boot { 29 compatible = "u-boot,config"; 30 bootscr-address = /bits/ 64 <0x20000000>; 31 }; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 cpu0: cpu@0 { 39 compatible = "arm,cortex-a53"; 40 device_type = "cpu"; 41 enable-method = "psci"; 42 operating-points-v2 = <&cpu_opp_table>; 43 reg = <0x0>; 44 cpu-idle-states = <&CPU_SLEEP_0>; 45 next-level-cache = <&L2>; 46 }; 47 48 cpu1: cpu@1 { 49 compatible = "arm,cortex-a53"; 50 device_type = "cpu"; 51 enable-method = "psci"; 52 reg = <0x1>; 53 operating-points-v2 = <&cpu_opp_table>; 54 cpu-idle-states = <&CPU_SLEEP_0>; 55 next-level-cache = <&L2>; 56 }; 57 58 cpu2: cpu@2 { 59 compatible = "arm,cortex-a53"; 60 device_type = "cpu"; 61 enable-method = "psci"; 62 reg = <0x2>; 63 operating-points-v2 = <&cpu_opp_table>; 64 cpu-idle-states = <&CPU_SLEEP_0>; 65 next-level-cache = <&L2>; 66 }; 67 68 cpu3: cpu@3 { 69 compatible = "arm,cortex-a53"; 70 device_type = "cpu"; 71 enable-method = "psci"; 72 reg = <0x3>; 73 operating-points-v2 = <&cpu_opp_table>; 74 cpu-idle-states = <&CPU_SLEEP_0>; 75 next-level-cache = <&L2>; 76 }; 77 78 L2: l2-cache { 79 compatible = "cache"; 80 cache-level = <2>; 81 cache-unified; 82 }; 83 84 idle-states { 85 entry-method = "psci"; 86 87 CPU_SLEEP_0: cpu-sleep-0 { 88 compatible = "arm,idle-state"; 89 arm,psci-suspend-param = <0x40000000>; 90 local-timer-stop; 91 entry-latency-us = <300>; 92 exit-latency-us = <600>; 93 min-residency-us = <10000>; 94 }; 95 }; 96 }; 97 98 cpu_opp_table: opp-table-cpu { 99 compatible = "operating-points-v2"; 100 opp-shared; 101 opp00 { 102 opp-hz = /bits/ 64 <1199999988>; 103 opp-microvolt = <1000000>; 104 clock-latency-ns = <500000>; 105 }; 106 opp01 { 107 opp-hz = /bits/ 64 <599999994>; 108 opp-microvolt = <1000000>; 109 clock-latency-ns = <500000>; 110 }; 111 opp02 { 112 opp-hz = /bits/ 64 <399999996>; 113 opp-microvolt = <1000000>; 114 clock-latency-ns = <500000>; 115 }; 116 opp03 { 117 opp-hz = /bits/ 64 <299999997>; 118 opp-microvolt = <1000000>; 119 clock-latency-ns = <500000>; 120 }; 121 }; 122 123 reserved-memory { 124 #address-cells = <2>; 125 #size-cells = <2>; 126 ranges; 127 128 rproc_0_fw_image: memory@3ed00000 { 129 no-map; 130 reg = <0x0 0x3ed00000 0x0 0x40000>; 131 }; 132 133 rproc_1_fw_image: memory@3ef00000 { 134 no-map; 135 reg = <0x0 0x3ef00000 0x0 0x40000>; 136 }; 137 }; 138 139 zynqmp_ipi: zynqmp-ipi { 140 bootph-all; 141 compatible = "xlnx,zynqmp-ipi-mailbox"; 142 interrupt-parent = <&gic>; 143 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 144 xlnx,ipi-id = <0>; 145 #address-cells = <2>; 146 #size-cells = <2>; 147 ranges; 148 149 ipi_mailbox_pmu1: mailbox@ff9905c0 { 150 bootph-all; 151 compatible = "xlnx,zynqmp-ipi-dest-mailbox"; 152 reg = <0x0 0xff9905c0 0x0 0x20>, 153 <0x0 0xff9905e0 0x0 0x20>, 154 <0x0 0xff990e80 0x0 0x20>, 155 <0x0 0xff990ea0 0x0 0x20>; 156 reg-names = "local_request_region", 157 "local_response_region", 158 "remote_request_region", 159 "remote_response_region"; 160 #mbox-cells = <1>; 161 xlnx,ipi-id = <4>; 162 }; 163 }; 164 165 dcc: dcc { 166 compatible = "arm,dcc"; 167 status = "disabled"; 168 bootph-all; 169 }; 170 171 pmu { 172 compatible = "arm,armv8-pmuv3"; 173 interrupt-parent = <&gic>; 174 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 178 interrupt-affinity = <&cpu0>, 179 <&cpu1>, 180 <&cpu2>, 181 <&cpu3>; 182 }; 183 184 psci { 185 compatible = "arm,psci-0.2"; 186 method = "smc"; 187 }; 188 189 firmware { 190 optee: optee { 191 compatible = "linaro,optee-tz"; 192 method = "smc"; 193 }; 194 195 zynqmp_firmware: zynqmp-firmware { 196 compatible = "xlnx,zynqmp-firmware"; 197 #power-domain-cells = <1>; 198 method = "smc"; 199 bootph-all; 200 201 zynqmp_power: power-management { 202 bootph-all; 203 compatible = "xlnx,zynqmp-power"; 204 interrupt-parent = <&gic>; 205 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 206 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; 207 mbox-names = "tx", "rx"; 208 }; 209 210 nvmem-firmware { 211 compatible = "xlnx,zynqmp-nvmem-fw"; 212 #address-cells = <1>; 213 #size-cells = <1>; 214 215 soc_revision: soc-revision@0 { 216 reg = <0x0 0x4>; 217 }; 218 }; 219 220 zynqmp_pcap: pcap { 221 compatible = "xlnx,zynqmp-pcap-fpga"; 222 }; 223 224 xlnx_aes: zynqmp-aes { 225 compatible = "xlnx,zynqmp-aes"; 226 }; 227 228 zynqmp_reset: reset-controller { 229 compatible = "xlnx,zynqmp-reset"; 230 #reset-cells = <1>; 231 }; 232 233 pinctrl0: pinctrl { 234 compatible = "xlnx,zynqmp-pinctrl"; 235 status = "disabled"; 236 }; 237 238 modepin_gpio: gpio { 239 compatible = "xlnx,zynqmp-gpio-modepin"; 240 gpio-controller; 241 #gpio-cells = <2>; 242 }; 243 }; 244 }; 245 246 timer { 247 compatible = "arm,armv8-timer"; 248 interrupt-parent = <&gic>; 249 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 250 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 251 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 252 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 253 }; 254 255 fpga_full: fpga-full { 256 compatible = "fpga-region"; 257 fpga-mgr = <&zynqmp_pcap>; 258 #address-cells = <2>; 259 #size-cells = <2>; 260 ranges; 261 }; 262 263 remoteproc { 264 compatible = "xlnx,zynqmp-r5fss"; 265 xlnx,cluster-mode = <1>; 266 267 r5f-0 { 268 compatible = "xlnx,zynqmp-r5f"; 269 power-domains = <&zynqmp_firmware PD_RPU_0>; 270 memory-region = <&rproc_0_fw_image>; 271 }; 272 273 r5f-1 { 274 compatible = "xlnx,zynqmp-r5f"; 275 power-domains = <&zynqmp_firmware PD_RPU_1>; 276 memory-region = <&rproc_1_fw_image>; 277 }; 278 }; 279 280 amba: axi { 281 compatible = "simple-bus"; 282 bootph-all; 283 #address-cells = <2>; 284 #size-cells = <2>; 285 ranges; 286 287 can0: can@ff060000 { 288 compatible = "xlnx,zynq-can-1.0"; 289 status = "disabled"; 290 clock-names = "can_clk", "pclk"; 291 reg = <0x0 0xff060000 0x0 0x1000>; 292 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 293 interrupt-parent = <&gic>; 294 tx-fifo-depth = <0x40>; 295 rx-fifo-depth = <0x40>; 296 resets = <&zynqmp_reset ZYNQMP_RESET_CAN0>; 297 power-domains = <&zynqmp_firmware PD_CAN_0>; 298 }; 299 300 can1: can@ff070000 { 301 compatible = "xlnx,zynq-can-1.0"; 302 status = "disabled"; 303 clock-names = "can_clk", "pclk"; 304 reg = <0x0 0xff070000 0x0 0x1000>; 305 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 306 interrupt-parent = <&gic>; 307 tx-fifo-depth = <0x40>; 308 rx-fifo-depth = <0x40>; 309 resets = <&zynqmp_reset ZYNQMP_RESET_CAN1>; 310 power-domains = <&zynqmp_firmware PD_CAN_1>; 311 }; 312 313 cci: cci@fd6e0000 { 314 compatible = "arm,cci-400"; 315 status = "disabled"; 316 reg = <0x0 0xfd6e0000 0x0 0x9000>; 317 ranges = <0x0 0x0 0xfd6e0000 0x10000>; 318 #address-cells = <1>; 319 #size-cells = <1>; 320 321 pmu@9000 { 322 compatible = "arm,cci-400-pmu,r1"; 323 reg = <0x9000 0x5000>; 324 interrupt-parent = <&gic>; 325 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 330 }; 331 }; 332 333 /* GDMA */ 334 fpd_dma_chan1: dma-controller@fd500000 { 335 status = "disabled"; 336 compatible = "xlnx,zynqmp-dma-1.0"; 337 reg = <0x0 0xfd500000 0x0 0x1000>; 338 interrupt-parent = <&gic>; 339 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 340 clock-names = "clk_main", "clk_apb"; 341 #dma-cells = <1>; 342 xlnx,bus-width = <128>; 343 /* iommus = <&smmu 0x14e8>; */ 344 power-domains = <&zynqmp_firmware PD_GDMA>; 345 }; 346 347 fpd_dma_chan2: dma-controller@fd510000 { 348 status = "disabled"; 349 compatible = "xlnx,zynqmp-dma-1.0"; 350 reg = <0x0 0xfd510000 0x0 0x1000>; 351 interrupt-parent = <&gic>; 352 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 353 clock-names = "clk_main", "clk_apb"; 354 #dma-cells = <1>; 355 xlnx,bus-width = <128>; 356 /* iommus = <&smmu 0x14e9>; */ 357 power-domains = <&zynqmp_firmware PD_GDMA>; 358 }; 359 360 fpd_dma_chan3: dma-controller@fd520000 { 361 status = "disabled"; 362 compatible = "xlnx,zynqmp-dma-1.0"; 363 reg = <0x0 0xfd520000 0x0 0x1000>; 364 interrupt-parent = <&gic>; 365 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 366 clock-names = "clk_main", "clk_apb"; 367 #dma-cells = <1>; 368 xlnx,bus-width = <128>; 369 /* iommus = <&smmu 0x14ea>; */ 370 power-domains = <&zynqmp_firmware PD_GDMA>; 371 }; 372 373 fpd_dma_chan4: dma-controller@fd530000 { 374 status = "disabled"; 375 compatible = "xlnx,zynqmp-dma-1.0"; 376 reg = <0x0 0xfd530000 0x0 0x1000>; 377 interrupt-parent = <&gic>; 378 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 379 clock-names = "clk_main", "clk_apb"; 380 #dma-cells = <1>; 381 xlnx,bus-width = <128>; 382 /* iommus = <&smmu 0x14eb>; */ 383 power-domains = <&zynqmp_firmware PD_GDMA>; 384 }; 385 386 fpd_dma_chan5: dma-controller@fd540000 { 387 status = "disabled"; 388 compatible = "xlnx,zynqmp-dma-1.0"; 389 reg = <0x0 0xfd540000 0x0 0x1000>; 390 interrupt-parent = <&gic>; 391 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 392 clock-names = "clk_main", "clk_apb"; 393 #dma-cells = <1>; 394 xlnx,bus-width = <128>; 395 /* iommus = <&smmu 0x14ec>; */ 396 power-domains = <&zynqmp_firmware PD_GDMA>; 397 }; 398 399 fpd_dma_chan6: dma-controller@fd550000 { 400 status = "disabled"; 401 compatible = "xlnx,zynqmp-dma-1.0"; 402 reg = <0x0 0xfd550000 0x0 0x1000>; 403 interrupt-parent = <&gic>; 404 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 405 clock-names = "clk_main", "clk_apb"; 406 #dma-cells = <1>; 407 xlnx,bus-width = <128>; 408 /* iommus = <&smmu 0x14ed>; */ 409 power-domains = <&zynqmp_firmware PD_GDMA>; 410 }; 411 412 fpd_dma_chan7: dma-controller@fd560000 { 413 status = "disabled"; 414 compatible = "xlnx,zynqmp-dma-1.0"; 415 reg = <0x0 0xfd560000 0x0 0x1000>; 416 interrupt-parent = <&gic>; 417 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 418 clock-names = "clk_main", "clk_apb"; 419 #dma-cells = <1>; 420 xlnx,bus-width = <128>; 421 /* iommus = <&smmu 0x14ee>; */ 422 power-domains = <&zynqmp_firmware PD_GDMA>; 423 }; 424 425 fpd_dma_chan8: dma-controller@fd570000 { 426 status = "disabled"; 427 compatible = "xlnx,zynqmp-dma-1.0"; 428 reg = <0x0 0xfd570000 0x0 0x1000>; 429 interrupt-parent = <&gic>; 430 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 431 clock-names = "clk_main", "clk_apb"; 432 #dma-cells = <1>; 433 xlnx,bus-width = <128>; 434 /* iommus = <&smmu 0x14ef>; */ 435 power-domains = <&zynqmp_firmware PD_GDMA>; 436 }; 437 438 gic: interrupt-controller@f9010000 { 439 compatible = "arm,gic-400"; 440 #interrupt-cells = <3>; 441 reg = <0x0 0xf9010000 0x0 0x10000>, 442 <0x0 0xf9020000 0x0 0x20000>, 443 <0x0 0xf9040000 0x0 0x20000>, 444 <0x0 0xf9060000 0x0 0x20000>; 445 interrupt-controller; 446 interrupt-parent = <&gic>; 447 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 448 }; 449 450 gpu: gpu@fd4b0000 { 451 status = "disabled"; 452 compatible = "xlnx,zynqmp-mali", "arm,mali-400"; 453 reg = <0x0 0xfd4b0000 0x0 0x10000>; 454 interrupt-parent = <&gic>; 455 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 461 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1"; 462 clock-names = "bus", "core"; 463 power-domains = <&zynqmp_firmware PD_GPU>; 464 }; 465 466 /* LPDDMA default allows only secured access. inorder to enable 467 * These dma channels, Users should ensure that these dma 468 * Channels are allowed for non secure access. 469 */ 470 lpd_dma_chan1: dma-controller@ffa80000 { 471 status = "disabled"; 472 compatible = "xlnx,zynqmp-dma-1.0"; 473 reg = <0x0 0xffa80000 0x0 0x1000>; 474 interrupt-parent = <&gic>; 475 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 476 clock-names = "clk_main", "clk_apb"; 477 #dma-cells = <1>; 478 xlnx,bus-width = <64>; 479 /* iommus = <&smmu 0x868>; */ 480 power-domains = <&zynqmp_firmware PD_ADMA>; 481 }; 482 483 lpd_dma_chan2: dma-controller@ffa90000 { 484 status = "disabled"; 485 compatible = "xlnx,zynqmp-dma-1.0"; 486 reg = <0x0 0xffa90000 0x0 0x1000>; 487 interrupt-parent = <&gic>; 488 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 489 clock-names = "clk_main", "clk_apb"; 490 #dma-cells = <1>; 491 xlnx,bus-width = <64>; 492 /* iommus = <&smmu 0x869>; */ 493 power-domains = <&zynqmp_firmware PD_ADMA>; 494 }; 495 496 lpd_dma_chan3: dma-controller@ffaa0000 { 497 status = "disabled"; 498 compatible = "xlnx,zynqmp-dma-1.0"; 499 reg = <0x0 0xffaa0000 0x0 0x1000>; 500 interrupt-parent = <&gic>; 501 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 502 clock-names = "clk_main", "clk_apb"; 503 #dma-cells = <1>; 504 xlnx,bus-width = <64>; 505 /* iommus = <&smmu 0x86a>; */ 506 power-domains = <&zynqmp_firmware PD_ADMA>; 507 }; 508 509 lpd_dma_chan4: dma-controller@ffab0000 { 510 status = "disabled"; 511 compatible = "xlnx,zynqmp-dma-1.0"; 512 reg = <0x0 0xffab0000 0x0 0x1000>; 513 interrupt-parent = <&gic>; 514 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 515 clock-names = "clk_main", "clk_apb"; 516 #dma-cells = <1>; 517 xlnx,bus-width = <64>; 518 /* iommus = <&smmu 0x86b>; */ 519 power-domains = <&zynqmp_firmware PD_ADMA>; 520 }; 521 522 lpd_dma_chan5: dma-controller@ffac0000 { 523 status = "disabled"; 524 compatible = "xlnx,zynqmp-dma-1.0"; 525 reg = <0x0 0xffac0000 0x0 0x1000>; 526 interrupt-parent = <&gic>; 527 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 528 clock-names = "clk_main", "clk_apb"; 529 #dma-cells = <1>; 530 xlnx,bus-width = <64>; 531 /* iommus = <&smmu 0x86c>; */ 532 power-domains = <&zynqmp_firmware PD_ADMA>; 533 }; 534 535 lpd_dma_chan6: dma-controller@ffad0000 { 536 status = "disabled"; 537 compatible = "xlnx,zynqmp-dma-1.0"; 538 reg = <0x0 0xffad0000 0x0 0x1000>; 539 interrupt-parent = <&gic>; 540 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 541 clock-names = "clk_main", "clk_apb"; 542 #dma-cells = <1>; 543 xlnx,bus-width = <64>; 544 /* iommus = <&smmu 0x86d>; */ 545 power-domains = <&zynqmp_firmware PD_ADMA>; 546 }; 547 548 lpd_dma_chan7: dma-controller@ffae0000 { 549 status = "disabled"; 550 compatible = "xlnx,zynqmp-dma-1.0"; 551 reg = <0x0 0xffae0000 0x0 0x1000>; 552 interrupt-parent = <&gic>; 553 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 554 clock-names = "clk_main", "clk_apb"; 555 #dma-cells = <1>; 556 xlnx,bus-width = <64>; 557 /* iommus = <&smmu 0x86e>; */ 558 power-domains = <&zynqmp_firmware PD_ADMA>; 559 }; 560 561 lpd_dma_chan8: dma-controller@ffaf0000 { 562 status = "disabled"; 563 compatible = "xlnx,zynqmp-dma-1.0"; 564 reg = <0x0 0xffaf0000 0x0 0x1000>; 565 interrupt-parent = <&gic>; 566 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 567 clock-names = "clk_main", "clk_apb"; 568 #dma-cells = <1>; 569 xlnx,bus-width = <64>; 570 /* iommus = <&smmu 0x86f>; */ 571 power-domains = <&zynqmp_firmware PD_ADMA>; 572 }; 573 574 mc: memory-controller@fd070000 { 575 compatible = "xlnx,zynqmp-ddrc-2.40a"; 576 reg = <0x0 0xfd070000 0x0 0x30000>; 577 interrupt-parent = <&gic>; 578 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 579 }; 580 581 nand0: nand-controller@ff100000 { 582 compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10"; 583 status = "disabled"; 584 reg = <0x0 0xff100000 0x0 0x1000>; 585 clock-names = "controller", "bus"; 586 interrupt-parent = <&gic>; 587 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 588 #address-cells = <1>; 589 #size-cells = <0>; 590 /* iommus = <&smmu 0x872>; */ 591 power-domains = <&zynqmp_firmware PD_NAND>; 592 }; 593 594 gem0: ethernet@ff0b0000 { 595 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 596 status = "disabled"; 597 interrupt-parent = <&gic>; 598 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 600 reg = <0x0 0xff0b0000 0x0 0x1000>; 601 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 602 /* iommus = <&smmu 0x874>; */ 603 power-domains = <&zynqmp_firmware PD_ETH_0>; 604 resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; 605 reset-names = "gem0_rst"; 606 }; 607 608 gem1: ethernet@ff0c0000 { 609 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 610 status = "disabled"; 611 interrupt-parent = <&gic>; 612 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 614 reg = <0x0 0xff0c0000 0x0 0x1000>; 615 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 616 /* iommus = <&smmu 0x875>; */ 617 power-domains = <&zynqmp_firmware PD_ETH_1>; 618 resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; 619 reset-names = "gem1_rst"; 620 }; 621 622 gem2: ethernet@ff0d0000 { 623 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 624 status = "disabled"; 625 interrupt-parent = <&gic>; 626 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 628 reg = <0x0 0xff0d0000 0x0 0x1000>; 629 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 630 /* iommus = <&smmu 0x876>; */ 631 power-domains = <&zynqmp_firmware PD_ETH_2>; 632 resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; 633 reset-names = "gem2_rst"; 634 }; 635 636 gem3: ethernet@ff0e0000 { 637 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 638 status = "disabled"; 639 interrupt-parent = <&gic>; 640 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 642 reg = <0x0 0xff0e0000 0x0 0x1000>; 643 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 644 /* iommus = <&smmu 0x877>; */ 645 power-domains = <&zynqmp_firmware PD_ETH_3>; 646 resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>; 647 reset-names = "gem3_rst"; 648 }; 649 650 gpio: gpio@ff0a0000 { 651 compatible = "xlnx,zynqmp-gpio-1.0"; 652 status = "disabled"; 653 #gpio-cells = <0x2>; 654 gpio-controller; 655 interrupt-parent = <&gic>; 656 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 657 interrupt-controller; 658 #interrupt-cells = <2>; 659 reg = <0x0 0xff0a0000 0x0 0x1000>; 660 power-domains = <&zynqmp_firmware PD_GPIO>; 661 }; 662 663 i2c0: i2c@ff020000 { 664 compatible = "cdns,i2c-r1p14"; 665 status = "disabled"; 666 interrupt-parent = <&gic>; 667 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 668 clock-frequency = <400000>; 669 reg = <0x0 0xff020000 0x0 0x1000>; 670 #address-cells = <1>; 671 #size-cells = <0>; 672 power-domains = <&zynqmp_firmware PD_I2C_0>; 673 }; 674 675 i2c1: i2c@ff030000 { 676 compatible = "cdns,i2c-r1p14"; 677 status = "disabled"; 678 interrupt-parent = <&gic>; 679 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 680 clock-frequency = <400000>; 681 reg = <0x0 0xff030000 0x0 0x1000>; 682 #address-cells = <1>; 683 #size-cells = <0>; 684 power-domains = <&zynqmp_firmware PD_I2C_1>; 685 }; 686 687 pcie: pcie@fd0e0000 { 688 compatible = "xlnx,nwl-pcie-2.11"; 689 status = "disabled"; 690 #address-cells = <3>; 691 #size-cells = <2>; 692 #interrupt-cells = <1>; 693 msi-controller; 694 device_type = "pci"; 695 interrupt-parent = <&gic>; 696 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, /* MSI_1 [63...32] */ 700 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; /* MSI_0 [31...0] */ 701 interrupt-names = "misc", "dummy", "intx", 702 "msi1", "msi0"; 703 msi-parent = <&pcie>; 704 reg = <0x0 0xfd0e0000 0x0 0x1000>, 705 <0x0 0xfd480000 0x0 0x1000>, 706 <0x80 0x00000000 0x0 0x10000000>; 707 reg-names = "breg", "pcireg", "cfg"; 708 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */ 709 <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ 710 bus-range = <0x00 0xff>; 711 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 712 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, 713 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, 714 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, 715 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; 716 /* iommus = <&smmu 0x4d0>; */ 717 power-domains = <&zynqmp_firmware PD_PCIE>; 718 pcie_intc: legacy-interrupt-controller { 719 interrupt-controller; 720 #address-cells = <0>; 721 #interrupt-cells = <1>; 722 }; 723 }; 724 725 qspi: spi@ff0f0000 { 726 bootph-all; 727 compatible = "xlnx,zynqmp-qspi-1.0"; 728 status = "disabled"; 729 clock-names = "ref_clk", "pclk"; 730 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 731 interrupt-parent = <&gic>; 732 num-cs = <1>; 733 reg = <0x0 0xff0f0000 0x0 0x1000>, 734 <0x0 0xc0000000 0x0 0x8000000>; 735 #address-cells = <1>; 736 #size-cells = <0>; 737 /* iommus = <&smmu 0x873>; */ 738 power-domains = <&zynqmp_firmware PD_QSPI>; 739 }; 740 741 psgtr: phy@fd400000 { 742 compatible = "xlnx,zynqmp-psgtr-v1.1"; 743 status = "disabled"; 744 reg = <0x0 0xfd400000 0x0 0x40000>, 745 <0x0 0xfd3d0000 0x0 0x1000>; 746 reg-names = "serdes", "siou"; 747 #phy-cells = <4>; 748 }; 749 750 rtc: rtc@ffa60000 { 751 compatible = "xlnx,zynqmp-rtc"; 752 status = "disabled"; 753 reg = <0x0 0xffa60000 0x0 0x100>; 754 interrupt-parent = <&gic>; 755 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 757 interrupt-names = "alarm", "sec"; 758 calibration = <0x7FFF>; 759 }; 760 761 sata: ahci@fd0c0000 { 762 compatible = "ceva,ahci-1v84"; 763 status = "disabled"; 764 reg = <0x0 0xfd0c0000 0x0 0x2000>; 765 interrupt-parent = <&gic>; 766 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 767 power-domains = <&zynqmp_firmware PD_SATA>; 768 resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; 769 /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; */ 770 }; 771 772 sdhci0: mmc@ff160000 { 773 bootph-all; 774 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 775 status = "disabled"; 776 interrupt-parent = <&gic>; 777 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 778 reg = <0x0 0xff160000 0x0 0x1000>; 779 clock-names = "clk_xin", "clk_ahb"; 780 /* iommus = <&smmu 0x870>; */ 781 #clock-cells = <1>; 782 clock-output-names = "clk_out_sd0", "clk_in_sd0"; 783 power-domains = <&zynqmp_firmware PD_SD_0>; 784 resets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>; 785 }; 786 787 sdhci1: mmc@ff170000 { 788 bootph-all; 789 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 790 status = "disabled"; 791 interrupt-parent = <&gic>; 792 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 793 reg = <0x0 0xff170000 0x0 0x1000>; 794 clock-names = "clk_xin", "clk_ahb"; 795 /* iommus = <&smmu 0x871>; */ 796 #clock-cells = <1>; 797 clock-output-names = "clk_out_sd1", "clk_in_sd1"; 798 power-domains = <&zynqmp_firmware PD_SD_1>; 799 resets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>; 800 }; 801 802 smmu: iommu@fd800000 { 803 compatible = "arm,mmu-500"; 804 reg = <0x0 0xfd800000 0x0 0x20000>; 805 #iommu-cells = <1>; 806 status = "disabled"; 807 #global-interrupts = <1>; 808 interrupt-parent = <&gic>; 809 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 810 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 816 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 817 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 818 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 819 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 821 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 822 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 826 }; 827 828 spi0: spi@ff040000 { 829 compatible = "cdns,spi-r1p6"; 830 status = "disabled"; 831 interrupt-parent = <&gic>; 832 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 833 reg = <0x0 0xff040000 0x0 0x1000>; 834 clock-names = "ref_clk", "pclk"; 835 #address-cells = <1>; 836 #size-cells = <0>; 837 power-domains = <&zynqmp_firmware PD_SPI_0>; 838 }; 839 840 spi1: spi@ff050000 { 841 compatible = "cdns,spi-r1p6"; 842 status = "disabled"; 843 interrupt-parent = <&gic>; 844 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 845 reg = <0x0 0xff050000 0x0 0x1000>; 846 clock-names = "ref_clk", "pclk"; 847 #address-cells = <1>; 848 #size-cells = <0>; 849 power-domains = <&zynqmp_firmware PD_SPI_1>; 850 }; 851 852 ttc0: timer@ff110000 { 853 compatible = "cdns,ttc"; 854 status = "disabled"; 855 interrupt-parent = <&gic>; 856 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 859 reg = <0x0 0xff110000 0x0 0x1000>; 860 timer-width = <32>; 861 power-domains = <&zynqmp_firmware PD_TTC_0>; 862 }; 863 864 ttc1: timer@ff120000 { 865 compatible = "cdns,ttc"; 866 status = "disabled"; 867 interrupt-parent = <&gic>; 868 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 870 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 871 reg = <0x0 0xff120000 0x0 0x1000>; 872 timer-width = <32>; 873 power-domains = <&zynqmp_firmware PD_TTC_1>; 874 }; 875 876 ttc2: timer@ff130000 { 877 compatible = "cdns,ttc"; 878 status = "disabled"; 879 interrupt-parent = <&gic>; 880 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 883 reg = <0x0 0xff130000 0x0 0x1000>; 884 timer-width = <32>; 885 power-domains = <&zynqmp_firmware PD_TTC_2>; 886 }; 887 888 ttc3: timer@ff140000 { 889 compatible = "cdns,ttc"; 890 status = "disabled"; 891 interrupt-parent = <&gic>; 892 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 893 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 894 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 895 reg = <0x0 0xff140000 0x0 0x1000>; 896 timer-width = <32>; 897 power-domains = <&zynqmp_firmware PD_TTC_3>; 898 }; 899 900 uart0: serial@ff000000 { 901 bootph-all; 902 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; 903 status = "disabled"; 904 interrupt-parent = <&gic>; 905 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 906 reg = <0x0 0xff000000 0x0 0x1000>; 907 clock-names = "uart_clk", "pclk"; 908 power-domains = <&zynqmp_firmware PD_UART_0>; 909 }; 910 911 uart1: serial@ff010000 { 912 bootph-all; 913 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; 914 status = "disabled"; 915 interrupt-parent = <&gic>; 916 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 917 reg = <0x0 0xff010000 0x0 0x1000>; 918 clock-names = "uart_clk", "pclk"; 919 power-domains = <&zynqmp_firmware PD_UART_1>; 920 }; 921 922 usb0: usb@ff9d0000 { 923 #address-cells = <2>; 924 #size-cells = <2>; 925 status = "disabled"; 926 compatible = "xlnx,zynqmp-dwc3"; 927 reg = <0x0 0xff9d0000 0x0 0x100>; 928 clock-names = "bus_clk", "ref_clk"; 929 power-domains = <&zynqmp_firmware PD_USB_0>; 930 resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, 931 <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, 932 <&zynqmp_reset ZYNQMP_RESET_USB0_APB>; 933 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; 934 reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; 935 ranges; 936 937 dwc3_0: usb@fe200000 { 938 compatible = "snps,dwc3"; 939 status = "disabled"; 940 reg = <0x0 0xfe200000 0x0 0x40000>; 941 interrupt-parent = <&gic>; 942 interrupt-names = "host", "peripheral", "otg"; 943 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 946 clock-names = "ref"; 947 /* iommus = <&smmu 0x860>; */ 948 snps,quirk-frame-length-adjustment = <0x20>; 949 snps,resume-hs-terminations; 950 /* dma-coherent; */ 951 }; 952 }; 953 954 usb1: usb@ff9e0000 { 955 #address-cells = <2>; 956 #size-cells = <2>; 957 status = "disabled"; 958 compatible = "xlnx,zynqmp-dwc3"; 959 reg = <0x0 0xff9e0000 0x0 0x100>; 960 clock-names = "bus_clk", "ref_clk"; 961 power-domains = <&zynqmp_firmware PD_USB_1>; 962 resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, 963 <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, 964 <&zynqmp_reset ZYNQMP_RESET_USB1_APB>; 965 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; 966 ranges; 967 968 dwc3_1: usb@fe300000 { 969 compatible = "snps,dwc3"; 970 status = "disabled"; 971 reg = <0x0 0xfe300000 0x0 0x40000>; 972 interrupt-parent = <&gic>; 973 interrupt-names = "host", "peripheral", "otg"; 974 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 977 clock-names = "ref"; 978 /* iommus = <&smmu 0x861>; */ 979 snps,quirk-frame-length-adjustment = <0x20>; 980 snps,resume-hs-terminations; 981 /* dma-coherent; */ 982 }; 983 }; 984 985 watchdog0: watchdog@fd4d0000 { 986 compatible = "cdns,wdt-r1p2"; 987 status = "disabled"; 988 interrupt-parent = <&gic>; 989 interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>; 990 reg = <0x0 0xfd4d0000 0x0 0x1000>; 991 timeout-sec = <60>; 992 reset-on-timeout; 993 }; 994 995 lpd_watchdog: watchdog@ff150000 { 996 compatible = "cdns,wdt-r1p2"; 997 status = "disabled"; 998 interrupt-parent = <&gic>; 999 interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>; 1000 reg = <0x0 0xff150000 0x0 0x1000>; 1001 timeout-sec = <10>; 1002 }; 1003 1004 xilinx_ams: ams@ffa50000 { 1005 compatible = "xlnx,zynqmp-ams"; 1006 status = "disabled"; 1007 interrupt-parent = <&gic>; 1008 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1009 reg = <0x0 0xffa50000 0x0 0x800>; 1010 #address-cells = <1>; 1011 #size-cells = <1>; 1012 #io-channel-cells = <1>; 1013 ranges = <0 0 0xffa50800 0x800>; 1014 1015 ams_ps: ams-ps@0 { 1016 compatible = "xlnx,zynqmp-ams-ps"; 1017 status = "disabled"; 1018 reg = <0x0 0x400>; 1019 }; 1020 1021 ams_pl: ams-pl@400 { 1022 compatible = "xlnx,zynqmp-ams-pl"; 1023 status = "disabled"; 1024 reg = <0x400 0x400>; 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 }; 1028 }; 1029 1030 zynqmp_dpdma: dma-controller@fd4c0000 { 1031 compatible = "xlnx,zynqmp-dpdma"; 1032 status = "disabled"; 1033 reg = <0x0 0xfd4c0000 0x0 0x1000>; 1034 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1035 interrupt-parent = <&gic>; 1036 clock-names = "axi_clk"; 1037 power-domains = <&zynqmp_firmware PD_DP>; 1038 /* iommus = <&smmu 0xce4>; */ 1039 #dma-cells = <1>; 1040 }; 1041 1042 zynqmp_dpsub: display@fd4a0000 { 1043 bootph-all; 1044 compatible = "xlnx,zynqmp-dpsub-1.7"; 1045 status = "disabled"; 1046 reg = <0x0 0xfd4a0000 0x0 0x1000>, 1047 <0x0 0xfd4aa000 0x0 0x1000>, 1048 <0x0 0xfd4ab000 0x0 0x1000>, 1049 <0x0 0xfd4ac000 0x0 0x1000>; 1050 reg-names = "dp", "blend", "av_buf", "aud"; 1051 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1052 interrupt-parent = <&gic>; 1053 /* iommus = <&smmu 0xce3>; */ 1054 clock-names = "dp_apb_clk", "dp_aud_clk", 1055 "dp_vtc_pixel_clk_in"; 1056 power-domains = <&zynqmp_firmware PD_DP>; 1057 resets = <&zynqmp_reset ZYNQMP_RESET_DP>; 1058 dma-names = "vid0", "vid1", "vid2", "gfx0"; 1059 dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>, 1060 <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>, 1061 <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>, 1062 <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>; 1063 1064 ports { 1065 #address-cells = <1>; 1066 #size-cells = <0>; 1067 1068 port@0 { 1069 reg = <0>; 1070 }; 1071 port@1 { 1072 reg = <1>; 1073 }; 1074 port@2 { 1075 reg = <2>; 1076 }; 1077 port@3 { 1078 reg = <3>; 1079 }; 1080 port@4 { 1081 reg = <4>; 1082 }; 1083 port@5 { 1084 reg = <5>; 1085 }; 1086 }; 1087 }; 1088 }; 1089}; 1090