1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP 4 * 5 * (C) Copyright 2014 - 2019, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 */ 14 15#include <dt-bindings/power/xlnx-zynqmp-power.h> 16#include <dt-bindings/reset/xlnx-zynqmp-resets.h> 17 18/ { 19 compatible = "xlnx,zynqmp"; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 cpus { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 27 cpu0: cpu@0 { 28 compatible = "arm,cortex-a53"; 29 device_type = "cpu"; 30 enable-method = "psci"; 31 operating-points-v2 = <&cpu_opp_table>; 32 reg = <0x0>; 33 cpu-idle-states = <&CPU_SLEEP_0>; 34 }; 35 36 cpu1: cpu@1 { 37 compatible = "arm,cortex-a53"; 38 device_type = "cpu"; 39 enable-method = "psci"; 40 reg = <0x1>; 41 operating-points-v2 = <&cpu_opp_table>; 42 cpu-idle-states = <&CPU_SLEEP_0>; 43 }; 44 45 cpu2: cpu@2 { 46 compatible = "arm,cortex-a53"; 47 device_type = "cpu"; 48 enable-method = "psci"; 49 reg = <0x2>; 50 operating-points-v2 = <&cpu_opp_table>; 51 cpu-idle-states = <&CPU_SLEEP_0>; 52 }; 53 54 cpu3: cpu@3 { 55 compatible = "arm,cortex-a53"; 56 device_type = "cpu"; 57 enable-method = "psci"; 58 reg = <0x3>; 59 operating-points-v2 = <&cpu_opp_table>; 60 cpu-idle-states = <&CPU_SLEEP_0>; 61 }; 62 63 idle-states { 64 entry-method = "psci"; 65 66 CPU_SLEEP_0: cpu-sleep-0 { 67 compatible = "arm,idle-state"; 68 arm,psci-suspend-param = <0x40000000>; 69 local-timer-stop; 70 entry-latency-us = <300>; 71 exit-latency-us = <600>; 72 min-residency-us = <10000>; 73 }; 74 }; 75 }; 76 77 cpu_opp_table: cpu-opp-table { 78 compatible = "operating-points-v2"; 79 opp-shared; 80 opp00 { 81 opp-hz = /bits/ 64 <1199999988>; 82 opp-microvolt = <1000000>; 83 clock-latency-ns = <500000>; 84 }; 85 opp01 { 86 opp-hz = /bits/ 64 <599999994>; 87 opp-microvolt = <1000000>; 88 clock-latency-ns = <500000>; 89 }; 90 opp02 { 91 opp-hz = /bits/ 64 <399999996>; 92 opp-microvolt = <1000000>; 93 clock-latency-ns = <500000>; 94 }; 95 opp03 { 96 opp-hz = /bits/ 64 <299999997>; 97 opp-microvolt = <1000000>; 98 clock-latency-ns = <500000>; 99 }; 100 }; 101 102 zynqmp_ipi { 103 compatible = "xlnx,zynqmp-ipi-mailbox"; 104 interrupt-parent = <&gic>; 105 interrupts = <0 35 4>; 106 xlnx,ipi-id = <0>; 107 #address-cells = <2>; 108 #size-cells = <2>; 109 ranges; 110 111 ipi_mailbox_pmu1: mailbox@ff990400 { 112 reg = <0x0 0xff9905c0 0x0 0x20>, 113 <0x0 0xff9905e0 0x0 0x20>, 114 <0x0 0xff990e80 0x0 0x20>, 115 <0x0 0xff990ea0 0x0 0x20>; 116 reg-names = "local_request_region", 117 "local_response_region", 118 "remote_request_region", 119 "remote_response_region"; 120 #mbox-cells = <1>; 121 xlnx,ipi-id = <4>; 122 }; 123 }; 124 125 dcc: dcc { 126 compatible = "arm,dcc"; 127 status = "disabled"; 128 }; 129 130 pmu { 131 compatible = "arm,armv8-pmuv3"; 132 interrupt-parent = <&gic>; 133 interrupts = <0 143 4>, 134 <0 144 4>, 135 <0 145 4>, 136 <0 146 4>; 137 }; 138 139 psci { 140 compatible = "arm,psci-0.2"; 141 method = "smc"; 142 }; 143 144 firmware { 145 zynqmp_firmware: zynqmp-firmware { 146 compatible = "xlnx,zynqmp-firmware"; 147 #power-domain-cells = <1>; 148 method = "smc"; 149 150 zynqmp_power: zynqmp-power { 151 compatible = "xlnx,zynqmp-power"; 152 interrupt-parent = <&gic>; 153 interrupts = <0 35 4>; 154 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; 155 mbox-names = "tx", "rx"; 156 }; 157 158 zynqmp_clk: clock-controller { 159 #clock-cells = <1>; 160 compatible = "xlnx,zynqmp-clk"; 161 clocks = <&pss_ref_clk>, 162 <&video_clk>, 163 <&pss_alt_ref_clk>, 164 <&aux_ref_clk>, 165 <>_crx_ref_clk>; 166 clock-names = "pss_ref_clk", 167 "video_clk", 168 "pss_alt_ref_clk", 169 "aux_ref_clk", 170 "gt_crx_ref_clk"; 171 }; 172 173 nvmem_firmware { 174 compatible = "xlnx,zynqmp-nvmem-fw"; 175 #address-cells = <1>; 176 #size-cells = <1>; 177 178 soc_revision: soc_revision@0 { 179 reg = <0x0 0x4>; 180 }; 181 }; 182 183 zynqmp_pcap: pcap { 184 compatible = "xlnx,zynqmp-pcap-fpga"; 185 }; 186 187 xlnx_aes: zynqmp-aes { 188 compatible = "xlnx,zynqmp-aes"; 189 }; 190 }; 191 }; 192 193 timer { 194 compatible = "arm,armv8-timer"; 195 interrupt-parent = <&gic>; 196 interrupts = <1 13 0xf08>, 197 <1 14 0xf08>, 198 <1 11 0xf08>, 199 <1 10 0xf08>; 200 }; 201 202 fpga_full: fpga-full { 203 compatible = "fpga-region"; 204 fpga-mgr = <&zynqmp_pcap>; 205 #address-cells = <2>; 206 #size-cells = <2>; 207 ranges; 208 }; 209 210 amba: axi { 211 compatible = "simple-bus"; 212 #address-cells = <2>; 213 #size-cells = <2>; 214 ranges; 215 216 can0: can@ff060000 { 217 compatible = "xlnx,zynq-can-1.0"; 218 status = "disabled"; 219 clock-names = "can_clk", "pclk"; 220 reg = <0x0 0xff060000 0x0 0x1000>; 221 interrupts = <0 23 4>; 222 interrupt-parent = <&gic>; 223 tx-fifo-depth = <0x40>; 224 rx-fifo-depth = <0x40>; 225 power-domains = <&zynqmp_firmware PD_CAN_0>; 226 }; 227 228 can1: can@ff070000 { 229 compatible = "xlnx,zynq-can-1.0"; 230 status = "disabled"; 231 clock-names = "can_clk", "pclk"; 232 reg = <0x0 0xff070000 0x0 0x1000>; 233 interrupts = <0 24 4>; 234 interrupt-parent = <&gic>; 235 tx-fifo-depth = <0x40>; 236 rx-fifo-depth = <0x40>; 237 power-domains = <&zynqmp_firmware PD_CAN_1>; 238 }; 239 240 cci: cci@fd6e0000 { 241 compatible = "arm,cci-400"; 242 reg = <0x0 0xfd6e0000 0x0 0x9000>; 243 ranges = <0x0 0x0 0xfd6e0000 0x10000>; 244 #address-cells = <1>; 245 #size-cells = <1>; 246 247 pmu@9000 { 248 compatible = "arm,cci-400-pmu,r1"; 249 reg = <0x9000 0x5000>; 250 interrupt-parent = <&gic>; 251 interrupts = <0 123 4>, 252 <0 123 4>, 253 <0 123 4>, 254 <0 123 4>, 255 <0 123 4>; 256 }; 257 }; 258 259 /* GDMA */ 260 fpd_dma_chan1: dma@fd500000 { 261 status = "disabled"; 262 compatible = "xlnx,zynqmp-dma-1.0"; 263 reg = <0x0 0xfd500000 0x0 0x1000>; 264 interrupt-parent = <&gic>; 265 interrupts = <0 124 4>; 266 clock-names = "clk_main", "clk_apb"; 267 xlnx,bus-width = <128>; 268 power-domains = <&zynqmp_firmware PD_GDMA>; 269 }; 270 271 fpd_dma_chan2: dma@fd510000 { 272 status = "disabled"; 273 compatible = "xlnx,zynqmp-dma-1.0"; 274 reg = <0x0 0xfd510000 0x0 0x1000>; 275 interrupt-parent = <&gic>; 276 interrupts = <0 125 4>; 277 clock-names = "clk_main", "clk_apb"; 278 xlnx,bus-width = <128>; 279 power-domains = <&zynqmp_firmware PD_GDMA>; 280 }; 281 282 fpd_dma_chan3: dma@fd520000 { 283 status = "disabled"; 284 compatible = "xlnx,zynqmp-dma-1.0"; 285 reg = <0x0 0xfd520000 0x0 0x1000>; 286 interrupt-parent = <&gic>; 287 interrupts = <0 126 4>; 288 clock-names = "clk_main", "clk_apb"; 289 xlnx,bus-width = <128>; 290 power-domains = <&zynqmp_firmware PD_GDMA>; 291 }; 292 293 fpd_dma_chan4: dma@fd530000 { 294 status = "disabled"; 295 compatible = "xlnx,zynqmp-dma-1.0"; 296 reg = <0x0 0xfd530000 0x0 0x1000>; 297 interrupt-parent = <&gic>; 298 interrupts = <0 127 4>; 299 clock-names = "clk_main", "clk_apb"; 300 xlnx,bus-width = <128>; 301 power-domains = <&zynqmp_firmware PD_GDMA>; 302 }; 303 304 fpd_dma_chan5: dma@fd540000 { 305 status = "disabled"; 306 compatible = "xlnx,zynqmp-dma-1.0"; 307 reg = <0x0 0xfd540000 0x0 0x1000>; 308 interrupt-parent = <&gic>; 309 interrupts = <0 128 4>; 310 clock-names = "clk_main", "clk_apb"; 311 xlnx,bus-width = <128>; 312 power-domains = <&zynqmp_firmware PD_GDMA>; 313 }; 314 315 fpd_dma_chan6: dma@fd550000 { 316 status = "disabled"; 317 compatible = "xlnx,zynqmp-dma-1.0"; 318 reg = <0x0 0xfd550000 0x0 0x1000>; 319 interrupt-parent = <&gic>; 320 interrupts = <0 129 4>; 321 clock-names = "clk_main", "clk_apb"; 322 xlnx,bus-width = <128>; 323 power-domains = <&zynqmp_firmware PD_GDMA>; 324 }; 325 326 fpd_dma_chan7: dma@fd560000 { 327 status = "disabled"; 328 compatible = "xlnx,zynqmp-dma-1.0"; 329 reg = <0x0 0xfd560000 0x0 0x1000>; 330 interrupt-parent = <&gic>; 331 interrupts = <0 130 4>; 332 clock-names = "clk_main", "clk_apb"; 333 xlnx,bus-width = <128>; 334 power-domains = <&zynqmp_firmware PD_GDMA>; 335 }; 336 337 fpd_dma_chan8: dma@fd570000 { 338 status = "disabled"; 339 compatible = "xlnx,zynqmp-dma-1.0"; 340 reg = <0x0 0xfd570000 0x0 0x1000>; 341 interrupt-parent = <&gic>; 342 interrupts = <0 131 4>; 343 clock-names = "clk_main", "clk_apb"; 344 xlnx,bus-width = <128>; 345 power-domains = <&zynqmp_firmware PD_GDMA>; 346 }; 347 348 gic: interrupt-controller@f9010000 { 349 compatible = "arm,gic-400"; 350 #interrupt-cells = <3>; 351 reg = <0x0 0xf9010000 0x0 0x10000>, 352 <0x0 0xf9020000 0x0 0x20000>, 353 <0x0 0xf9040000 0x0 0x20000>, 354 <0x0 0xf9060000 0x0 0x20000>; 355 interrupt-controller; 356 interrupt-parent = <&gic>; 357 interrupts = <1 9 0xf04>; 358 }; 359 360 /* LPDDMA default allows only secured access. inorder to enable 361 * These dma channels, Users should ensure that these dma 362 * Channels are allowed for non secure access. 363 */ 364 lpd_dma_chan1: dma@ffa80000 { 365 status = "disabled"; 366 compatible = "xlnx,zynqmp-dma-1.0"; 367 reg = <0x0 0xffa80000 0x0 0x1000>; 368 interrupt-parent = <&gic>; 369 interrupts = <0 77 4>; 370 clock-names = "clk_main", "clk_apb"; 371 xlnx,bus-width = <64>; 372 power-domains = <&zynqmp_firmware PD_ADMA>; 373 }; 374 375 lpd_dma_chan2: dma@ffa90000 { 376 status = "disabled"; 377 compatible = "xlnx,zynqmp-dma-1.0"; 378 reg = <0x0 0xffa90000 0x0 0x1000>; 379 interrupt-parent = <&gic>; 380 interrupts = <0 78 4>; 381 clock-names = "clk_main", "clk_apb"; 382 xlnx,bus-width = <64>; 383 power-domains = <&zynqmp_firmware PD_ADMA>; 384 }; 385 386 lpd_dma_chan3: dma@ffaa0000 { 387 status = "disabled"; 388 compatible = "xlnx,zynqmp-dma-1.0"; 389 reg = <0x0 0xffaa0000 0x0 0x1000>; 390 interrupt-parent = <&gic>; 391 interrupts = <0 79 4>; 392 clock-names = "clk_main", "clk_apb"; 393 xlnx,bus-width = <64>; 394 power-domains = <&zynqmp_firmware PD_ADMA>; 395 }; 396 397 lpd_dma_chan4: dma@ffab0000 { 398 status = "disabled"; 399 compatible = "xlnx,zynqmp-dma-1.0"; 400 reg = <0x0 0xffab0000 0x0 0x1000>; 401 interrupt-parent = <&gic>; 402 interrupts = <0 80 4>; 403 clock-names = "clk_main", "clk_apb"; 404 xlnx,bus-width = <64>; 405 power-domains = <&zynqmp_firmware PD_ADMA>; 406 }; 407 408 lpd_dma_chan5: dma@ffac0000 { 409 status = "disabled"; 410 compatible = "xlnx,zynqmp-dma-1.0"; 411 reg = <0x0 0xffac0000 0x0 0x1000>; 412 interrupt-parent = <&gic>; 413 interrupts = <0 81 4>; 414 clock-names = "clk_main", "clk_apb"; 415 xlnx,bus-width = <64>; 416 power-domains = <&zynqmp_firmware PD_ADMA>; 417 }; 418 419 lpd_dma_chan6: dma@ffad0000 { 420 status = "disabled"; 421 compatible = "xlnx,zynqmp-dma-1.0"; 422 reg = <0x0 0xffad0000 0x0 0x1000>; 423 interrupt-parent = <&gic>; 424 interrupts = <0 82 4>; 425 clock-names = "clk_main", "clk_apb"; 426 xlnx,bus-width = <64>; 427 power-domains = <&zynqmp_firmware PD_ADMA>; 428 }; 429 430 lpd_dma_chan7: dma@ffae0000 { 431 status = "disabled"; 432 compatible = "xlnx,zynqmp-dma-1.0"; 433 reg = <0x0 0xffae0000 0x0 0x1000>; 434 interrupt-parent = <&gic>; 435 interrupts = <0 83 4>; 436 clock-names = "clk_main", "clk_apb"; 437 xlnx,bus-width = <64>; 438 power-domains = <&zynqmp_firmware PD_ADMA>; 439 }; 440 441 lpd_dma_chan8: dma@ffaf0000 { 442 status = "disabled"; 443 compatible = "xlnx,zynqmp-dma-1.0"; 444 reg = <0x0 0xffaf0000 0x0 0x1000>; 445 interrupt-parent = <&gic>; 446 interrupts = <0 84 4>; 447 clock-names = "clk_main", "clk_apb"; 448 xlnx,bus-width = <64>; 449 power-domains = <&zynqmp_firmware PD_ADMA>; 450 }; 451 452 mc: memory-controller@fd070000 { 453 compatible = "xlnx,zynqmp-ddrc-2.40a"; 454 reg = <0x0 0xfd070000 0x0 0x30000>; 455 interrupt-parent = <&gic>; 456 interrupts = <0 112 4>; 457 }; 458 459 gem0: ethernet@ff0b0000 { 460 compatible = "cdns,zynqmp-gem", "cdns,gem"; 461 status = "disabled"; 462 interrupt-parent = <&gic>; 463 interrupts = <0 57 4>, <0 57 4>; 464 reg = <0x0 0xff0b0000 0x0 0x1000>; 465 clock-names = "pclk", "hclk", "tx_clk"; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 power-domains = <&zynqmp_firmware PD_ETH_0>; 469 }; 470 471 gem1: ethernet@ff0c0000 { 472 compatible = "cdns,zynqmp-gem", "cdns,gem"; 473 status = "disabled"; 474 interrupt-parent = <&gic>; 475 interrupts = <0 59 4>, <0 59 4>; 476 reg = <0x0 0xff0c0000 0x0 0x1000>; 477 clock-names = "pclk", "hclk", "tx_clk"; 478 #address-cells = <1>; 479 #size-cells = <0>; 480 power-domains = <&zynqmp_firmware PD_ETH_1>; 481 }; 482 483 gem2: ethernet@ff0d0000 { 484 compatible = "cdns,zynqmp-gem", "cdns,gem"; 485 status = "disabled"; 486 interrupt-parent = <&gic>; 487 interrupts = <0 61 4>, <0 61 4>; 488 reg = <0x0 0xff0d0000 0x0 0x1000>; 489 clock-names = "pclk", "hclk", "tx_clk"; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 power-domains = <&zynqmp_firmware PD_ETH_2>; 493 }; 494 495 gem3: ethernet@ff0e0000 { 496 compatible = "cdns,zynqmp-gem", "cdns,gem"; 497 status = "disabled"; 498 interrupt-parent = <&gic>; 499 interrupts = <0 63 4>, <0 63 4>; 500 reg = <0x0 0xff0e0000 0x0 0x1000>; 501 clock-names = "pclk", "hclk", "tx_clk"; 502 #address-cells = <1>; 503 #size-cells = <0>; 504 power-domains = <&zynqmp_firmware PD_ETH_3>; 505 }; 506 507 gpio: gpio@ff0a0000 { 508 compatible = "xlnx,zynqmp-gpio-1.0"; 509 status = "disabled"; 510 #gpio-cells = <0x2>; 511 gpio-controller; 512 interrupt-parent = <&gic>; 513 interrupts = <0 16 4>; 514 interrupt-controller; 515 #interrupt-cells = <2>; 516 reg = <0x0 0xff0a0000 0x0 0x1000>; 517 power-domains = <&zynqmp_firmware PD_GPIO>; 518 }; 519 520 i2c0: i2c@ff020000 { 521 compatible = "cdns,i2c-r1p14"; 522 status = "disabled"; 523 interrupt-parent = <&gic>; 524 interrupts = <0 17 4>; 525 reg = <0x0 0xff020000 0x0 0x1000>; 526 #address-cells = <1>; 527 #size-cells = <0>; 528 power-domains = <&zynqmp_firmware PD_I2C_0>; 529 }; 530 531 i2c1: i2c@ff030000 { 532 compatible = "cdns,i2c-r1p14"; 533 status = "disabled"; 534 interrupt-parent = <&gic>; 535 interrupts = <0 18 4>; 536 reg = <0x0 0xff030000 0x0 0x1000>; 537 #address-cells = <1>; 538 #size-cells = <0>; 539 power-domains = <&zynqmp_firmware PD_I2C_1>; 540 }; 541 542 pcie: pcie@fd0e0000 { 543 compatible = "xlnx,nwl-pcie-2.11"; 544 status = "disabled"; 545 #address-cells = <3>; 546 #size-cells = <2>; 547 #interrupt-cells = <1>; 548 msi-controller; 549 device_type = "pci"; 550 interrupt-parent = <&gic>; 551 interrupts = <0 118 4>, 552 <0 117 4>, 553 <0 116 4>, 554 <0 115 4>, /* MSI_1 [63...32] */ 555 <0 114 4>; /* MSI_0 [31...0] */ 556 interrupt-names = "misc", "dummy", "intx", 557 "msi1", "msi0"; 558 msi-parent = <&pcie>; 559 reg = <0x0 0xfd0e0000 0x0 0x1000>, 560 <0x0 0xfd480000 0x0 0x1000>, 561 <0x80 0x00000000 0x0 0x1000000>; 562 reg-names = "breg", "pcireg", "cfg"; 563 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */ 564 <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ 565 bus-range = <0x00 0xff>; 566 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 567 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, 568 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, 569 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, 570 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; 571 power-domains = <&zynqmp_firmware PD_PCIE>; 572 pcie_intc: legacy-interrupt-controller { 573 interrupt-controller; 574 #address-cells = <0>; 575 #interrupt-cells = <1>; 576 }; 577 }; 578 579 psgtr: phy@fd400000 { 580 compatible = "xlnx,zynqmp-psgtr-v1.1"; 581 status = "disabled"; 582 reg = <0x0 0xfd400000 0x0 0x40000>, 583 <0x0 0xfd3d0000 0x0 0x1000>; 584 reg-names = "serdes", "siou"; 585 #phy-cells = <4>; 586 }; 587 588 rtc: rtc@ffa60000 { 589 compatible = "xlnx,zynqmp-rtc"; 590 status = "disabled"; 591 reg = <0x0 0xffa60000 0x0 0x100>; 592 interrupt-parent = <&gic>; 593 interrupts = <0 26 4>, <0 27 4>; 594 interrupt-names = "alarm", "sec"; 595 calibration = <0x8000>; 596 }; 597 598 sata: ahci@fd0c0000 { 599 compatible = "ceva,ahci-1v84"; 600 status = "disabled"; 601 reg = <0x0 0xfd0c0000 0x0 0x2000>; 602 interrupt-parent = <&gic>; 603 interrupts = <0 133 4>; 604 power-domains = <&zynqmp_firmware PD_SATA>; 605 }; 606 607 sdhci0: mmc@ff160000 { 608 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 609 status = "disabled"; 610 interrupt-parent = <&gic>; 611 interrupts = <0 48 4>; 612 reg = <0x0 0xff160000 0x0 0x1000>; 613 clock-names = "clk_xin", "clk_ahb"; 614 #clock-cells = <1>; 615 clock-output-names = "clk_out_sd0", "clk_in_sd0"; 616 power-domains = <&zynqmp_firmware PD_SD_0>; 617 }; 618 619 sdhci1: mmc@ff170000 { 620 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 621 status = "disabled"; 622 interrupt-parent = <&gic>; 623 interrupts = <0 49 4>; 624 reg = <0x0 0xff170000 0x0 0x1000>; 625 clock-names = "clk_xin", "clk_ahb"; 626 #clock-cells = <1>; 627 clock-output-names = "clk_out_sd1", "clk_in_sd1"; 628 power-domains = <&zynqmp_firmware PD_SD_1>; 629 }; 630 631 smmu: iommu@fd800000 { 632 compatible = "arm,mmu-500"; 633 reg = <0x0 0xfd800000 0x0 0x20000>; 634 status = "disabled"; 635 #global-interrupts = <1>; 636 interrupt-parent = <&gic>; 637 interrupts = <0 155 4>, 638 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 639 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 640 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 641 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; 642 }; 643 644 spi0: spi@ff040000 { 645 compatible = "cdns,spi-r1p6"; 646 status = "disabled"; 647 interrupt-parent = <&gic>; 648 interrupts = <0 19 4>; 649 reg = <0x0 0xff040000 0x0 0x1000>; 650 clock-names = "ref_clk", "pclk"; 651 #address-cells = <1>; 652 #size-cells = <0>; 653 power-domains = <&zynqmp_firmware PD_SPI_0>; 654 }; 655 656 spi1: spi@ff050000 { 657 compatible = "cdns,spi-r1p6"; 658 status = "disabled"; 659 interrupt-parent = <&gic>; 660 interrupts = <0 20 4>; 661 reg = <0x0 0xff050000 0x0 0x1000>; 662 clock-names = "ref_clk", "pclk"; 663 #address-cells = <1>; 664 #size-cells = <0>; 665 power-domains = <&zynqmp_firmware PD_SPI_1>; 666 }; 667 668 ttc0: timer@ff110000 { 669 compatible = "cdns,ttc"; 670 status = "disabled"; 671 interrupt-parent = <&gic>; 672 interrupts = <0 36 4>, <0 37 4>, <0 38 4>; 673 reg = <0x0 0xff110000 0x0 0x1000>; 674 timer-width = <32>; 675 power-domains = <&zynqmp_firmware PD_TTC_0>; 676 }; 677 678 ttc1: timer@ff120000 { 679 compatible = "cdns,ttc"; 680 status = "disabled"; 681 interrupt-parent = <&gic>; 682 interrupts = <0 39 4>, <0 40 4>, <0 41 4>; 683 reg = <0x0 0xff120000 0x0 0x1000>; 684 timer-width = <32>; 685 power-domains = <&zynqmp_firmware PD_TTC_1>; 686 }; 687 688 ttc2: timer@ff130000 { 689 compatible = "cdns,ttc"; 690 status = "disabled"; 691 interrupt-parent = <&gic>; 692 interrupts = <0 42 4>, <0 43 4>, <0 44 4>; 693 reg = <0x0 0xff130000 0x0 0x1000>; 694 timer-width = <32>; 695 power-domains = <&zynqmp_firmware PD_TTC_2>; 696 }; 697 698 ttc3: timer@ff140000 { 699 compatible = "cdns,ttc"; 700 status = "disabled"; 701 interrupt-parent = <&gic>; 702 interrupts = <0 45 4>, <0 46 4>, <0 47 4>; 703 reg = <0x0 0xff140000 0x0 0x1000>; 704 timer-width = <32>; 705 power-domains = <&zynqmp_firmware PD_TTC_3>; 706 }; 707 708 uart0: serial@ff000000 { 709 compatible = "cdns,uart-r1p12", "xlnx,xuartps"; 710 status = "disabled"; 711 interrupt-parent = <&gic>; 712 interrupts = <0 21 4>; 713 reg = <0x0 0xff000000 0x0 0x1000>; 714 clock-names = "uart_clk", "pclk"; 715 power-domains = <&zynqmp_firmware PD_UART_0>; 716 }; 717 718 uart1: serial@ff010000 { 719 compatible = "cdns,uart-r1p12", "xlnx,xuartps"; 720 status = "disabled"; 721 interrupt-parent = <&gic>; 722 interrupts = <0 22 4>; 723 reg = <0x0 0xff010000 0x0 0x1000>; 724 clock-names = "uart_clk", "pclk"; 725 power-domains = <&zynqmp_firmware PD_UART_1>; 726 }; 727 728 usb0: usb@fe200000 { 729 compatible = "snps,dwc3"; 730 status = "disabled"; 731 interrupt-parent = <&gic>; 732 interrupts = <0 65 4>; 733 reg = <0x0 0xfe200000 0x0 0x40000>; 734 clock-names = "clk_xin", "clk_ahb"; 735 power-domains = <&zynqmp_firmware PD_USB_0>; 736 }; 737 738 usb1: usb@fe300000 { 739 compatible = "snps,dwc3"; 740 status = "disabled"; 741 interrupt-parent = <&gic>; 742 interrupts = <0 70 4>; 743 reg = <0x0 0xfe300000 0x0 0x40000>; 744 clock-names = "clk_xin", "clk_ahb"; 745 power-domains = <&zynqmp_firmware PD_USB_1>; 746 }; 747 748 watchdog0: watchdog@fd4d0000 { 749 compatible = "cdns,wdt-r1p2"; 750 status = "disabled"; 751 interrupt-parent = <&gic>; 752 interrupts = <0 113 1>; 753 reg = <0x0 0xfd4d0000 0x0 0x1000>; 754 timeout-sec = <10>; 755 }; 756 }; 757}; 758