1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP ZCU111 4 * 5 * (C) Copyright 2017 - 2022, Xilinx, Inc. 6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. 7 * 8 * Michal Simek <michal.simek@amd.com> 9 */ 10 11/dts-v1/; 12 13#include "zynqmp.dtsi" 14#include "zynqmp-clk-ccf.dtsi" 15#include <dt-bindings/input/input.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 18#include <dt-bindings/phy/phy.h> 19 20/ { 21 model = "ZynqMP ZCU111 RevA"; 22 compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; 23 24 aliases { 25 ethernet0 = &gem3; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 mmc0 = &sdhci1; 29 nvmem0 = &eeprom; 30 rtc0 = &rtc; 31 serial0 = &uart0; 32 serial1 = &dcc; 33 spi0 = &qspi; 34 usb0 = &usb0; 35 }; 36 37 chosen { 38 bootargs = "earlycon"; 39 stdout-path = "serial0:115200n8"; 40 }; 41 42 memory@0 { 43 device_type = "memory"; 44 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; 45 /* Another 4GB connected to PL */ 46 }; 47 48 gpio-keys { 49 compatible = "gpio-keys"; 50 autorepeat; 51 switch-19 { 52 label = "sw19"; 53 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; 54 linux,code = <KEY_DOWN>; 55 wakeup-source; 56 autorepeat; 57 }; 58 }; 59 60 leds { 61 compatible = "gpio-leds"; 62 heartbeat-led { 63 label = "heartbeat"; 64 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; 65 linux,default-trigger = "heartbeat"; 66 }; 67 }; 68 69 ina226-u67 { 70 compatible = "iio-hwmon"; 71 io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>; 72 }; 73 ina226-u59 { 74 compatible = "iio-hwmon"; 75 io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>; 76 }; 77 ina226-u61 { 78 compatible = "iio-hwmon"; 79 io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; 80 }; 81 ina226-u60 { 82 compatible = "iio-hwmon"; 83 io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; 84 }; 85 ina226-u64 { 86 compatible = "iio-hwmon"; 87 io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; 88 }; 89 ina226-u69 { 90 compatible = "iio-hwmon"; 91 io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>; 92 }; 93 ina226-u66 { 94 compatible = "iio-hwmon"; 95 io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>; 96 }; 97 ina226-u65 { 98 compatible = "iio-hwmon"; 99 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; 100 }; 101 ina226-u63 { 102 compatible = "iio-hwmon"; 103 io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; 104 }; 105 ina226-u3 { 106 compatible = "iio-hwmon"; 107 io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>; 108 }; 109 ina226-u71 { 110 compatible = "iio-hwmon"; 111 io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>; 112 }; 113 ina226-u77 { 114 compatible = "iio-hwmon"; 115 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; 116 }; 117 ina226-u73 { 118 compatible = "iio-hwmon"; 119 io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>; 120 }; 121 ina226-u79 { 122 compatible = "iio-hwmon"; 123 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; 124 }; 125 126 /* 48MHz reference crystal */ 127 ref48: ref48M { 128 compatible = "fixed-clock"; 129 #clock-cells = <0>; 130 clock-frequency = <48000000>; 131 }; 132 133 dpcon { 134 compatible = "dp-connector"; 135 label = "P11"; 136 type = "full-size"; 137 138 port { 139 dpcon_in: endpoint { 140 remote-endpoint = <&dpsub_dp_out>; 141 }; 142 }; 143 }; 144}; 145 146&dcc { 147 status = "okay"; 148}; 149 150&fpd_dma_chan1 { 151 status = "okay"; 152}; 153 154&fpd_dma_chan2 { 155 status = "okay"; 156}; 157 158&fpd_dma_chan3 { 159 status = "okay"; 160}; 161 162&fpd_dma_chan4 { 163 status = "okay"; 164}; 165 166&fpd_dma_chan5 { 167 status = "okay"; 168}; 169 170&fpd_dma_chan6 { 171 status = "okay"; 172}; 173 174&fpd_dma_chan7 { 175 status = "okay"; 176}; 177 178&fpd_dma_chan8 { 179 status = "okay"; 180}; 181 182&gem3 { 183 status = "okay"; 184 phy-handle = <&phy0>; 185 phy-mode = "rgmii-id"; 186 pinctrl-names = "default"; 187 pinctrl-0 = <&pinctrl_gem3_default>; 188 mdio: mdio { 189 #address-cells = <1>; 190 #size-cells = <0>; 191 phy0: ethernet-phy@c { 192 #phy-cells = <1>; 193 compatible = "ethernet-phy-id2000.a231"; 194 reg = <0xc>; 195 ti,rx-internal-delay = <0x8>; 196 ti,tx-internal-delay = <0xa>; 197 ti,fifo-depth = <0x1>; 198 ti,dp83867-rxctrl-strap-quirk; 199 reset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>; 200 }; 201 }; 202}; 203 204&gpio { 205 status = "okay"; 206 pinctrl-names = "default"; 207 pinctrl-0 = <&pinctrl_gpio_default>; 208}; 209 210&gpu { 211 status = "okay"; 212}; 213 214&i2c0 { 215 status = "okay"; 216 clock-frequency = <400000>; 217 pinctrl-names = "default", "gpio"; 218 pinctrl-0 = <&pinctrl_i2c0_default>; 219 pinctrl-1 = <&pinctrl_i2c0_gpio>; 220 scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 221 sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 222 223 tca6416_u22: gpio@20 { 224 compatible = "ti,tca6416"; 225 reg = <0x20>; 226 gpio-controller; /* interrupt not connected */ 227 #gpio-cells = <2>; 228 /* 229 * IRQ not connected 230 * Lines: 231 * 0 - MAX6643_OT_B 232 * 1 - MAX6643_FANFAIL_B 233 * 2 - MIO26_PMU_INPUT_LS 234 * 4 - SFP_SI5382_INT_ALM 235 * 5 - IIC_MUX_RESET_B 236 * 6 - GEM3_EXP_RESET_B 237 * 10 - FMCP_HSPC_PRSNT_M2C_B 238 * 11 - CLK_SPI_MUX_SEL0 239 * 12 - CLK_SPI_MUX_SEL1 240 * 16 - IRPS5401_ALERT_B 241 * 17 - INA226_PMBUS_ALERT 242 * 3, 7, 13-15 - not connected 243 */ 244 }; 245 246 i2c-mux@75 { /* u23 */ 247 compatible = "nxp,pca9544"; 248 #address-cells = <1>; 249 #size-cells = <0>; 250 reg = <0x75>; 251 i2c@0 { 252 #address-cells = <1>; 253 #size-cells = <0>; 254 reg = <0>; 255 /* PS_PMBUS */ 256 /* PMBUS_ALERT done via pca9544 */ 257 u67: ina226@40 { /* u67 */ 258 compatible = "ti,ina226"; 259 #io-channel-cells = <1>; 260 label = "ina226-u67"; 261 reg = <0x40>; 262 shunt-resistor = <2000>; 263 }; 264 u59: ina226@41 { /* u59 */ 265 compatible = "ti,ina226"; 266 #io-channel-cells = <1>; 267 label = "ina226-u59"; 268 reg = <0x41>; 269 shunt-resistor = <5000>; 270 }; 271 u61: ina226@42 { /* u61 */ 272 compatible = "ti,ina226"; 273 #io-channel-cells = <1>; 274 label = "ina226-u61"; 275 reg = <0x42>; 276 shunt-resistor = <5000>; 277 }; 278 u60: ina226@43 { /* u60 */ 279 compatible = "ti,ina226"; 280 #io-channel-cells = <1>; 281 label = "ina226-u60"; 282 reg = <0x43>; 283 shunt-resistor = <5000>; 284 }; 285 u64: ina226@45 { /* u64 */ 286 compatible = "ti,ina226"; 287 #io-channel-cells = <1>; 288 label = "ina226-u64"; 289 reg = <0x45>; 290 shunt-resistor = <5000>; 291 }; 292 u69: ina226@46 { /* u69 */ 293 compatible = "ti,ina226"; 294 #io-channel-cells = <1>; 295 label = "ina226-u69"; 296 reg = <0x46>; 297 shunt-resistor = <2000>; 298 }; 299 u66: ina226@47 { /* u66 */ 300 compatible = "ti,ina226"; 301 #io-channel-cells = <1>; 302 label = "ina226-u66"; 303 reg = <0x47>; 304 shunt-resistor = <5000>; 305 }; 306 u65: ina226@48 { /* u65 */ 307 compatible = "ti,ina226"; 308 #io-channel-cells = <1>; 309 label = "ina226-u65"; 310 reg = <0x48>; 311 shunt-resistor = <5000>; 312 }; 313 u63: ina226@49 { /* u63 */ 314 compatible = "ti,ina226"; 315 #io-channel-cells = <1>; 316 label = "ina226-u63"; 317 reg = <0x49>; 318 shunt-resistor = <5000>; 319 }; 320 u3: ina226@4a { /* u3 */ 321 compatible = "ti,ina226"; 322 #io-channel-cells = <1>; 323 label = "ina226-u3"; 324 reg = <0x4a>; 325 shunt-resistor = <5000>; 326 }; 327 u71: ina226@4b { /* u71 */ 328 compatible = "ti,ina226"; 329 #io-channel-cells = <1>; 330 label = "ina226-u71"; 331 reg = <0x4b>; 332 shunt-resistor = <5000>; 333 }; 334 u77: ina226@4c { /* u77 */ 335 compatible = "ti,ina226"; 336 #io-channel-cells = <1>; 337 label = "ina226-u77"; 338 reg = <0x4c>; 339 shunt-resistor = <5000>; 340 }; 341 u73: ina226@4d { /* u73 */ 342 compatible = "ti,ina226"; 343 #io-channel-cells = <1>; 344 label = "ina226-u73"; 345 reg = <0x4d>; 346 shunt-resistor = <5000>; 347 }; 348 u79: ina226@4e { /* u79 */ 349 compatible = "ti,ina226"; 350 #io-channel-cells = <1>; 351 label = "ina226-u79"; 352 reg = <0x4e>; 353 shunt-resistor = <5000>; 354 }; 355 }; 356 i2c@1 { 357 #address-cells = <1>; 358 #size-cells = <0>; 359 reg = <1>; 360 /* NC */ 361 }; 362 i2c@2 { 363 #address-cells = <1>; 364 #size-cells = <0>; 365 reg = <2>; 366 irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */ 367 compatible = "infineon,irps5401"; 368 reg = <0x43>; 369 }; 370 irps5401_44: irps5401@44 { /* IRPS5401 - u55 */ 371 compatible = "infineon,irps5401"; 372 reg = <0x44>; 373 }; 374 irps5401_45: irps5401@45 { /* IRPS5401 - u57 */ 375 compatible = "infineon,irps5401"; 376 reg = <0x45>; 377 }; 378 /* u68 IR38064 +0 */ 379 /* u70 IR38060 +1 */ 380 /* u74 IR38060 +2 */ 381 /* u75 IR38060 +6 */ 382 /* J19 header too */ 383 384 }; 385 i2c@3 { 386 #address-cells = <1>; 387 #size-cells = <0>; 388 reg = <3>; 389 /* SYSMON */ 390 }; 391 }; 392}; 393 394&i2c1 { 395 status = "okay"; 396 clock-frequency = <400000>; 397 pinctrl-names = "default", "gpio"; 398 pinctrl-0 = <&pinctrl_i2c1_default>; 399 pinctrl-1 = <&pinctrl_i2c1_gpio>; 400 scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 401 sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 402 403 i2c-mux@74 { /* u26 */ 404 compatible = "nxp,pca9548"; 405 #address-cells = <1>; 406 #size-cells = <0>; 407 reg = <0x74>; 408 i2c@0 { 409 #address-cells = <1>; 410 #size-cells = <0>; 411 reg = <0>; 412 /* 413 * IIC_EEPROM 1kB memory which uses 256B blocks 414 * where every block has different address. 415 * 0 - 256B address 0x54 416 * 256B - 512B address 0x55 417 * 512B - 768B address 0x56 418 * 768B - 1024B address 0x57 419 */ 420 eeprom: eeprom@54 { /* u88 */ 421 compatible = "atmel,24c08"; 422 reg = <0x54>; 423 }; 424 }; 425 i2c@1 { 426 #address-cells = <1>; 427 #size-cells = <0>; 428 reg = <1>; 429 si5341: clock-generator@36 { /* SI5341 - u46 */ 430 compatible = "silabs,si5341"; 431 reg = <0x36>; 432 #clock-cells = <2>; 433 #address-cells = <1>; 434 #size-cells = <0>; 435 clocks = <&ref48>; 436 clock-names = "xtal"; 437 clock-output-names = "si5341"; 438 439 si5341_0: out@0 { 440 /* refclk0 for PS-GT, used for DP */ 441 reg = <0>; 442 always-on; 443 }; 444 si5341_2: out@2 { 445 /* refclk2 for PS-GT, used for USB3 */ 446 reg = <2>; 447 always-on; 448 }; 449 si5341_3: out@3 { 450 /* refclk3 for PS-GT, used for SATA */ 451 reg = <3>; 452 always-on; 453 }; 454 si5341_5: out@5 { 455 /* refclk5 PL CLK100 */ 456 reg = <5>; 457 always-on; 458 }; 459 si5341_6: out@6 { 460 /* refclk6 PL CLK125 */ 461 reg = <6>; 462 always-on; 463 }; 464 si5341_9: out@9 { 465 /* refclk9 used for PS_REF_CLK 33.3 MHz */ 466 reg = <9>; 467 always-on; 468 }; 469 }; 470 }; 471 i2c@2 { 472 #address-cells = <1>; 473 #size-cells = <0>; 474 reg = <2>; 475 si570_1: clock-generator@5d { /* USER SI570 - u47 */ 476 #clock-cells = <0>; 477 compatible = "silabs,si570"; 478 reg = <0x5d>; 479 temperature-stability = <50>; 480 factory-fout = <300000000>; 481 clock-frequency = <300000000>; 482 clock-output-names = "si570_user"; 483 }; 484 }; 485 i2c@3 { 486 #address-cells = <1>; 487 #size-cells = <0>; 488 reg = <3>; 489 si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ 490 #clock-cells = <0>; 491 compatible = "silabs,si570"; 492 reg = <0x5d>; 493 temperature-stability = <50>; 494 factory-fout = <156250000>; 495 clock-frequency = <156250000>; 496 clock-output-names = "si570_mgt"; 497 }; 498 }; 499 i2c@4 { 500 #address-cells = <1>; 501 #size-cells = <0>; 502 reg = <4>; 503 /* SI5382 - u48 */ 504 }; 505 i2c@5 { 506 #address-cells = <1>; 507 #size-cells = <0>; 508 reg = <5>; 509 sc18is603: spi@2f { /* sc18is602 - u93 */ 510 compatible = "nxp,sc18is603"; 511 reg = <0x2f>; 512 /* 4 gpios for CS not handled by driver */ 513 /* 514 * USB2ANY cable or 515 * LMK04208 - u90 or 516 * LMX2594 - u102 or 517 * LMX2594 - u103 or 518 * LMX2594 - u104 519 */ 520 }; 521 }; 522 i2c@6 { 523 #address-cells = <1>; 524 #size-cells = <0>; 525 reg = <6>; 526 /* FMC connector */ 527 }; 528 /* 7 NC */ 529 }; 530 531 i2c-mux@75 { 532 compatible = "nxp,pca9548"; /* u27 */ 533 #address-cells = <1>; 534 #size-cells = <0>; 535 reg = <0x75>; 536 537 i2c@0 { 538 #address-cells = <1>; 539 #size-cells = <0>; 540 reg = <0>; 541 /* FMCP_HSPC_IIC */ 542 }; 543 i2c@1 { 544 #address-cells = <1>; 545 #size-cells = <0>; 546 reg = <1>; 547 /* NC */ 548 }; 549 i2c@2 { 550 #address-cells = <1>; 551 #size-cells = <0>; 552 reg = <2>; 553 /* SYSMON */ 554 }; 555 i2c@3 { 556 #address-cells = <1>; 557 #size-cells = <0>; 558 reg = <3>; 559 /* DDR4 SODIMM */ 560 }; 561 i2c@4 { 562 #address-cells = <1>; 563 #size-cells = <0>; 564 reg = <4>; 565 /* SFP3 */ 566 }; 567 i2c@5 { 568 #address-cells = <1>; 569 #size-cells = <0>; 570 reg = <5>; 571 /* SFP2 */ 572 }; 573 i2c@6 { 574 #address-cells = <1>; 575 #size-cells = <0>; 576 reg = <6>; 577 /* SFP1 */ 578 }; 579 i2c@7 { 580 #address-cells = <1>; 581 #size-cells = <0>; 582 reg = <7>; 583 /* SFP0 */ 584 }; 585 }; 586}; 587 588&pinctrl0 { 589 status = "okay"; 590 pinctrl_i2c0_default: i2c0-default { 591 mux { 592 groups = "i2c0_3_grp"; 593 function = "i2c0"; 594 }; 595 596 conf { 597 groups = "i2c0_3_grp"; 598 bias-pull-up; 599 slew-rate = <SLEW_RATE_SLOW>; 600 power-source = <IO_STANDARD_LVCMOS18>; 601 }; 602 }; 603 604 pinctrl_i2c0_gpio: i2c0-gpio-grp { 605 mux { 606 groups = "gpio0_14_grp", "gpio0_15_grp"; 607 function = "gpio0"; 608 }; 609 610 conf { 611 groups = "gpio0_14_grp", "gpio0_15_grp"; 612 slew-rate = <SLEW_RATE_SLOW>; 613 power-source = <IO_STANDARD_LVCMOS18>; 614 }; 615 }; 616 617 pinctrl_i2c1_default: i2c1-default { 618 mux { 619 groups = "i2c1_4_grp"; 620 function = "i2c1"; 621 }; 622 623 conf { 624 groups = "i2c1_4_grp"; 625 bias-pull-up; 626 slew-rate = <SLEW_RATE_SLOW>; 627 power-source = <IO_STANDARD_LVCMOS18>; 628 }; 629 }; 630 631 pinctrl_i2c1_gpio: i2c1-gpio-grp { 632 mux { 633 groups = "gpio0_16_grp", "gpio0_17_grp"; 634 function = "gpio0"; 635 }; 636 637 conf { 638 groups = "gpio0_16_grp", "gpio0_17_grp"; 639 slew-rate = <SLEW_RATE_SLOW>; 640 power-source = <IO_STANDARD_LVCMOS18>; 641 }; 642 }; 643 644 pinctrl_uart0_default: uart0-default { 645 mux { 646 groups = "uart0_4_grp"; 647 function = "uart0"; 648 }; 649 650 conf { 651 groups = "uart0_4_grp"; 652 slew-rate = <SLEW_RATE_SLOW>; 653 power-source = <IO_STANDARD_LVCMOS18>; 654 }; 655 656 conf-rx { 657 pins = "MIO18"; 658 bias-high-impedance; 659 }; 660 661 conf-tx { 662 pins = "MIO19"; 663 bias-disable; 664 }; 665 }; 666 667 pinctrl_usb0_default: usb0-default { 668 mux { 669 groups = "usb0_0_grp"; 670 function = "usb0"; 671 }; 672 673 conf { 674 groups = "usb0_0_grp"; 675 power-source = <IO_STANDARD_LVCMOS18>; 676 }; 677 678 conf-rx { 679 pins = "MIO52", "MIO53", "MIO55"; 680 bias-high-impedance; 681 drive-strength = <12>; 682 slew-rate = <SLEW_RATE_FAST>; 683 }; 684 685 conf-tx { 686 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", 687 "MIO60", "MIO61", "MIO62", "MIO63"; 688 bias-disable; 689 drive-strength = <4>; 690 slew-rate = <SLEW_RATE_SLOW>; 691 }; 692 }; 693 694 pinctrl_gem3_default: gem3-default { 695 mux { 696 function = "ethernet3"; 697 groups = "ethernet3_0_grp"; 698 }; 699 700 conf { 701 groups = "ethernet3_0_grp"; 702 slew-rate = <SLEW_RATE_SLOW>; 703 power-source = <IO_STANDARD_LVCMOS18>; 704 }; 705 706 conf-rx { 707 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", 708 "MIO75"; 709 bias-high-impedance; 710 low-power-disable; 711 }; 712 713 conf-tx { 714 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", 715 "MIO69"; 716 bias-disable; 717 low-power-enable; 718 }; 719 720 mux-mdio { 721 function = "mdio3"; 722 groups = "mdio3_0_grp"; 723 }; 724 725 conf-mdio { 726 groups = "mdio3_0_grp"; 727 slew-rate = <SLEW_RATE_SLOW>; 728 power-source = <IO_STANDARD_LVCMOS18>; 729 bias-disable; 730 }; 731 }; 732 733 pinctrl_sdhci1_default: sdhci1-default { 734 mux { 735 groups = "sdio1_0_grp"; 736 function = "sdio1"; 737 }; 738 739 conf { 740 groups = "sdio1_0_grp"; 741 slew-rate = <SLEW_RATE_SLOW>; 742 power-source = <IO_STANDARD_LVCMOS18>; 743 bias-disable; 744 }; 745 746 mux-cd { 747 groups = "sdio1_cd_0_grp"; 748 function = "sdio1_cd"; 749 }; 750 751 conf-cd { 752 groups = "sdio1_cd_0_grp"; 753 bias-high-impedance; 754 bias-pull-up; 755 slew-rate = <SLEW_RATE_SLOW>; 756 power-source = <IO_STANDARD_LVCMOS18>; 757 }; 758 }; 759 760 pinctrl_gpio_default: gpio-default { 761 mux { 762 function = "gpio0"; 763 groups = "gpio0_22_grp", "gpio0_23_grp"; 764 }; 765 766 conf { 767 groups = "gpio0_22_grp", "gpio0_23_grp"; 768 slew-rate = <SLEW_RATE_SLOW>; 769 power-source = <IO_STANDARD_LVCMOS18>; 770 }; 771 772 mux-msp { 773 function = "gpio0"; 774 groups = "gpio0_13_grp", "gpio0_38_grp"; 775 }; 776 777 conf-msp { 778 groups = "gpio0_13_grp", "gpio0_38_grp"; 779 slew-rate = <SLEW_RATE_SLOW>; 780 power-source = <IO_STANDARD_LVCMOS18>; 781 }; 782 783 conf-pull-up { 784 pins = "MIO22"; 785 bias-pull-up; 786 }; 787 788 conf-pull-none { 789 pins = "MIO13", "MIO23", "MIO38"; 790 bias-disable; 791 }; 792 }; 793}; 794 795&psgtr { 796 status = "okay"; 797 /* nc, dp, usb3, sata */ 798 clocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>; 799 clock-names = "ref1", "ref2", "ref3"; 800}; 801 802&qspi { 803 status = "okay"; 804 flash@0 { 805 compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */ 806 #address-cells = <1>; 807 #size-cells = <1>; 808 reg = <0x0>; 809 spi-tx-bus-width = <4>; 810 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ 811 spi-max-frequency = <108000000>; /* Based on DC1 spec */ 812 }; 813}; 814 815&rtc { 816 status = "okay"; 817}; 818 819&sata { 820 status = "okay"; 821 /* SATA OOB timing settings */ 822 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 823 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 824 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 825 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 826 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 827 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 828 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 829 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 830 phy-names = "sata-phy"; 831 phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; 832}; 833 834/* SD1 with level shifter */ 835&sdhci1 { 836 status = "okay"; 837 pinctrl-names = "default"; 838 pinctrl-0 = <&pinctrl_sdhci1_default>; 839 disable-wp; 840 /* 841 * This property should be removed for supporting UHS mode 842 */ 843 no-1-8-v; 844 xlnx,mio-bank = <1>; 845}; 846 847&uart0 { 848 status = "okay"; 849 pinctrl-names = "default"; 850 pinctrl-0 = <&pinctrl_uart0_default>; 851}; 852 853/* ULPI SMSC USB3320 */ 854&usb0 { 855 status = "okay"; 856 pinctrl-names = "default"; 857 pinctrl-0 = <&pinctrl_usb0_default>; 858 phy-names = "usb3-phy"; 859 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; 860}; 861 862&dwc3_0 { 863 status = "okay"; 864 dr_mode = "host"; 865 snps,usb3_lpm_capable; 866 maximum-speed = "super-speed"; 867}; 868 869&zynqmp_dpdma { 870 status = "okay"; 871}; 872 873&zynqmp_dpsub { 874 status = "okay"; 875 phy-names = "dp-phy0", "dp-phy1"; 876 phys = <&psgtr 1 PHY_TYPE_DP 0 1>, 877 <&psgtr 0 PHY_TYPE_DP 1 1>; 878}; 879 880&out_dp { 881 dpsub_dp_out: endpoint { 882 remote-endpoint = <&dpcon_in>; 883 }; 884}; 885