xref: /linux/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts (revision e9f0878c4b2004ac19581274c1ae4c61ae3ca70e) 
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU106
4 *
5 * (C) Copyright 2016, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk.dtsi"
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/gpio/gpio.h>
16
17/ {
18	model = "ZynqMP ZCU106 RevA";
19	compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
20
21	aliases {
22		ethernet0 = &gem3;
23		i2c0 = &i2c0;
24		i2c1 = &i2c1;
25		mmc0 = &sdhci1;
26		rtc0 = &rtc;
27		serial0 = &uart0;
28		serial1 = &uart1;
29		serial2 = &dcc;
30	};
31
32	chosen {
33		bootargs = "earlycon";
34		stdout-path = "serial0:115200n8";
35	};
36
37	memory@0 {
38		device_type = "memory";
39		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
40	};
41
42	gpio-keys {
43		compatible = "gpio-keys";
44		autorepeat;
45		sw19 {
46			label = "sw19";
47			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
48			linux,code = <KEY_DOWN>;
49			gpio-key,wakeup;
50			autorepeat;
51		};
52	};
53
54	leds {
55		compatible = "gpio-leds";
56		heartbeat_led {
57			label = "heartbeat";
58			gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
59			linux,default-trigger = "heartbeat";
60		};
61	};
62};
63
64&can1 {
65	status = "okay";
66};
67
68&dcc {
69	status = "okay";
70};
71
72/* fpd_dma clk 667MHz, lpd_dma 500MHz */
73&fpd_dma_chan1 {
74	status = "okay";
75};
76
77&fpd_dma_chan2 {
78	status = "okay";
79};
80
81&fpd_dma_chan3 {
82	status = "okay";
83};
84
85&fpd_dma_chan4 {
86	status = "okay";
87};
88
89&fpd_dma_chan5 {
90	status = "okay";
91};
92
93&fpd_dma_chan6 {
94	status = "okay";
95};
96
97&fpd_dma_chan7 {
98	status = "okay";
99};
100
101&fpd_dma_chan8 {
102	status = "okay";
103};
104
105&gem3 {
106	status = "okay";
107	phy-handle = <&phy0>;
108	phy-mode = "rgmii-id";
109	phy0: phy@c {
110		reg = <0xc>;
111		ti,rx-internal-delay = <0x8>;
112		ti,tx-internal-delay = <0xa>;
113		ti,fifo-depth = <0x1>;
114	};
115};
116
117&gpio {
118	status = "okay";
119};
120
121&i2c0 {
122	status = "okay";
123	clock-frequency = <400000>;
124
125	tca6416_u97: gpio@20 {
126		compatible = "ti,tca6416";
127		reg = <0x20>;
128		gpio-controller; /* interrupt not connected */
129		#gpio-cells = <2>;
130		/*
131		 * IRQ not connected
132		 * Lines:
133		 * 0 - SFP_SI5328_INT_ALM
134		 * 1 - HDMI_SI5328_INT_ALM
135		 * 5 - IIC_MUX_RESET_B
136		 * 6 - GEM3_EXP_RESET_B
137		 * 10 - FMC_HPC0_PRSNT_M2C_B
138		 * 11 - FMC_HPC1_PRSNT_M2C_B
139		 * 2-4, 7, 12-17 - not connected
140		 */
141	};
142
143	tca6416_u61: gpio@21 {
144		compatible = "ti,tca6416";
145		reg = <0x21>;
146		gpio-controller;
147		#gpio-cells = <2>;
148		/*
149		 * IRQ not connected
150		 * Lines:
151		 * 0 - VCCPSPLL_EN
152		 * 1 - MGTRAVCC_EN
153		 * 2 - MGTRAVTT_EN
154		 * 3 - VCCPSDDRPLL_EN
155		 * 4 - MIO26_PMU_INPUT_LS
156		 * 5 - PL_PMBUS_ALERT
157		 * 6 - PS_PMBUS_ALERT
158		 * 7 - MAXIM_PMBUS_ALERT
159		 * 10 - PL_DDR4_VTERM_EN
160		 * 11 - PL_DDR4_VPP_2V5_EN
161		 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
162		 * 13 - PS_DIMM_SUSPEND_EN
163		 * 14 - PS_DDR4_VTERM_EN
164		 * 15 - PS_DDR4_VPP_2V5_EN
165		 * 16 - 17 - not connected
166		 */
167	};
168
169	i2c-mux@75 { /* u60 */
170		compatible = "nxp,pca9544";
171		#address-cells = <1>;
172		#size-cells = <0>;
173		reg = <0x75>;
174		i2c@0 {
175			#address-cells = <1>;
176			#size-cells = <0>;
177			reg = <0>;
178			/* PS_PMBUS */
179			ina226@40 { /* u76 */
180				compatible = "ti,ina226";
181				reg = <0x40>;
182				shunt-resistor = <5000>;
183			};
184			ina226@41 { /* u77 */
185				compatible = "ti,ina226";
186				reg = <0x41>;
187				shunt-resistor = <5000>;
188			};
189			ina226@42 { /* u78 */
190				compatible = "ti,ina226";
191				reg = <0x42>;
192				shunt-resistor = <5000>;
193			};
194			ina226@43 { /* u87 */
195				compatible = "ti,ina226";
196				reg = <0x43>;
197				shunt-resistor = <5000>;
198			};
199			ina226@44 { /* u85 */
200				compatible = "ti,ina226";
201				reg = <0x44>;
202				shunt-resistor = <5000>;
203			};
204			ina226@45 { /* u86 */
205				compatible = "ti,ina226";
206				reg = <0x45>;
207				shunt-resistor = <5000>;
208			};
209			ina226@46 { /* u93 */
210				compatible = "ti,ina226";
211				reg = <0x46>;
212				shunt-resistor = <5000>;
213			};
214			ina226@47 { /* u88 */
215				compatible = "ti,ina226";
216				reg = <0x47>;
217				shunt-resistor = <5000>;
218			};
219			ina226@4a { /* u15 */
220				compatible = "ti,ina226";
221				reg = <0x4a>;
222				shunt-resistor = <5000>;
223			};
224			ina226@4b { /* u92 */
225				compatible = "ti,ina226";
226				reg = <0x4b>;
227				shunt-resistor = <5000>;
228			};
229		};
230		i2c@1 {
231			#address-cells = <1>;
232			#size-cells = <0>;
233			reg = <1>;
234			/* PL_PMBUS */
235			ina226@40 { /* u79 */
236				compatible = "ti,ina226";
237				reg = <0x40>;
238				shunt-resistor = <2000>;
239			};
240			ina226@41 { /* u81 */
241				compatible = "ti,ina226";
242				reg = <0x41>;
243				shunt-resistor = <5000>;
244			};
245			ina226@42 { /* u80 */
246				compatible = "ti,ina226";
247				reg = <0x42>;
248				shunt-resistor = <5000>;
249			};
250			ina226@43 { /* u84 */
251				compatible = "ti,ina226";
252				reg = <0x43>;
253				shunt-resistor = <5000>;
254			};
255			ina226@44 { /* u16 */
256				compatible = "ti,ina226";
257				reg = <0x44>;
258				shunt-resistor = <5000>;
259			};
260			ina226@45 { /* u65 */
261				compatible = "ti,ina226";
262				reg = <0x45>;
263				shunt-resistor = <5000>;
264			};
265			ina226@46 { /* u74 */
266				compatible = "ti,ina226";
267				reg = <0x46>;
268				shunt-resistor = <5000>;
269			};
270			ina226@47 { /* u75 */
271				compatible = "ti,ina226";
272				reg = <0x47>;
273				shunt-resistor = <5000>;
274			};
275		};
276		i2c@2 {
277			#address-cells = <1>;
278			#size-cells = <0>;
279			reg = <2>;
280			/* MAXIM_PMBUS - 00 */
281			max15301@a { /* u46 */
282				compatible = "maxim,max15301";
283				reg = <0xa>;
284			};
285			max15303@b { /* u4 */
286				compatible = "maxim,max15303";
287				reg = <0xb>;
288			};
289			max15303@10 { /* u13 */
290				compatible = "maxim,max15303";
291				reg = <0x10>;
292			};
293			max15301@13 { /* u47 */
294				compatible = "maxim,max15301";
295				reg = <0x13>;
296			};
297			max15303@14 { /* u7 */
298				compatible = "maxim,max15303";
299				reg = <0x14>;
300			};
301			max15303@15 { /* u6 */
302				compatible = "maxim,max15303";
303				reg = <0x15>;
304			};
305			max15303@16 { /* u10 */
306				compatible = "maxim,max15303";
307				reg = <0x16>;
308			};
309			max15303@17 { /* u9 */
310				compatible = "maxim,max15303";
311				reg = <0x17>;
312			};
313			max15301@18 { /* u63 */
314				compatible = "maxim,max15301";
315				reg = <0x18>;
316			};
317			max15303@1a { /* u49 */
318				compatible = "maxim,max15303";
319				reg = <0x1a>;
320			};
321			max15303@1b { /* u8 */
322				compatible = "maxim,max15303";
323				reg = <0x1b>;
324			};
325			max15303@1d { /* u18 */
326				compatible = "maxim,max15303";
327				reg = <0x1d>;
328			};
329
330			max20751@72 { /* u95 */
331				compatible = "maxim,max20751";
332				reg = <0x72>;
333			};
334			max20751@73 { /* u96 */
335				compatible = "maxim,max20751";
336				reg = <0x73>;
337			};
338		};
339		/* Bus 3 is not connected */
340	};
341};
342
343&i2c1 {
344	status = "okay";
345	clock-frequency = <400000>;
346
347	/* PL i2c via PCA9306 - u45 */
348	i2c-mux@74 { /* u34 */
349		compatible = "nxp,pca9548";
350		#address-cells = <1>;
351		#size-cells = <0>;
352		reg = <0x74>;
353		i2c@0 {
354			#address-cells = <1>;
355			#size-cells = <0>;
356			reg = <0>;
357			/*
358			 * IIC_EEPROM 1kB memory which uses 256B blocks
359			 * where every block has different address.
360			 *    0 - 256B address 0x54
361			 * 256B - 512B address 0x55
362			 * 512B - 768B address 0x56
363			 * 768B - 1024B address 0x57
364			 */
365			eeprom: eeprom@54 { /* u23 */
366				compatible = "atmel,24c08";
367				reg = <0x54>;
368			};
369		};
370		i2c@1 {
371			#address-cells = <1>;
372			#size-cells = <0>;
373			reg = <1>;
374			si5341: clock-generator@36 { /* SI5341 - u69 */
375				reg = <0x36>;
376			};
377
378		};
379		i2c@2 {
380			#address-cells = <1>;
381			#size-cells = <0>;
382			reg = <2>;
383			si570_1: clock-generator@5d { /* USER SI570 - u42 */
384				#clock-cells = <0>;
385				compatible = "silabs,si570";
386				reg = <0x5d>;
387				temperature-stability = <50>;
388				factory-fout = <300000000>;
389				clock-frequency = <300000000>;
390			};
391		};
392		i2c@3 {
393			#address-cells = <1>;
394			#size-cells = <0>;
395			reg = <3>;
396			si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
397				#clock-cells = <0>;
398				compatible = "silabs,si570";
399				reg = <0x5d>;
400				temperature-stability = <50>; /* copy from zc702 */
401				factory-fout = <156250000>;
402				clock-frequency = <148500000>;
403			};
404		};
405		i2c@4 {
406			#address-cells = <1>;
407			#size-cells = <0>;
408			reg = <4>;
409			si5328: clock-generator@69 {/* SI5328 - u20 */
410				reg = <0x69>;
411			};
412		};
413		i2c@5 {
414			#address-cells = <1>;
415			#size-cells = <0>;
416			reg = <5>; /* FAN controller */
417			temp@4c {/* lm96163 - u128 */
418				compatible = "national,lm96163";
419				reg = <0x4c>;
420			};
421		};
422		/* 6 - 7 unconnected */
423	};
424
425	i2c-mux@75 {
426		compatible = "nxp,pca9548"; /* u135 */
427		#address-cells = <1>;
428		#size-cells = <0>;
429		reg = <0x75>;
430
431		i2c@0 {
432			#address-cells = <1>;
433			#size-cells = <0>;
434			reg = <0>;
435			/* HPC0_IIC */
436		};
437		i2c@1 {
438			#address-cells = <1>;
439			#size-cells = <0>;
440			reg = <1>;
441			/* HPC1_IIC */
442		};
443		i2c@2 {
444			#address-cells = <1>;
445			#size-cells = <0>;
446			reg = <2>;
447			/* SYSMON */
448		};
449		i2c@3 {
450			#address-cells = <1>;
451			#size-cells = <0>;
452			reg = <3>;
453			/* DDR4 SODIMM */
454		};
455		i2c@4 {
456			#address-cells = <1>;
457			#size-cells = <0>;
458			reg = <4>;
459			/* SEP 3 */
460		};
461		i2c@5 {
462			#address-cells = <1>;
463			#size-cells = <0>;
464			reg = <5>;
465			/* SEP 2 */
466		};
467		i2c@6 {
468			#address-cells = <1>;
469			#size-cells = <0>;
470			reg = <6>;
471			/* SEP 1 */
472		};
473		i2c@7 {
474			#address-cells = <1>;
475			#size-cells = <0>;
476			reg = <7>;
477			/* SEP 0 */
478		};
479	};
480};
481
482&rtc {
483	status = "okay";
484};
485
486&sata {
487	status = "okay";
488	/* SATA OOB timing settings */
489	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
490	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
491	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
492	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
493	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
494	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
495	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
496	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
497};
498
499/* SD1 with level shifter */
500&sdhci1 {
501	status = "okay";
502	no-1-8-v;
503};
504
505&uart0 {
506	status = "okay";
507};
508
509&uart1 {
510	status = "okay";
511};
512
513/* ULPI SMSC USB3320 */
514&usb0 {
515	status = "okay";
516};
517
518&watchdog0 {
519	status = "okay";
520};
521