xref: /linux/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts (revision e6a901a00822659181c93c86d8bbc2a17779fddc) 
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx ZynqMP ZCU104
4 *
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
7 *
8 * Michal Simek <michal.simek@amd.com>
9 */
10
11/dts-v1/;
12
13#include "zynqmp.dtsi"
14#include "zynqmp-clk-ccf.dtsi"
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17#include <dt-bindings/phy/phy.h>
18
19/ {
20	model = "ZynqMP ZCU104 RevC";
21	compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
22
23	aliases {
24		ethernet0 = &gem3;
25		i2c0 = &i2c1;
26		mmc0 = &sdhci1;
27		nvmem0 = &eeprom;
28		rtc0 = &rtc;
29		serial0 = &uart0;
30		serial1 = &uart1;
31		serial2 = &dcc;
32		spi0 = &qspi;
33		usb0 = &usb0;
34	};
35
36	chosen {
37		bootargs = "earlycon";
38		stdout-path = "serial0:115200n8";
39	};
40
41	memory@0 {
42		device_type = "memory";
43		reg = <0x0 0x0 0x0 0x80000000>;
44	};
45
46	ina226 {
47		compatible = "iio-hwmon";
48		io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;
49	};
50
51	clock_8t49n287_5: clk125 {
52		compatible = "fixed-clock";
53		#clock-cells = <0>;
54		clock-frequency = <125000000>;
55	};
56
57	clock_8t49n287_2: clk26 {
58		compatible = "fixed-clock";
59		#clock-cells = <0>;
60		clock-frequency = <26000000>;
61	};
62
63	clock_8t49n287_3: clk27 {
64		compatible = "fixed-clock";
65		#clock-cells = <0>;
66		clock-frequency = <27000000>;
67	};
68};
69
70&can1 {
71	status = "okay";
72	pinctrl-names = "default";
73	pinctrl-0 = <&pinctrl_can1_default>;
74};
75
76&dcc {
77	status = "okay";
78};
79
80&fpd_dma_chan1 {
81	status = "okay";
82};
83
84&fpd_dma_chan2 {
85	status = "okay";
86};
87
88&fpd_dma_chan3 {
89	status = "okay";
90};
91
92&fpd_dma_chan4 {
93	status = "okay";
94};
95
96&fpd_dma_chan5 {
97	status = "okay";
98};
99
100&fpd_dma_chan6 {
101	status = "okay";
102};
103
104&fpd_dma_chan7 {
105	status = "okay";
106};
107
108&fpd_dma_chan8 {
109	status = "okay";
110};
111
112&gem3 {
113	status = "okay";
114	phy-handle = <&phy0>;
115	phy-mode = "rgmii-id";
116	pinctrl-names = "default";
117	pinctrl-0 = <&pinctrl_gem3_default>;
118	mdio: mdio {
119		#address-cells = <1>;
120		#size-cells = <0>;
121		phy0: ethernet-phy@c {
122			#phy-cells = <1>;
123			compatible = "ethernet-phy-id2000.a231";
124			reg = <0xc>;
125			ti,rx-internal-delay = <0x8>;
126			ti,tx-internal-delay = <0xa>;
127			ti,fifo-depth = <0x1>;
128			ti,dp83867-rxctrl-strap-quirk;
129			reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
130		};
131	};
132};
133
134&gpio {
135	status = "okay";
136};
137
138&gpu {
139	status = "okay";
140};
141
142&i2c1 {
143	status = "okay";
144	clock-frequency = <400000>;
145	pinctrl-names = "default", "gpio";
146	pinctrl-0 = <&pinctrl_i2c1_default>;
147	pinctrl-1 = <&pinctrl_i2c1_gpio>;
148	scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
149	sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
150
151	tca6416_u97: gpio@20 {
152		compatible = "ti,tca6416";
153		reg = <0x20>;
154		gpio-controller;
155		#gpio-cells = <2>;
156		/*
157		 * IRQ not connected
158		 * Lines:
159		 * 0 - IRPS5401_ALERT_B
160		 * 1 - HDMI_8T49N241_INT_ALM
161		 * 2 - MAX6643_OT_B
162		 * 3 - MAX6643_FANFAIL_B
163		 * 5 - IIC_MUX_RESET_B
164		 * 6 - GEM3_EXP_RESET_B
165		 * 7 - FMC_LPC_PRSNT_M2C_B
166		 * 4, 10 - 17 - not connected
167		 */
168	};
169
170	/* Another connection to this bus via PL i2c via PCA9306 - u45 */
171	i2c-mux@74 { /* u34 */
172		compatible = "nxp,pca9548";
173		#address-cells = <1>;
174		#size-cells = <0>;
175		reg = <0x74>;
176		i2c@0 {
177			#address-cells = <1>;
178			#size-cells = <0>;
179			reg = <0>;
180			/*
181			 * IIC_EEPROM 1kB memory which uses 256B blocks
182			 * where every block has different address.
183			 *    0 - 256B address 0x54
184			 * 256B - 512B address 0x55
185			 * 512B - 768B address 0x56
186			 * 768B - 1024B address 0x57
187			 */
188			eeprom: eeprom@54 { /* u23 */
189				compatible = "atmel,24c08";
190				reg = <0x54>;
191				#address-cells = <1>;
192				#size-cells = <1>;
193			};
194		};
195
196		i2c@1 {
197			#address-cells = <1>;
198			#size-cells = <0>;
199			reg = <1>;
200			/* 8T49N287 - u182 */
201		};
202
203		i2c@2 {
204			#address-cells = <1>;
205			#size-cells = <0>;
206			reg = <2>;
207			irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
208				compatible = "infineon,irps5401";
209				reg = <0x43>; /* pmbus / i2c 0x13 */
210			};
211			irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
212				compatible = "infineon,irps5401";
213				reg = <0x44>; /* pmbus / i2c 0x14 */
214			};
215		};
216
217		i2c@3 {
218			#address-cells = <1>;
219			#size-cells = <0>;
220			reg = <3>;
221			u183: ina226@40 { /* u183 */
222				compatible = "ti,ina226";
223				#io-channel-cells = <1>;
224				reg = <0x40>;
225				shunt-resistor = <5000>;
226			};
227		};
228
229		i2c@5 {
230			#address-cells = <1>;
231			#size-cells = <0>;
232			reg = <5>;
233		};
234
235		i2c@7 {
236			#address-cells = <1>;
237			#size-cells = <0>;
238			reg = <7>;
239		};
240
241		/* 4, 6 not connected */
242	};
243};
244
245&pinctrl0 {
246	status = "okay";
247
248	pinctrl_can1_default: can1-default {
249		mux {
250			function = "can1";
251			groups = "can1_6_grp";
252		};
253
254		conf {
255			groups = "can1_6_grp";
256			slew-rate = <SLEW_RATE_SLOW>;
257			power-source = <IO_STANDARD_LVCMOS18>;
258			drive-strength = <12>;
259		};
260
261		conf-rx {
262			pins = "MIO25";
263			bias-high-impedance;
264		};
265
266		conf-tx {
267			pins = "MIO24";
268			bias-disable;
269		};
270	};
271
272	pinctrl_i2c1_default: i2c1-default {
273		mux {
274			groups = "i2c1_4_grp";
275			function = "i2c1";
276		};
277
278		conf {
279			groups = "i2c1_4_grp";
280			bias-pull-up;
281			slew-rate = <SLEW_RATE_SLOW>;
282			power-source = <IO_STANDARD_LVCMOS18>;
283			drive-strength = <12>;
284		};
285	};
286
287	pinctrl_i2c1_gpio: i2c1-gpio-grp {
288		mux {
289			groups = "gpio0_16_grp", "gpio0_17_grp";
290			function = "gpio0";
291		};
292
293		conf {
294			groups = "gpio0_16_grp", "gpio0_17_grp";
295			slew-rate = <SLEW_RATE_SLOW>;
296			power-source = <IO_STANDARD_LVCMOS18>;
297			drive-strength = <12>;
298		};
299	};
300
301	pinctrl_gem3_default: gem3-default {
302		mux {
303			function = "ethernet3";
304			groups = "ethernet3_0_grp";
305		};
306
307		conf {
308			groups = "ethernet3_0_grp";
309			slew-rate = <SLEW_RATE_SLOW>;
310			power-source = <IO_STANDARD_LVCMOS18>;
311			drive-strength = <12>;
312		};
313
314		conf-rx {
315			pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
316									"MIO75";
317			bias-high-impedance;
318			low-power-disable;
319		};
320
321		conf-tx {
322			pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
323									"MIO69";
324			bias-disable;
325			low-power-enable;
326		};
327
328		mux-mdio {
329			function = "mdio3";
330			groups = "mdio3_0_grp";
331		};
332
333		conf-mdio {
334			groups = "mdio3_0_grp";
335			slew-rate = <SLEW_RATE_SLOW>;
336			power-source = <IO_STANDARD_LVCMOS18>;
337			bias-disable;
338		};
339	};
340
341	pinctrl_sdhci1_default: sdhci1-default {
342		mux {
343			groups = "sdio1_0_grp";
344			function = "sdio1";
345		};
346
347		conf {
348			groups = "sdio1_0_grp";
349			slew-rate = <SLEW_RATE_SLOW>;
350			power-source = <IO_STANDARD_LVCMOS18>;
351			bias-disable;
352			drive-strength = <12>;
353		};
354
355		mux-cd {
356			groups = "sdio1_cd_0_grp";
357			function = "sdio1_cd";
358		};
359
360		conf-cd {
361			groups = "sdio1_cd_0_grp";
362			bias-high-impedance;
363			bias-pull-up;
364			slew-rate = <SLEW_RATE_SLOW>;
365			power-source = <IO_STANDARD_LVCMOS18>;
366		};
367	};
368
369	pinctrl_uart0_default: uart0-default {
370		mux {
371			groups = "uart0_4_grp";
372			function = "uart0";
373		};
374
375		conf {
376			groups = "uart0_4_grp";
377			slew-rate = <SLEW_RATE_SLOW>;
378			power-source = <IO_STANDARD_LVCMOS18>;
379			drive-strength = <12>;
380		};
381
382		conf-rx {
383			pins = "MIO18";
384			bias-high-impedance;
385		};
386
387		conf-tx {
388			pins = "MIO19";
389			bias-disable;
390		};
391	};
392
393	pinctrl_uart1_default: uart1-default {
394		mux {
395			groups = "uart1_5_grp";
396			function = "uart1";
397		};
398
399		conf {
400			groups = "uart1_5_grp";
401			slew-rate = <SLEW_RATE_SLOW>;
402			power-source = <IO_STANDARD_LVCMOS18>;
403			drive-strength = <12>;
404		};
405
406		conf-rx {
407			pins = "MIO21";
408			bias-high-impedance;
409		};
410
411		conf-tx {
412			pins = "MIO20";
413			bias-disable;
414		};
415	};
416
417	pinctrl_usb0_default: usb0-default {
418		mux {
419			groups = "usb0_0_grp";
420			function = "usb0";
421		};
422
423		conf {
424			groups = "usb0_0_grp";
425			power-source = <IO_STANDARD_LVCMOS18>;
426		};
427
428		conf-rx {
429			pins = "MIO52", "MIO53", "MIO55";
430			bias-high-impedance;
431			drive-strength = <12>;
432			slew-rate = <SLEW_RATE_FAST>;
433		};
434
435		conf-tx {
436			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
437			       "MIO60", "MIO61", "MIO62", "MIO63";
438			bias-disable;
439			drive-strength = <4>;
440			slew-rate = <SLEW_RATE_SLOW>;
441		};
442	};
443};
444
445&psgtr {
446	status = "okay";
447	/* nc, sata, usb3, dp */
448	clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
449	clock-names = "ref1", "ref2", "ref3";
450};
451
452&qspi {
453	status = "okay";
454	flash@0 {
455		compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
456		#address-cells = <1>;
457		#size-cells = <1>;
458		reg = <0x0>;
459		spi-tx-bus-width = <4>;
460		spi-rx-bus-width = <4>;
461		spi-max-frequency = <108000000>; /* Based on DC1 spec */
462	};
463};
464
465&rtc {
466	status = "okay";
467};
468
469&sata {
470	status = "okay";
471	/* SATA OOB timing settings */
472	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
473	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
474	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
475	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
476	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
477	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
478	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
479	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
480	phy-names = "sata-phy";
481	phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
482};
483
484/* SD1 with level shifter */
485&sdhci1 {
486	status = "okay";
487	no-1-8-v;
488	pinctrl-names = "default";
489	pinctrl-0 = <&pinctrl_sdhci1_default>;
490	xlnx,mio-bank = <1>;
491	disable-wp;
492};
493
494&uart0 {
495	status = "okay";
496	pinctrl-names = "default";
497	pinctrl-0 = <&pinctrl_uart0_default>;
498};
499
500&uart1 {
501	status = "okay";
502	pinctrl-names = "default";
503	pinctrl-0 = <&pinctrl_uart1_default>;
504};
505
506/* ULPI SMSC USB3320 */
507&usb0 {
508	status = "okay";
509	pinctrl-names = "default";
510	pinctrl-0 = <&pinctrl_usb0_default>;
511	phy-names = "usb3-phy";
512	phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
513};
514
515&dwc3_0 {
516	status = "okay";
517	dr_mode = "host";
518	snps,usb3_lpm_capable;
519	maximum-speed = "super-speed";
520};
521
522&watchdog0 {
523	status = "okay";
524};
525
526&xilinx_ams {
527	status = "okay";
528};
529
530&ams_ps {
531	status = "okay";
532};
533
534&ams_pl {
535	status = "okay";
536};
537
538&zynqmp_dpdma {
539	status = "okay";
540};
541
542&zynqmp_dpsub {
543	status = "okay";
544	phy-names = "dp-phy0", "dp-phy1";
545	phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
546	       <&psgtr 0 PHY_TYPE_DP 1 3>;
547};
548