xref: /linux/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts (revision db4a3f0fbedb0398f77b9047e8b8bb2b49f355bb) 
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx ZynqMP ZCU104
4 *
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
7 *
8 * Michal Simek <michal.simek@amd.com>
9 */
10
11/dts-v1/;
12
13#include "zynqmp.dtsi"
14#include "zynqmp-clk-ccf.dtsi"
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17#include <dt-bindings/phy/phy.h>
18
19/ {
20	model = "ZynqMP ZCU104 RevC";
21	compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
22
23	aliases {
24		ethernet0 = &gem3;
25		i2c0 = &i2c1;
26		mmc0 = &sdhci1;
27		nvmem0 = &eeprom;
28		rtc0 = &rtc;
29		serial0 = &uart0;
30		serial1 = &uart1;
31		serial2 = &dcc;
32		spi0 = &qspi;
33		usb0 = &usb0;
34	};
35
36	chosen {
37		bootargs = "earlycon";
38		stdout-path = "serial0:115200n8";
39	};
40
41	memory@0 {
42		device_type = "memory";
43		reg = <0x0 0x0 0x0 0x80000000>;
44	};
45
46	ina226 {
47		compatible = "iio-hwmon";
48		io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;
49	};
50
51	clock_8t49n287_5: clk125 {
52		compatible = "fixed-clock";
53		#clock-cells = <0>;
54		clock-frequency = <125000000>;
55	};
56
57	clock_8t49n287_2: clk26 {
58		compatible = "fixed-clock";
59		#clock-cells = <0>;
60		clock-frequency = <26000000>;
61	};
62
63	clock_8t49n287_3: clk27 {
64		compatible = "fixed-clock";
65		#clock-cells = <0>;
66		clock-frequency = <27000000>;
67	};
68
69	dpcon {
70		compatible = "dp-connector";
71		label = "P11";
72		type = "full-size";
73
74		port {
75			dpcon_in: endpoint {
76				remote-endpoint = <&dpsub_dp_out>;
77			};
78		};
79	};
80};
81
82&can1 {
83	status = "okay";
84	pinctrl-names = "default";
85	pinctrl-0 = <&pinctrl_can1_default>;
86};
87
88&dcc {
89	status = "okay";
90};
91
92&fpd_dma_chan1 {
93	status = "okay";
94};
95
96&fpd_dma_chan2 {
97	status = "okay";
98};
99
100&fpd_dma_chan3 {
101	status = "okay";
102};
103
104&fpd_dma_chan4 {
105	status = "okay";
106};
107
108&fpd_dma_chan5 {
109	status = "okay";
110};
111
112&fpd_dma_chan6 {
113	status = "okay";
114};
115
116&fpd_dma_chan7 {
117	status = "okay";
118};
119
120&fpd_dma_chan8 {
121	status = "okay";
122};
123
124&gem3 {
125	status = "okay";
126	phy-handle = <&phy0>;
127	phy-mode = "rgmii-id";
128	pinctrl-names = "default";
129	pinctrl-0 = <&pinctrl_gem3_default>;
130	mdio: mdio {
131		#address-cells = <1>;
132		#size-cells = <0>;
133		phy0: ethernet-phy@c {
134			#phy-cells = <1>;
135			compatible = "ethernet-phy-id2000.a231";
136			reg = <0xc>;
137			ti,rx-internal-delay = <0x8>;
138			ti,tx-internal-delay = <0xa>;
139			ti,fifo-depth = <0x1>;
140			ti,dp83867-rxctrl-strap-quirk;
141			reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
142		};
143	};
144};
145
146&gpio {
147	status = "okay";
148};
149
150&gpu {
151	status = "okay";
152};
153
154&i2c1 {
155	status = "okay";
156	clock-frequency = <400000>;
157	pinctrl-names = "default", "gpio";
158	pinctrl-0 = <&pinctrl_i2c1_default>;
159	pinctrl-1 = <&pinctrl_i2c1_gpio>;
160	scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
161	sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
162
163	tca6416_u97: gpio@20 {
164		compatible = "ti,tca6416";
165		reg = <0x20>;
166		gpio-controller;
167		#gpio-cells = <2>;
168		/*
169		 * IRQ not connected
170		 * Lines:
171		 * 0 - IRPS5401_ALERT_B
172		 * 1 - HDMI_8T49N241_INT_ALM
173		 * 2 - MAX6643_OT_B
174		 * 3 - MAX6643_FANFAIL_B
175		 * 5 - IIC_MUX_RESET_B
176		 * 6 - GEM3_EXP_RESET_B
177		 * 7 - FMC_LPC_PRSNT_M2C_B
178		 * 4, 10 - 17 - not connected
179		 */
180	};
181
182	/* Another connection to this bus via PL i2c via PCA9306 - u45 */
183	i2c-mux@74 { /* u34 */
184		compatible = "nxp,pca9548";
185		#address-cells = <1>;
186		#size-cells = <0>;
187		reg = <0x74>;
188		i2c@0 {
189			#address-cells = <1>;
190			#size-cells = <0>;
191			reg = <0>;
192			/*
193			 * IIC_EEPROM 1kB memory which uses 256B blocks
194			 * where every block has different address.
195			 *    0 - 256B address 0x54
196			 * 256B - 512B address 0x55
197			 * 512B - 768B address 0x56
198			 * 768B - 1024B address 0x57
199			 */
200			eeprom: eeprom@54 { /* u23 */
201				compatible = "atmel,24c08";
202				reg = <0x54>;
203				#address-cells = <1>;
204				#size-cells = <1>;
205			};
206		};
207
208		i2c@1 {
209			#address-cells = <1>;
210			#size-cells = <0>;
211			reg = <1>;
212			/* 8T49N287 - u182 */
213		};
214
215		i2c@2 {
216			#address-cells = <1>;
217			#size-cells = <0>;
218			reg = <2>;
219			irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
220				compatible = "infineon,irps5401";
221				reg = <0x43>; /* pmbus / i2c 0x13 */
222			};
223			irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
224				compatible = "infineon,irps5401";
225				reg = <0x44>; /* pmbus / i2c 0x14 */
226			};
227		};
228
229		i2c@3 {
230			#address-cells = <1>;
231			#size-cells = <0>;
232			reg = <3>;
233			u183: ina226@40 { /* u183 */
234				compatible = "ti,ina226";
235				#io-channel-cells = <1>;
236				reg = <0x40>;
237				shunt-resistor = <5000>;
238			};
239		};
240
241		i2c@5 {
242			#address-cells = <1>;
243			#size-cells = <0>;
244			reg = <5>;
245		};
246
247		i2c@7 {
248			#address-cells = <1>;
249			#size-cells = <0>;
250			reg = <7>;
251		};
252
253		/* 4, 6 not connected */
254	};
255};
256
257&pinctrl0 {
258	status = "okay";
259
260	pinctrl_can1_default: can1-default {
261		mux {
262			function = "can1";
263			groups = "can1_6_grp";
264		};
265
266		conf {
267			groups = "can1_6_grp";
268			slew-rate = <SLEW_RATE_SLOW>;
269			power-source = <IO_STANDARD_LVCMOS18>;
270			drive-strength = <12>;
271		};
272
273		conf-rx {
274			pins = "MIO25";
275			bias-high-impedance;
276		};
277
278		conf-tx {
279			pins = "MIO24";
280			bias-disable;
281		};
282	};
283
284	pinctrl_i2c1_default: i2c1-default {
285		mux {
286			groups = "i2c1_4_grp";
287			function = "i2c1";
288		};
289
290		conf {
291			groups = "i2c1_4_grp";
292			bias-pull-up;
293			slew-rate = <SLEW_RATE_SLOW>;
294			power-source = <IO_STANDARD_LVCMOS18>;
295			drive-strength = <12>;
296		};
297	};
298
299	pinctrl_i2c1_gpio: i2c1-gpio-grp {
300		mux {
301			groups = "gpio0_16_grp", "gpio0_17_grp";
302			function = "gpio0";
303		};
304
305		conf {
306			groups = "gpio0_16_grp", "gpio0_17_grp";
307			slew-rate = <SLEW_RATE_SLOW>;
308			power-source = <IO_STANDARD_LVCMOS18>;
309			drive-strength = <12>;
310		};
311	};
312
313	pinctrl_gem3_default: gem3-default {
314		mux {
315			function = "ethernet3";
316			groups = "ethernet3_0_grp";
317		};
318
319		conf {
320			groups = "ethernet3_0_grp";
321			slew-rate = <SLEW_RATE_SLOW>;
322			power-source = <IO_STANDARD_LVCMOS18>;
323			drive-strength = <12>;
324		};
325
326		conf-rx {
327			pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
328									"MIO75";
329			bias-high-impedance;
330			low-power-disable;
331		};
332
333		conf-tx {
334			pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
335									"MIO69";
336			bias-disable;
337			low-power-enable;
338		};
339
340		mux-mdio {
341			function = "mdio3";
342			groups = "mdio3_0_grp";
343		};
344
345		conf-mdio {
346			groups = "mdio3_0_grp";
347			slew-rate = <SLEW_RATE_SLOW>;
348			power-source = <IO_STANDARD_LVCMOS18>;
349			bias-disable;
350		};
351	};
352
353	pinctrl_sdhci1_default: sdhci1-default {
354		mux {
355			groups = "sdio1_0_grp";
356			function = "sdio1";
357		};
358
359		conf {
360			groups = "sdio1_0_grp";
361			slew-rate = <SLEW_RATE_SLOW>;
362			power-source = <IO_STANDARD_LVCMOS18>;
363			bias-disable;
364			drive-strength = <12>;
365		};
366
367		mux-cd {
368			groups = "sdio1_cd_0_grp";
369			function = "sdio1_cd";
370		};
371
372		conf-cd {
373			groups = "sdio1_cd_0_grp";
374			bias-high-impedance;
375			bias-pull-up;
376			slew-rate = <SLEW_RATE_SLOW>;
377			power-source = <IO_STANDARD_LVCMOS18>;
378		};
379	};
380
381	pinctrl_uart0_default: uart0-default {
382		mux {
383			groups = "uart0_4_grp";
384			function = "uart0";
385		};
386
387		conf {
388			groups = "uart0_4_grp";
389			slew-rate = <SLEW_RATE_SLOW>;
390			power-source = <IO_STANDARD_LVCMOS18>;
391			drive-strength = <12>;
392		};
393
394		conf-rx {
395			pins = "MIO18";
396			bias-high-impedance;
397		};
398
399		conf-tx {
400			pins = "MIO19";
401			bias-disable;
402		};
403	};
404
405	pinctrl_uart1_default: uart1-default {
406		mux {
407			groups = "uart1_5_grp";
408			function = "uart1";
409		};
410
411		conf {
412			groups = "uart1_5_grp";
413			slew-rate = <SLEW_RATE_SLOW>;
414			power-source = <IO_STANDARD_LVCMOS18>;
415			drive-strength = <12>;
416		};
417
418		conf-rx {
419			pins = "MIO21";
420			bias-high-impedance;
421		};
422
423		conf-tx {
424			pins = "MIO20";
425			bias-disable;
426		};
427	};
428
429	pinctrl_usb0_default: usb0-default {
430		mux {
431			groups = "usb0_0_grp";
432			function = "usb0";
433		};
434
435		conf {
436			groups = "usb0_0_grp";
437			power-source = <IO_STANDARD_LVCMOS18>;
438		};
439
440		conf-rx {
441			pins = "MIO52", "MIO53", "MIO55";
442			bias-high-impedance;
443			drive-strength = <12>;
444			slew-rate = <SLEW_RATE_FAST>;
445		};
446
447		conf-tx {
448			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
449			       "MIO60", "MIO61", "MIO62", "MIO63";
450			bias-disable;
451			drive-strength = <4>;
452			slew-rate = <SLEW_RATE_SLOW>;
453		};
454	};
455};
456
457&psgtr {
458	status = "okay";
459	/* nc, sata, usb3, dp */
460	clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
461	clock-names = "ref1", "ref2", "ref3";
462};
463
464&qspi {
465	status = "okay";
466	flash@0 {
467		compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
468		#address-cells = <1>;
469		#size-cells = <1>;
470		reg = <0x0>;
471		spi-tx-bus-width = <4>;
472		spi-rx-bus-width = <4>;
473		spi-max-frequency = <108000000>; /* Based on DC1 spec */
474	};
475};
476
477&rtc {
478	status = "okay";
479};
480
481&sata {
482	status = "okay";
483	/* SATA OOB timing settings */
484	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
485	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
486	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
487	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
488	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
489	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
490	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
491	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
492	phy-names = "sata-phy";
493	phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
494};
495
496/* SD1 with level shifter */
497&sdhci1 {
498	status = "okay";
499	no-1-8-v;
500	pinctrl-names = "default";
501	pinctrl-0 = <&pinctrl_sdhci1_default>;
502	xlnx,mio-bank = <1>;
503	disable-wp;
504};
505
506&uart0 {
507	status = "okay";
508	pinctrl-names = "default";
509	pinctrl-0 = <&pinctrl_uart0_default>;
510};
511
512&uart1 {
513	status = "okay";
514	pinctrl-names = "default";
515	pinctrl-0 = <&pinctrl_uart1_default>;
516};
517
518/* ULPI SMSC USB3320 */
519&usb0 {
520	status = "okay";
521	pinctrl-names = "default";
522	pinctrl-0 = <&pinctrl_usb0_default>;
523	phy-names = "usb3-phy";
524	phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
525};
526
527&dwc3_0 {
528	status = "okay";
529	dr_mode = "host";
530	snps,usb3_lpm_capable;
531	maximum-speed = "super-speed";
532};
533
534&watchdog0 {
535	status = "okay";
536};
537
538&ams_ps {
539	status = "okay";
540};
541
542&ams_pl {
543	status = "okay";
544};
545
546&zynqmp_dpdma {
547	status = "okay";
548};
549
550&zynqmp_dpsub {
551	status = "okay";
552	phy-names = "dp-phy0", "dp-phy1";
553	phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
554	       <&psgtr 0 PHY_TYPE_DP 1 3>;
555};
556
557&out_dp {
558	dpsub_dp_out: endpoint {
559		remote-endpoint = <&dpcon_in>;
560	};
561};
562