1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for Xilinx ZynqMP ZCU104 4 * 5 * (C) Copyright 2017 - 2020, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9 10/dts-v1/; 11 12#include "zynqmp.dtsi" 13#include "zynqmp-clk-ccf.dtsi" 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/phy/phy.h> 16 17/ { 18 model = "ZynqMP ZCU104 RevC"; 19 compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; 20 21 aliases { 22 ethernet0 = &gem3; 23 i2c0 = &i2c1; 24 mmc0 = &sdhci1; 25 rtc0 = &rtc; 26 serial0 = &uart0; 27 serial1 = &uart1; 28 serial2 = &dcc; 29 }; 30 31 chosen { 32 bootargs = "earlycon"; 33 stdout-path = "serial0:115200n8"; 34 }; 35 36 memory@0 { 37 device_type = "memory"; 38 reg = <0x0 0x0 0x0 0x80000000>; 39 }; 40 41 ina226 { 42 compatible = "iio-hwmon"; 43 io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>; 44 }; 45 46 clock_8t49n287_5: clk125 { 47 compatible = "fixed-clock"; 48 #clock-cells = <0>; 49 clock-frequency = <125000000>; 50 }; 51 52 clock_8t49n287_2: clk26 { 53 compatible = "fixed-clock"; 54 #clock-cells = <0>; 55 clock-frequency = <26000000>; 56 }; 57 58 clock_8t49n287_3: clk27 { 59 compatible = "fixed-clock"; 60 #clock-cells = <0>; 61 clock-frequency = <27000000>; 62 }; 63}; 64 65&can1 { 66 status = "okay"; 67}; 68 69&dcc { 70 status = "okay"; 71}; 72 73&fpd_dma_chan1 { 74 status = "okay"; 75}; 76 77&fpd_dma_chan2 { 78 status = "okay"; 79}; 80 81&fpd_dma_chan3 { 82 status = "okay"; 83}; 84 85&fpd_dma_chan4 { 86 status = "okay"; 87}; 88 89&fpd_dma_chan5 { 90 status = "okay"; 91}; 92 93&fpd_dma_chan6 { 94 status = "okay"; 95}; 96 97&fpd_dma_chan7 { 98 status = "okay"; 99}; 100 101&fpd_dma_chan8 { 102 status = "okay"; 103}; 104 105&gem3 { 106 status = "okay"; 107 phy-handle = <&phy0>; 108 phy-mode = "rgmii-id"; 109 phy0: ethernet-phy@c { 110 reg = <0xc>; 111 ti,rx-internal-delay = <0x8>; 112 ti,tx-internal-delay = <0xa>; 113 ti,fifo-depth = <0x1>; 114 ti,dp83867-rxctrl-strap-quirk; 115 }; 116}; 117 118&gpio { 119 status = "okay"; 120}; 121 122&i2c1 { 123 status = "okay"; 124 clock-frequency = <400000>; 125 126 tca6416_u97: gpio@20 { 127 compatible = "ti,tca6416"; 128 reg = <0x20>; 129 gpio-controller; 130 #gpio-cells = <2>; 131 /* 132 * IRQ not connected 133 * Lines: 134 * 0 - IRPS5401_ALERT_B 135 * 1 - HDMI_8T49N241_INT_ALM 136 * 2 - MAX6643_OT_B 137 * 3 - MAX6643_FANFAIL_B 138 * 5 - IIC_MUX_RESET_B 139 * 6 - GEM3_EXP_RESET_B 140 * 7 - FMC_LPC_PRSNT_M2C_B 141 * 4, 10 - 17 - not connected 142 */ 143 }; 144 145 /* Another connection to this bus via PL i2c via PCA9306 - u45 */ 146 i2c-mux@74 { /* u34 */ 147 compatible = "nxp,pca9548"; 148 #address-cells = <1>; 149 #size-cells = <0>; 150 reg = <0x74>; 151 i2c@0 { 152 #address-cells = <1>; 153 #size-cells = <0>; 154 reg = <0>; 155 /* 156 * IIC_EEPROM 1kB memory which uses 256B blocks 157 * where every block has different address. 158 * 0 - 256B address 0x54 159 * 256B - 512B address 0x55 160 * 512B - 768B address 0x56 161 * 768B - 1024B address 0x57 162 */ 163 eeprom: eeprom@54 { /* u23 */ 164 compatible = "atmel,24c08"; 165 reg = <0x54>; 166 #address-cells = <1>; 167 #size-cells = <1>; 168 }; 169 }; 170 171 i2c@1 { 172 #address-cells = <1>; 173 #size-cells = <0>; 174 reg = <1>; 175 clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ 176 reg = <0x6c>; 177 }; 178 }; 179 180 i2c@2 { 181 #address-cells = <1>; 182 #size-cells = <0>; 183 reg = <2>; 184 irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ 185 compatible = "infineon,irps5401"; 186 reg = <0x43>; /* pmbus / i2c 0x13 */ 187 }; 188 irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ 189 compatible = "infineon,irps5401"; 190 reg = <0x44>; /* pmbus / i2c 0x14 */ 191 }; 192 }; 193 194 i2c@3 { 195 #address-cells = <1>; 196 #size-cells = <0>; 197 reg = <3>; 198 u183: ina226@40 { /* u183 */ 199 compatible = "ti,ina226"; 200 #io-channel-cells = <1>; 201 reg = <0x40>; 202 shunt-resistor = <5000>; 203 }; 204 }; 205 206 i2c@5 { 207 #address-cells = <1>; 208 #size-cells = <0>; 209 reg = <5>; 210 }; 211 212 i2c@7 { 213 #address-cells = <1>; 214 #size-cells = <0>; 215 reg = <7>; 216 }; 217 218 /* 4, 6 not connected */ 219 }; 220}; 221 222&qspi { 223 status = "okay"; 224 flash@0 { 225 compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ 226 #address-cells = <1>; 227 #size-cells = <1>; 228 reg = <0x0>; 229 }; 230}; 231 232&rtc { 233 status = "okay"; 234}; 235 236&psgtr { 237 status = "okay"; 238 /* nc, sata, usb3, dp */ 239 clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; 240 clock-names = "ref1", "ref2", "ref3"; 241}; 242 243&sata { 244 status = "okay"; 245 /* SATA OOB timing settings */ 246 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 247 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 248 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 249 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 250 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 251 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 252 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 253 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 254 phy-names = "sata-phy"; 255 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; 256}; 257 258/* SD1 with level shifter */ 259&sdhci1 { 260 status = "okay"; 261 no-1-8-v; 262 xlnx,mio-bank = <1>; 263 disable-wp; 264}; 265 266&uart0 { 267 status = "okay"; 268}; 269 270&uart1 { 271 status = "okay"; 272}; 273 274/* ULPI SMSC USB3320 */ 275&usb0 { 276 status = "okay"; 277 dr_mode = "host"; 278}; 279 280&watchdog0 { 281 status = "okay"; 282}; 283 284&zynqmp_dpdma { 285 status = "okay"; 286}; 287 288&zynqmp_dpsub { 289 status = "okay"; 290 phy-names = "dp-phy0", "dp-phy1"; 291 phys = <&psgtr 1 PHY_TYPE_DP 0 3>, 292 <&psgtr 0 PHY_TYPE_DP 1 3>; 293}; 294