xref: /linux/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts (revision db4a3f0fbedb0398f77b9047e8b8bb2b49f355bb) 
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU104
4 *
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
7 *
8 * Michal Simek <michal.simek@amd.com>
9 */
10
11/dts-v1/;
12
13#include "zynqmp.dtsi"
14#include "zynqmp-clk-ccf.dtsi"
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17#include <dt-bindings/phy/phy.h>
18
19/ {
20	model = "ZynqMP ZCU104 RevA";
21	compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
22
23	aliases {
24		ethernet0 = &gem3;
25		i2c0 = &i2c1;
26		mmc0 = &sdhci1;
27		nvmem0 = &eeprom;
28		rtc0 = &rtc;
29		serial0 = &uart0;
30		serial1 = &uart1;
31		serial2 = &dcc;
32		spi0 = &qspi;
33		usb0 = &usb0;
34	};
35
36	chosen {
37		bootargs = "earlycon";
38		stdout-path = "serial0:115200n8";
39	};
40
41	memory@0 {
42		device_type = "memory";
43		reg = <0x0 0x0 0x0 0x80000000>;
44	};
45
46	clock_8t49n287_5: clk125 {
47		compatible = "fixed-clock";
48		#clock-cells = <0>;
49		clock-frequency = <125000000>;
50	};
51
52	clock_8t49n287_2: clk26 {
53		compatible = "fixed-clock";
54		#clock-cells = <0>;
55		clock-frequency = <26000000>;
56	};
57
58	clock_8t49n287_3: clk27 {
59		compatible = "fixed-clock";
60		#clock-cells = <0>;
61		clock-frequency = <27000000>;
62	};
63
64	dpcon {
65		compatible = "dp-connector";
66		label = "P11";
67		type = "full-size";
68
69		port {
70			dpcon_in: endpoint {
71				remote-endpoint = <&dpsub_dp_out>;
72			};
73		};
74	};
75};
76
77&can1 {
78	status = "okay";
79	pinctrl-names = "default";
80	pinctrl-0 = <&pinctrl_can1_default>;
81};
82
83&dcc {
84	status = "okay";
85};
86
87&fpd_dma_chan1 {
88	status = "okay";
89};
90
91&fpd_dma_chan2 {
92	status = "okay";
93};
94
95&fpd_dma_chan3 {
96	status = "okay";
97};
98
99&fpd_dma_chan4 {
100	status = "okay";
101};
102
103&fpd_dma_chan5 {
104	status = "okay";
105};
106
107&fpd_dma_chan6 {
108	status = "okay";
109};
110
111&fpd_dma_chan7 {
112	status = "okay";
113};
114
115&fpd_dma_chan8 {
116	status = "okay";
117};
118
119&gem3 {
120	status = "okay";
121	phy-handle = <&phy0>;
122	phy-mode = "rgmii-id";
123	pinctrl-names = "default";
124	pinctrl-0 = <&pinctrl_gem3_default>;
125	mdio: mdio {
126		#address-cells = <1>;
127		#size-cells = <0>;
128		phy0: ethernet-phy@c {
129			#phy-cells = <1>;
130			compatible = "ethernet-phy-id2000.a231";
131			reg = <0xc>;
132			ti,rx-internal-delay = <0x8>;
133			ti,tx-internal-delay = <0xa>;
134			ti,fifo-depth = <0x1>;
135			ti,dp83867-rxctrl-strap-quirk;
136			reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
137		};
138	};
139};
140
141&gpio {
142	status = "okay";
143};
144
145&gpu {
146	status = "okay";
147};
148
149&i2c1 {
150	status = "okay";
151	clock-frequency = <400000>;
152	pinctrl-names = "default", "gpio";
153	pinctrl-0 = <&pinctrl_i2c1_default>;
154	pinctrl-1 = <&pinctrl_i2c1_gpio>;
155	scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
156	sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
157
158	/* Another connection to this bus via PL i2c via PCA9306 - u45 */
159	i2c-mux@74 { /* u34 */
160		compatible = "nxp,pca9548";
161		#address-cells = <1>;
162		#size-cells = <0>;
163		reg = <0x74>;
164		i2c@0 {
165			#address-cells = <1>;
166			#size-cells = <0>;
167			reg = <0>;
168			/*
169			 * IIC_EEPROM 1kB memory which uses 256B blocks
170			 * where every block has different address.
171			 *    0 - 256B address 0x54
172			 * 256B - 512B address 0x55
173			 * 512B - 768B address 0x56
174			 * 768B - 1024B address 0x57
175			 */
176			eeprom: eeprom@54 { /* u23 */
177				compatible = "atmel,24c08";
178				reg = <0x54>;
179				#address-cells = <1>;
180				#size-cells = <1>;
181			};
182		};
183
184		i2c@1 {
185			#address-cells = <1>;
186			#size-cells = <0>;
187			reg = <1>;
188			/* 8T49N287 - u182 */
189		};
190
191		i2c@2 {
192			#address-cells = <1>;
193			#size-cells = <0>;
194			reg = <2>;
195			irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
196				compatible = "infineon,irps5401";
197				reg = <0x43>; /* pmbus / i2c 0x13 */
198			};
199			irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
200				compatible = "infineon,irps5401";
201				reg = <0x44>; /* pmbus / i2c 0x14 */
202			};
203		};
204
205		i2c@4 {
206			#address-cells = <1>;
207			#size-cells = <0>;
208			reg = <4>;
209			tca6416_u97: gpio@20 {
210				compatible = "ti,tca6416";
211				reg = <0x20>;
212				gpio-controller;
213				#gpio-cells = <2>;
214				/*
215				 * IRQ not connected
216				 * Lines:
217				 * 0 - IRPS5401_ALERT_B
218				 * 1 - HDMI_8T49N241_INT_ALM
219				 * 2 - MAX6643_OT_B
220				 * 3 - MAX6643_FANFAIL_B
221				 * 5 - IIC_MUX_RESET_B
222				 * 6 - GEM3_EXP_RESET_B
223				 * 7 - FMC_LPC_PRSNT_M2C_B
224				 * 4, 10 - 17 - not connected
225				 */
226			};
227		};
228
229		i2c@5 {
230			#address-cells = <1>;
231			#size-cells = <0>;
232			reg = <5>;
233		};
234
235		i2c@7 {
236			#address-cells = <1>;
237			#size-cells = <0>;
238			reg = <7>;
239		};
240
241		/* 3, 6 not connected */
242	};
243};
244
245&pinctrl0 {
246	status = "okay";
247
248	pinctrl_can1_default: can1-default {
249		mux {
250			function = "can1";
251			groups = "can1_6_grp";
252		};
253
254		conf {
255			groups = "can1_6_grp";
256			slew-rate = <SLEW_RATE_SLOW>;
257			power-source = <IO_STANDARD_LVCMOS18>;
258			drive-strength = <12>;
259		};
260
261		conf-rx {
262			pins = "MIO25";
263			bias-high-impedance;
264		};
265
266		conf-tx {
267			pins = "MIO24";
268			bias-disable;
269		};
270	};
271
272	pinctrl_i2c1_default: i2c1-default {
273		mux {
274			groups = "i2c1_4_grp";
275			function = "i2c1";
276		};
277
278		conf {
279			groups = "i2c1_4_grp";
280			bias-pull-up;
281			slew-rate = <SLEW_RATE_SLOW>;
282			power-source = <IO_STANDARD_LVCMOS18>;
283			drive-strength = <12>;
284		};
285	};
286
287	pinctrl_i2c1_gpio: i2c1-gpio-grp {
288		mux {
289			groups = "gpio0_16_grp", "gpio0_17_grp";
290			function = "gpio0";
291		};
292
293		conf {
294			groups = "gpio0_16_grp", "gpio0_17_grp";
295			slew-rate = <SLEW_RATE_SLOW>;
296			power-source = <IO_STANDARD_LVCMOS18>;
297			drive-strength = <12>;
298		};
299	};
300
301	pinctrl_gem3_default: gem3-default {
302		mux {
303			function = "ethernet3";
304			groups = "ethernet3_0_grp";
305		};
306
307		conf {
308			groups = "ethernet3_0_grp";
309			slew-rate = <SLEW_RATE_SLOW>;
310			power-source = <IO_STANDARD_LVCMOS18>;
311			drive-strength = <12>;
312		};
313
314		conf-rx {
315			pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
316									"MIO75";
317			bias-high-impedance;
318			low-power-disable;
319		};
320
321		conf-tx {
322			pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
323									"MIO69";
324			bias-disable;
325			low-power-enable;
326		};
327
328		mux-mdio {
329			function = "mdio3";
330			groups = "mdio3_0_grp";
331		};
332
333		conf-mdio {
334			groups = "mdio3_0_grp";
335			slew-rate = <SLEW_RATE_SLOW>;
336			power-source = <IO_STANDARD_LVCMOS18>;
337			bias-disable;
338		};
339	};
340
341	pinctrl_sdhci1_default: sdhci1-default {
342		mux {
343			groups = "sdio1_0_grp";
344			function = "sdio1";
345		};
346
347		conf {
348			groups = "sdio1_0_grp";
349			slew-rate = <SLEW_RATE_SLOW>;
350			power-source = <IO_STANDARD_LVCMOS18>;
351			bias-disable;
352			drive-strength = <12>;
353		};
354
355		mux-cd {
356			groups = "sdio1_cd_0_grp";
357			function = "sdio1_cd";
358		};
359
360		conf-cd {
361			groups = "sdio1_cd_0_grp";
362			bias-high-impedance;
363			bias-pull-up;
364			slew-rate = <SLEW_RATE_SLOW>;
365			power-source = <IO_STANDARD_LVCMOS18>;
366		};
367	};
368
369	pinctrl_uart0_default: uart0-default {
370		mux {
371			groups = "uart0_4_grp";
372			function = "uart0";
373		};
374
375		conf {
376			groups = "uart0_4_grp";
377			slew-rate = <SLEW_RATE_SLOW>;
378			power-source = <IO_STANDARD_LVCMOS18>;
379			drive-strength = <12>;
380		};
381
382		conf-rx {
383			pins = "MIO18";
384			bias-high-impedance;
385		};
386
387		conf-tx {
388			pins = "MIO19";
389			bias-disable;
390		};
391	};
392
393	pinctrl_uart1_default: uart1-default {
394		mux {
395			groups = "uart1_5_grp";
396			function = "uart1";
397		};
398
399		conf {
400			groups = "uart1_5_grp";
401			slew-rate = <SLEW_RATE_SLOW>;
402			power-source = <IO_STANDARD_LVCMOS18>;
403			drive-strength = <12>;
404		};
405
406		conf-rx {
407			pins = "MIO21";
408			bias-high-impedance;
409		};
410
411		conf-tx {
412			pins = "MIO20";
413			bias-disable;
414		};
415	};
416
417	pinctrl_usb0_default: usb0-default {
418		mux {
419			groups = "usb0_0_grp";
420			function = "usb0";
421		};
422
423		conf {
424			groups = "usb0_0_grp";
425			power-source = <IO_STANDARD_LVCMOS18>;
426		};
427
428		conf-rx {
429			pins = "MIO52", "MIO53", "MIO55";
430			bias-high-impedance;
431			drive-strength = <12>;
432			slew-rate = <SLEW_RATE_FAST>;
433		};
434
435		conf-tx {
436			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
437			       "MIO60", "MIO61", "MIO62", "MIO63";
438			bias-disable;
439			drive-strength = <4>;
440			slew-rate = <SLEW_RATE_SLOW>;
441		};
442	};
443};
444
445&psgtr {
446	status = "okay";
447	/* nc, sata, usb3, dp */
448	clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
449	clock-names = "ref1", "ref2", "ref3";
450};
451
452&qspi {
453	status = "okay";
454	flash@0 {
455		compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
456		#address-cells = <1>;
457		#size-cells = <1>;
458		reg = <0x0>;
459		spi-tx-bus-width = <4>;
460		spi-rx-bus-width = <4>;
461		spi-max-frequency = <108000000>; /* Based on DC1 spec */
462	};
463};
464
465&rtc {
466	status = "okay";
467};
468
469&sata {
470	status = "okay";
471	/* SATA OOB timing settings */
472	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
473	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
474	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
475	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
476	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
477	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
478	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
479	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
480	phy-names = "sata-phy";
481	phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
482};
483
484/* SD1 with level shifter */
485&sdhci1 {
486	status = "okay";
487	no-1-8-v;
488	pinctrl-names = "default";
489	pinctrl-0 = <&pinctrl_sdhci1_default>;
490	xlnx,mio-bank = <1>;
491	disable-wp;
492};
493
494&uart0 {
495	status = "okay";
496	pinctrl-names = "default";
497	pinctrl-0 = <&pinctrl_uart0_default>;
498};
499
500&uart1 {
501	status = "okay";
502	pinctrl-names = "default";
503	pinctrl-0 = <&pinctrl_uart1_default>;
504};
505
506/* ULPI SMSC USB3320 */
507&usb0 {
508	status = "okay";
509	pinctrl-names = "default";
510	pinctrl-0 = <&pinctrl_usb0_default>;
511	phy-names = "usb3-phy";
512	phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
513};
514
515&dwc3_0 {
516	status = "okay";
517	dr_mode = "host";
518	snps,usb3_lpm_capable;
519	maximum-speed = "super-speed";
520};
521
522&watchdog0 {
523	status = "okay";
524};
525
526&ams_ps {
527	status = "okay";
528};
529
530&ams_pl {
531	status = "okay";
532};
533
534&zynqmp_dpdma {
535	status = "okay";
536};
537
538&zynqmp_dpsub {
539	status = "okay";
540	phy-names = "dp-phy0", "dp-phy1";
541	phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
542	       <&psgtr 0 PHY_TYPE_DP 1 3>;
543};
544
545&out_dp {
546	dpsub_dp_out: endpoint {
547		remote-endpoint = <&dpcon_in>;
548	};
549};
550