1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP ZCU102 RevA 4 * 5 * (C) Copyright 2015 - 2022, Xilinx, Inc. 6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. 7 * 8 * Michal Simek <michal.simek@amd.com> 9 */ 10 11/dts-v1/; 12 13#include "zynqmp.dtsi" 14#include "zynqmp-clk-ccf.dtsi" 15#include <dt-bindings/input/input.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 18#include <dt-bindings/phy/phy.h> 19 20/ { 21 model = "ZynqMP ZCU102 RevA"; 22 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; 23 24 aliases { 25 ethernet0 = &gem3; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 mmc0 = &sdhci1; 29 nvmem0 = &eeprom; 30 rtc0 = &rtc; 31 serial0 = &uart0; 32 serial1 = &uart1; 33 serial2 = &dcc; 34 spi0 = &qspi; 35 usb0 = &usb0; 36 }; 37 38 chosen { 39 bootargs = "earlycon"; 40 stdout-path = "serial0:115200n8"; 41 }; 42 43 memory@0 { 44 device_type = "memory"; 45 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; 46 }; 47 48 gpio-keys { 49 compatible = "gpio-keys"; 50 autorepeat; 51 switch-19 { 52 label = "sw19"; 53 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; 54 linux,code = <KEY_DOWN>; 55 wakeup-source; 56 autorepeat; 57 }; 58 }; 59 60 leds { 61 compatible = "gpio-leds"; 62 heartbeat-led { 63 label = "heartbeat"; 64 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; 65 linux,default-trigger = "heartbeat"; 66 }; 67 }; 68 69 ina226-u76 { 70 compatible = "iio-hwmon"; 71 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; 72 }; 73 ina226-u77 { 74 compatible = "iio-hwmon"; 75 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; 76 }; 77 ina226-u78 { 78 compatible = "iio-hwmon"; 79 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; 80 }; 81 ina226-u87 { 82 compatible = "iio-hwmon"; 83 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; 84 }; 85 ina226-u85 { 86 compatible = "iio-hwmon"; 87 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; 88 }; 89 ina226-u86 { 90 compatible = "iio-hwmon"; 91 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; 92 }; 93 ina226-u93 { 94 compatible = "iio-hwmon"; 95 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; 96 }; 97 ina226-u88 { 98 compatible = "iio-hwmon"; 99 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; 100 }; 101 ina226-u15 { 102 compatible = "iio-hwmon"; 103 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; 104 }; 105 ina226-u92 { 106 compatible = "iio-hwmon"; 107 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; 108 }; 109 ina226-u79 { 110 compatible = "iio-hwmon"; 111 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; 112 }; 113 ina226-u81 { 114 compatible = "iio-hwmon"; 115 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; 116 }; 117 ina226-u80 { 118 compatible = "iio-hwmon"; 119 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; 120 }; 121 ina226-u84 { 122 compatible = "iio-hwmon"; 123 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; 124 }; 125 ina226-u16 { 126 compatible = "iio-hwmon"; 127 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; 128 }; 129 ina226-u65 { 130 compatible = "iio-hwmon"; 131 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; 132 }; 133 ina226-u74 { 134 compatible = "iio-hwmon"; 135 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; 136 }; 137 ina226-u75 { 138 compatible = "iio-hwmon"; 139 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; 140 }; 141 142 /* 48MHz reference crystal */ 143 ref48: ref48M { 144 compatible = "fixed-clock"; 145 #clock-cells = <0>; 146 clock-frequency = <48000000>; 147 }; 148 149 refhdmi: refhdmi { 150 compatible = "fixed-clock"; 151 #clock-cells = <0>; 152 clock-frequency = <114285000>; 153 }; 154 155 dpcon { 156 compatible = "dp-connector"; 157 label = "P11"; 158 type = "full-size"; 159 160 port { 161 dpcon_in: endpoint { 162 remote-endpoint = <&dpsub_dp_out>; 163 }; 164 }; 165 }; 166}; 167 168&can1 { 169 status = "okay"; 170 pinctrl-names = "default"; 171 pinctrl-0 = <&pinctrl_can1_default>; 172}; 173 174&dcc { 175 status = "okay"; 176}; 177 178&fpd_dma_chan1 { 179 status = "okay"; 180}; 181 182&fpd_dma_chan2 { 183 status = "okay"; 184}; 185 186&fpd_dma_chan3 { 187 status = "okay"; 188}; 189 190&fpd_dma_chan4 { 191 status = "okay"; 192}; 193 194&fpd_dma_chan5 { 195 status = "okay"; 196}; 197 198&fpd_dma_chan6 { 199 status = "okay"; 200}; 201 202&fpd_dma_chan7 { 203 status = "okay"; 204}; 205 206&fpd_dma_chan8 { 207 status = "okay"; 208}; 209 210&gem3 { 211 status = "okay"; 212 phy-handle = <&phy0>; 213 phy-mode = "rgmii-id"; 214 pinctrl-names = "default"; 215 pinctrl-0 = <&pinctrl_gem3_default>; 216 mdio: mdio { 217 #address-cells = <1>; 218 #size-cells = <0>; 219 phy0: ethernet-phy@21 { 220 #phy-cells = <1>; 221 compatible = "ethernet-phy-id2000.a231"; 222 reg = <21>; 223 ti,rx-internal-delay = <0x8>; 224 ti,tx-internal-delay = <0xa>; 225 ti,fifo-depth = <0x1>; 226 ti,dp83867-rxctrl-strap-quirk; 227 reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; 228 }; 229 }; 230}; 231 232&gpio { 233 status = "okay"; 234 pinctrl-names = "default"; 235 pinctrl-0 = <&pinctrl_gpio_default>; 236}; 237 238&gpu { 239 status = "okay"; 240}; 241 242&i2c0 { 243 status = "okay"; 244 clock-frequency = <400000>; 245 pinctrl-names = "default", "gpio"; 246 pinctrl-0 = <&pinctrl_i2c0_default>; 247 pinctrl-1 = <&pinctrl_i2c0_gpio>; 248 scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 249 sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 250 251 tca6416_u97: gpio@20 { 252 compatible = "ti,tca6416"; 253 reg = <0x20>; 254 gpio-controller; /* IRQ not connected */ 255 #gpio-cells = <2>; 256 gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", 257 "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", 258 "", "", "", "", "", "", "", "", ""; 259 gtr-sel0-hog { 260 gpio-hog; 261 gpios = <0 0>; 262 output-low; /* PCIE = 0, DP = 1 */ 263 line-name = "sel0"; 264 }; 265 gtr-sel1-hog { 266 gpio-hog; 267 gpios = <1 0>; 268 output-high; /* PCIE = 0, DP = 1 */ 269 line-name = "sel1"; 270 }; 271 gtr-sel2-hog { 272 gpio-hog; 273 gpios = <2 0>; 274 output-high; /* PCIE = 0, USB0 = 1 */ 275 line-name = "sel2"; 276 }; 277 gtr-sel3-hog { 278 gpio-hog; 279 gpios = <3 0>; 280 output-high; /* PCIE = 0, SATA = 1 */ 281 line-name = "sel3"; 282 }; 283 }; 284 285 tca6416_u61: gpio@21 { 286 compatible = "ti,tca6416"; 287 reg = <0x21>; 288 gpio-controller; /* IRQ not connected */ 289 #gpio-cells = <2>; 290 gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", 291 "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", 292 "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", 293 "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; 294 }; 295 296 i2c-mux@75 { /* u60 */ 297 compatible = "nxp,pca9544"; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 reg = <0x75>; 301 i2c@0 { 302 #address-cells = <1>; 303 #size-cells = <0>; 304 reg = <0>; 305 /* PS_PMBUS */ 306 u76: ina226@40 { /* u76 */ 307 compatible = "ti,ina226"; 308 #io-channel-cells = <1>; 309 label = "ina226-u76"; 310 reg = <0x40>; 311 shunt-resistor = <5000>; 312 }; 313 u77: ina226@41 { /* u77 */ 314 compatible = "ti,ina226"; 315 #io-channel-cells = <1>; 316 label = "ina226-u77"; 317 reg = <0x41>; 318 shunt-resistor = <5000>; 319 }; 320 u78: ina226@42 { /* u78 */ 321 compatible = "ti,ina226"; 322 #io-channel-cells = <1>; 323 label = "ina226-u78"; 324 reg = <0x42>; 325 shunt-resistor = <5000>; 326 }; 327 u87: ina226@43 { /* u87 */ 328 compatible = "ti,ina226"; 329 #io-channel-cells = <1>; 330 label = "ina226-u87"; 331 reg = <0x43>; 332 shunt-resistor = <5000>; 333 }; 334 u85: ina226@44 { /* u85 */ 335 compatible = "ti,ina226"; 336 #io-channel-cells = <1>; 337 label = "ina226-u85"; 338 reg = <0x44>; 339 shunt-resistor = <5000>; 340 }; 341 u86: ina226@45 { /* u86 */ 342 compatible = "ti,ina226"; 343 #io-channel-cells = <1>; 344 label = "ina226-u86"; 345 reg = <0x45>; 346 shunt-resistor = <5000>; 347 }; 348 u93: ina226@46 { /* u93 */ 349 compatible = "ti,ina226"; 350 #io-channel-cells = <1>; 351 label = "ina226-u93"; 352 reg = <0x46>; 353 shunt-resistor = <5000>; 354 }; 355 u88: ina226@47 { /* u88 */ 356 compatible = "ti,ina226"; 357 #io-channel-cells = <1>; 358 label = "ina226-u88"; 359 reg = <0x47>; 360 shunt-resistor = <5000>; 361 }; 362 u15: ina226@4a { /* u15 */ 363 compatible = "ti,ina226"; 364 #io-channel-cells = <1>; 365 label = "ina226-u15"; 366 reg = <0x4a>; 367 shunt-resistor = <5000>; 368 }; 369 u92: ina226@4b { /* u92 */ 370 compatible = "ti,ina226"; 371 #io-channel-cells = <1>; 372 label = "ina226-u92"; 373 reg = <0x4b>; 374 shunt-resistor = <5000>; 375 }; 376 }; 377 i2c@1 { 378 #address-cells = <1>; 379 #size-cells = <0>; 380 reg = <1>; 381 /* PL_PMBUS */ 382 u79: ina226@40 { /* u79 */ 383 compatible = "ti,ina226"; 384 #io-channel-cells = <1>; 385 label = "ina226-u79"; 386 reg = <0x40>; 387 shunt-resistor = <2000>; 388 }; 389 u81: ina226@41 { /* u81 */ 390 compatible = "ti,ina226"; 391 #io-channel-cells = <1>; 392 label = "ina226-u81"; 393 reg = <0x41>; 394 shunt-resistor = <5000>; 395 }; 396 u80: ina226@42 { /* u80 */ 397 compatible = "ti,ina226"; 398 #io-channel-cells = <1>; 399 label = "ina226-u80"; 400 reg = <0x42>; 401 shunt-resistor = <5000>; 402 }; 403 u84: ina226@43 { /* u84 */ 404 compatible = "ti,ina226"; 405 #io-channel-cells = <1>; 406 label = "ina226-u84"; 407 reg = <0x43>; 408 shunt-resistor = <5000>; 409 }; 410 u16: ina226@44 { /* u16 */ 411 compatible = "ti,ina226"; 412 #io-channel-cells = <1>; 413 label = "ina226-u16"; 414 reg = <0x44>; 415 shunt-resistor = <5000>; 416 }; 417 u65: ina226@45 { /* u65 */ 418 compatible = "ti,ina226"; 419 #io-channel-cells = <1>; 420 label = "ina226-u65"; 421 reg = <0x45>; 422 shunt-resistor = <5000>; 423 }; 424 u74: ina226@46 { /* u74 */ 425 compatible = "ti,ina226"; 426 #io-channel-cells = <1>; 427 label = "ina226-u74"; 428 reg = <0x46>; 429 shunt-resistor = <5000>; 430 }; 431 u75: ina226@47 { /* u75 */ 432 compatible = "ti,ina226"; 433 #io-channel-cells = <1>; 434 label = "ina226-u75"; 435 reg = <0x47>; 436 shunt-resistor = <5000>; 437 }; 438 }; 439 i2c@2 { 440 #address-cells = <1>; 441 #size-cells = <0>; 442 reg = <2>; 443 /* MAXIM_PMBUS - 00 */ 444 max15301@a { /* u46 */ 445 compatible = "maxim,max15301"; 446 reg = <0xa>; 447 }; 448 max15303@b { /* u4 */ 449 compatible = "maxim,max15303"; 450 reg = <0xb>; 451 }; 452 max15303@10 { /* u13 */ 453 compatible = "maxim,max15303"; 454 reg = <0x10>; 455 }; 456 max15301@13 { /* u47 */ 457 compatible = "maxim,max15301"; 458 reg = <0x13>; 459 }; 460 max15303@14 { /* u7 */ 461 compatible = "maxim,max15303"; 462 reg = <0x14>; 463 }; 464 max15303@15 { /* u6 */ 465 compatible = "maxim,max15303"; 466 reg = <0x15>; 467 }; 468 max15303@16 { /* u10 */ 469 compatible = "maxim,max15303"; 470 reg = <0x16>; 471 }; 472 max15303@17 { /* u9 */ 473 compatible = "maxim,max15303"; 474 reg = <0x17>; 475 }; 476 max15301@18 { /* u63 */ 477 compatible = "maxim,max15301"; 478 reg = <0x18>; 479 }; 480 max15303@1a { /* u49 */ 481 compatible = "maxim,max15303"; 482 reg = <0x1a>; 483 }; 484 max15303@1d { /* u18 */ 485 compatible = "maxim,max15303"; 486 reg = <0x1d>; 487 }; 488 max15303@20 { /* u8 */ 489 compatible = "maxim,max15303"; 490 status = "disabled"; /* unreachable */ 491 reg = <0x20>; 492 }; 493 max20751@72 { /* u95 */ 494 compatible = "maxim,max20751"; 495 reg = <0x72>; 496 }; 497 max20751@73 { /* u96 */ 498 compatible = "maxim,max20751"; 499 reg = <0x73>; 500 }; 501 }; 502 /* Bus 3 is not connected */ 503 }; 504}; 505 506&i2c1 { 507 status = "okay"; 508 clock-frequency = <400000>; 509 pinctrl-names = "default", "gpio"; 510 pinctrl-0 = <&pinctrl_i2c1_default>; 511 pinctrl-1 = <&pinctrl_i2c1_gpio>; 512 scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 513 sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 514 515 /* PL i2c via PCA9306 - u45 */ 516 i2c-mux@74 { /* u34 */ 517 compatible = "nxp,pca9548"; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 reg = <0x74>; 521 i2c@0 { 522 #address-cells = <1>; 523 #size-cells = <0>; 524 reg = <0>; 525 /* 526 * IIC_EEPROM 1kB memory which uses 256B blocks 527 * where every block has different address. 528 * 0 - 256B address 0x54 529 * 256B - 512B address 0x55 530 * 512B - 768B address 0x56 531 * 768B - 1024B address 0x57 532 */ 533 eeprom: eeprom@54 { /* u23 */ 534 compatible = "atmel,24c08"; 535 reg = <0x54>; 536 }; 537 }; 538 i2c@1 { 539 #address-cells = <1>; 540 #size-cells = <0>; 541 reg = <1>; 542 si5341: clock-generator@36 { /* SI5341 - u69 */ 543 compatible = "silabs,si5341"; 544 reg = <0x36>; 545 #clock-cells = <2>; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 clocks = <&ref48>; 549 clock-names = "xtal"; 550 clock-output-names = "si5341"; 551 552 si5341_0: out@0 { 553 /* refclk0 for PS-GT, used for DP */ 554 reg = <0>; 555 always-on; 556 }; 557 si5341_2: out@2 { 558 /* refclk2 for PS-GT, used for USB3 */ 559 reg = <2>; 560 always-on; 561 }; 562 si5341_3: out@3 { 563 /* refclk3 for PS-GT, used for SATA */ 564 reg = <3>; 565 always-on; 566 }; 567 si5341_4: out@4 { 568 /* refclk4 for PS-GT, used for PCIE slot */ 569 reg = <4>; 570 always-on; 571 }; 572 si5341_5: out@5 { 573 /* refclk5 for PS-GT, used for PCIE */ 574 reg = <5>; 575 always-on; 576 }; 577 si5341_6: out@6 { 578 /* refclk6 PL CLK125 */ 579 reg = <6>; 580 always-on; 581 }; 582 si5341_7: out@7 { 583 /* refclk7 PL CLK74 */ 584 reg = <7>; 585 always-on; 586 }; 587 si5341_9: out@9 { 588 /* refclk9 used for PS_REF_CLK 33.3 MHz */ 589 reg = <9>; 590 always-on; 591 }; 592 }; 593 }; 594 i2c@2 { 595 #address-cells = <1>; 596 #size-cells = <0>; 597 reg = <2>; 598 si570_1: clock-generator@5d { /* USER SI570 - u42 */ 599 #clock-cells = <0>; 600 compatible = "silabs,si570"; 601 reg = <0x5d>; 602 temperature-stability = <50>; 603 factory-fout = <300000000>; 604 clock-frequency = <300000000>; 605 clock-output-names = "si570_user"; 606 }; 607 }; 608 i2c@3 { 609 #address-cells = <1>; 610 #size-cells = <0>; 611 reg = <3>; 612 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ 613 #clock-cells = <0>; 614 compatible = "silabs,si570"; 615 reg = <0x5d>; 616 temperature-stability = <50>; /* copy from zc702 */ 617 factory-fout = <156250000>; 618 clock-frequency = <156250000>; 619 clock-output-names = "si570_mgt"; 620 }; 621 }; 622 i2c@4 { 623 #address-cells = <1>; 624 #size-cells = <0>; 625 reg = <4>; 626 /* SI5328 - u20 */ 627 }; 628 /* 5 - 7 unconnected */ 629 }; 630 631 i2c-mux@75 { 632 compatible = "nxp,pca9548"; /* u135 */ 633 #address-cells = <1>; 634 #size-cells = <0>; 635 reg = <0x75>; 636 637 i2c@0 { 638 #address-cells = <1>; 639 #size-cells = <0>; 640 reg = <0>; 641 /* HPC0_IIC */ 642 }; 643 i2c@1 { 644 #address-cells = <1>; 645 #size-cells = <0>; 646 reg = <1>; 647 /* HPC1_IIC */ 648 }; 649 i2c@2 { 650 #address-cells = <1>; 651 #size-cells = <0>; 652 reg = <2>; 653 /* SYSMON */ 654 }; 655 i2c@3 { 656 #address-cells = <1>; 657 #size-cells = <0>; 658 reg = <3>; 659 /* DDR4 SODIMM */ 660 }; 661 i2c@4 { 662 #address-cells = <1>; 663 #size-cells = <0>; 664 reg = <4>; 665 /* SEP 3 */ 666 }; 667 i2c@5 { 668 #address-cells = <1>; 669 #size-cells = <0>; 670 reg = <5>; 671 /* SEP 2 */ 672 }; 673 i2c@6 { 674 #address-cells = <1>; 675 #size-cells = <0>; 676 reg = <6>; 677 /* SEP 1 */ 678 }; 679 i2c@7 { 680 #address-cells = <1>; 681 #size-cells = <0>; 682 reg = <7>; 683 /* SEP 0 */ 684 }; 685 }; 686}; 687 688&pinctrl0 { 689 status = "okay"; 690 pinctrl_i2c0_default: i2c0-default { 691 mux { 692 groups = "i2c0_3_grp"; 693 function = "i2c0"; 694 }; 695 696 conf { 697 groups = "i2c0_3_grp"; 698 bias-pull-up; 699 slew-rate = <SLEW_RATE_SLOW>; 700 power-source = <IO_STANDARD_LVCMOS18>; 701 }; 702 }; 703 704 pinctrl_i2c0_gpio: i2c0-gpio-grp { 705 mux { 706 groups = "gpio0_14_grp", "gpio0_15_grp"; 707 function = "gpio0"; 708 }; 709 710 conf { 711 groups = "gpio0_14_grp", "gpio0_15_grp"; 712 slew-rate = <SLEW_RATE_SLOW>; 713 power-source = <IO_STANDARD_LVCMOS18>; 714 }; 715 }; 716 717 pinctrl_i2c1_default: i2c1-default { 718 mux { 719 groups = "i2c1_4_grp"; 720 function = "i2c1"; 721 }; 722 723 conf { 724 groups = "i2c1_4_grp"; 725 bias-pull-up; 726 slew-rate = <SLEW_RATE_SLOW>; 727 power-source = <IO_STANDARD_LVCMOS18>; 728 }; 729 }; 730 731 pinctrl_i2c1_gpio: i2c1-gpio-grp { 732 mux { 733 groups = "gpio0_16_grp", "gpio0_17_grp"; 734 function = "gpio0"; 735 }; 736 737 conf { 738 groups = "gpio0_16_grp", "gpio0_17_grp"; 739 slew-rate = <SLEW_RATE_SLOW>; 740 power-source = <IO_STANDARD_LVCMOS18>; 741 }; 742 }; 743 744 pinctrl_uart0_default: uart0-default { 745 mux { 746 groups = "uart0_4_grp"; 747 function = "uart0"; 748 }; 749 750 conf { 751 groups = "uart0_4_grp"; 752 slew-rate = <SLEW_RATE_SLOW>; 753 power-source = <IO_STANDARD_LVCMOS18>; 754 }; 755 756 conf-rx { 757 pins = "MIO18"; 758 bias-high-impedance; 759 }; 760 761 conf-tx { 762 pins = "MIO19"; 763 bias-disable; 764 }; 765 }; 766 767 pinctrl_uart1_default: uart1-default { 768 mux { 769 groups = "uart1_5_grp"; 770 function = "uart1"; 771 }; 772 773 conf { 774 groups = "uart1_5_grp"; 775 slew-rate = <SLEW_RATE_SLOW>; 776 power-source = <IO_STANDARD_LVCMOS18>; 777 }; 778 779 conf-rx { 780 pins = "MIO21"; 781 bias-high-impedance; 782 }; 783 784 conf-tx { 785 pins = "MIO20"; 786 bias-disable; 787 }; 788 }; 789 790 pinctrl_usb0_default: usb0-default { 791 mux { 792 groups = "usb0_0_grp"; 793 function = "usb0"; 794 }; 795 796 conf { 797 groups = "usb0_0_grp"; 798 power-source = <IO_STANDARD_LVCMOS18>; 799 }; 800 801 conf-rx { 802 pins = "MIO52", "MIO53", "MIO55"; 803 bias-high-impedance; 804 drive-strength = <12>; 805 slew-rate = <SLEW_RATE_FAST>; 806 }; 807 808 conf-tx { 809 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", 810 "MIO60", "MIO61", "MIO62", "MIO63"; 811 bias-disable; 812 drive-strength = <4>; 813 slew-rate = <SLEW_RATE_SLOW>; 814 }; 815 }; 816 817 pinctrl_gem3_default: gem3-default { 818 mux { 819 function = "ethernet3"; 820 groups = "ethernet3_0_grp"; 821 }; 822 823 conf { 824 groups = "ethernet3_0_grp"; 825 slew-rate = <SLEW_RATE_SLOW>; 826 power-source = <IO_STANDARD_LVCMOS18>; 827 }; 828 829 conf-rx { 830 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", 831 "MIO75"; 832 bias-high-impedance; 833 low-power-disable; 834 }; 835 836 conf-tx { 837 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", 838 "MIO69"; 839 bias-disable; 840 low-power-enable; 841 }; 842 843 mux-mdio { 844 function = "mdio3"; 845 groups = "mdio3_0_grp"; 846 }; 847 848 conf-mdio { 849 groups = "mdio3_0_grp"; 850 slew-rate = <SLEW_RATE_SLOW>; 851 power-source = <IO_STANDARD_LVCMOS18>; 852 bias-disable; 853 }; 854 }; 855 856 pinctrl_can1_default: can1-default { 857 mux { 858 function = "can1"; 859 groups = "can1_6_grp"; 860 }; 861 862 conf { 863 groups = "can1_6_grp"; 864 slew-rate = <SLEW_RATE_SLOW>; 865 power-source = <IO_STANDARD_LVCMOS18>; 866 }; 867 868 conf-rx { 869 pins = "MIO25"; 870 bias-high-impedance; 871 }; 872 873 conf-tx { 874 pins = "MIO24"; 875 bias-disable; 876 }; 877 }; 878 879 pinctrl_sdhci1_default: sdhci1-default { 880 mux { 881 groups = "sdio1_0_grp"; 882 function = "sdio1"; 883 }; 884 885 conf { 886 groups = "sdio1_0_grp"; 887 slew-rate = <SLEW_RATE_SLOW>; 888 power-source = <IO_STANDARD_LVCMOS18>; 889 bias-disable; 890 }; 891 892 mux-cd { 893 groups = "sdio1_cd_0_grp"; 894 function = "sdio1_cd"; 895 }; 896 897 conf-cd { 898 groups = "sdio1_cd_0_grp"; 899 bias-high-impedance; 900 bias-pull-up; 901 slew-rate = <SLEW_RATE_SLOW>; 902 power-source = <IO_STANDARD_LVCMOS18>; 903 }; 904 905 mux-wp { 906 groups = "sdio1_wp_0_grp"; 907 function = "sdio1_wp"; 908 }; 909 910 conf-wp { 911 groups = "sdio1_wp_0_grp"; 912 bias-high-impedance; 913 bias-pull-up; 914 slew-rate = <SLEW_RATE_SLOW>; 915 power-source = <IO_STANDARD_LVCMOS18>; 916 }; 917 }; 918 919 pinctrl_gpio_default: gpio-default { 920 mux-sw { 921 function = "gpio0"; 922 groups = "gpio0_22_grp", "gpio0_23_grp"; 923 }; 924 925 conf-sw { 926 groups = "gpio0_22_grp", "gpio0_23_grp"; 927 slew-rate = <SLEW_RATE_SLOW>; 928 power-source = <IO_STANDARD_LVCMOS18>; 929 }; 930 931 mux-msp { 932 function = "gpio0"; 933 groups = "gpio0_13_grp", "gpio0_38_grp"; 934 }; 935 936 conf-msp { 937 groups = "gpio0_13_grp", "gpio0_38_grp"; 938 slew-rate = <SLEW_RATE_SLOW>; 939 power-source = <IO_STANDARD_LVCMOS18>; 940 }; 941 942 conf-pull-up { 943 pins = "MIO22", "MIO23"; 944 bias-pull-up; 945 }; 946 947 conf-pull-none { 948 pins = "MIO13", "MIO38"; 949 bias-disable; 950 }; 951 }; 952}; 953 954&pcie { 955 status = "okay"; 956 phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>; 957}; 958 959&psgtr { 960 status = "okay"; 961 /* pcie, sata, usb3, dp */ 962 clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; 963 clock-names = "ref0", "ref1", "ref2", "ref3"; 964}; 965 966&qspi { 967 status = "okay"; 968 flash@0 { 969 compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */ 970 #address-cells = <1>; 971 #size-cells = <1>; 972 reg = <0x0>; 973 spi-tx-bus-width = <4>; 974 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ 975 spi-max-frequency = <108000000>; /* Based on DC1 spec */ 976 }; 977}; 978 979&rtc { 980 status = "okay"; 981}; 982 983&sata { 984 status = "okay"; 985 /* SATA OOB timing settings */ 986 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 987 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 988 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 989 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 990 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 991 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 992 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 993 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 994 phy-names = "sata-phy"; 995 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; 996}; 997 998/* SD1 with level shifter */ 999&sdhci1 { 1000 status = "okay"; 1001 /* 1002 * 1.0 revision has level shifter and this property should be 1003 * removed for supporting UHS mode 1004 */ 1005 no-1-8-v; 1006 pinctrl-names = "default"; 1007 pinctrl-0 = <&pinctrl_sdhci1_default>; 1008 xlnx,mio-bank = <1>; 1009}; 1010 1011&uart0 { 1012 status = "okay"; 1013 pinctrl-names = "default"; 1014 pinctrl-0 = <&pinctrl_uart0_default>; 1015}; 1016 1017&uart1 { 1018 status = "okay"; 1019 pinctrl-names = "default"; 1020 pinctrl-0 = <&pinctrl_uart1_default>; 1021}; 1022 1023/* ULPI SMSC USB3320 */ 1024&usb0 { 1025 status = "okay"; 1026 pinctrl-names = "default"; 1027 pinctrl-0 = <&pinctrl_usb0_default>; 1028 phy-names = "usb3-phy"; 1029 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; 1030}; 1031 1032&dwc3_0 { 1033 status = "okay"; 1034 dr_mode = "host"; 1035 snps,usb3_lpm_capable; 1036 maximum-speed = "super-speed"; 1037}; 1038 1039&watchdog0 { 1040 status = "okay"; 1041}; 1042 1043&ams_ps { 1044 status = "okay"; 1045}; 1046 1047&ams_pl { 1048 status = "okay"; 1049}; 1050 1051&zynqmp_dpdma { 1052 status = "okay"; 1053}; 1054 1055&zynqmp_dpsub { 1056 status = "okay"; 1057 phy-names = "dp-phy0"; 1058 phys = <&psgtr 1 PHY_TYPE_DP 0 3>; 1059}; 1060 1061&out_dp { 1062 dpsub_dp_out: endpoint { 1063 remote-endpoint = <&dpcon_in>; 1064 }; 1065}; 1066