xref: /linux/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts (revision db4a3f0fbedb0398f77b9047e8b8bb2b49f355bb)
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU100 revC
4 *
5 * (C) Copyright 2016 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
7 *
8 * Michal Simek <michal.simek@amd.com>
9 * Nathalie Chan King Choy
10 */
11
12/dts-v1/;
13
14#include "zynqmp.dtsi"
15#include "zynqmp-clk-ccf.dtsi"
16#include <dt-bindings/input/input.h>
17#include <dt-bindings/interrupt-controller/irq.h>
18#include <dt-bindings/gpio/gpio.h>
19#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20#include <dt-bindings/phy/phy.h>
21
22/ {
23	model = "ZynqMP ZCU100 RevC";
24	compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp";
25
26	aliases {
27		i2c0 = &i2c1;
28		rtc0 = &rtc;
29		serial0 = &uart1;
30		serial1 = &uart0;
31		serial2 = &dcc;
32		spi0 = &spi0;
33		spi1 = &spi1;
34		usb0 = &usb0;
35		usb1 = &usb1;
36		mmc0 = &sdhci0;
37		mmc1 = &sdhci1;
38	};
39
40	chosen {
41		bootargs = "earlycon";
42		stdout-path = "serial0:115200n8";
43	};
44
45	memory@0 {
46		device_type = "memory";
47		reg = <0x0 0x0 0x0 0x80000000>;
48	};
49
50	gpio-keys {
51		compatible = "gpio-keys";
52		autorepeat;
53		switch-4 {
54			label = "sw4";
55			gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
56			linux,code = <KEY_POWER>;
57			wakeup-source;
58			autorepeat;
59		};
60	};
61
62	iio-hwmon {
63		compatible = "iio-hwmon";
64		io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
65			      <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,
66			      <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,
67			      <&xilinx_ams 9>, <&xilinx_ams 10>,
68			      <&xilinx_ams 11>, <&xilinx_ams 12>;
69	};
70
71	leds {
72		compatible = "gpio-leds";
73		led-ds2 {
74			label = "ds2";
75			gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
76			linux,default-trigger = "heartbeat";
77		};
78
79		led-ds3 {
80			label = "ds3";
81			gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
82			linux,default-trigger = "phy0tx"; /* WLAN tx */
83			default-state = "off";
84		};
85
86		led-ds4 {
87			label = "ds4";
88			gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
89			linux,default-trigger = "phy0rx"; /* WLAN rx */
90			default-state = "off";
91		};
92
93		led-ds5 {
94			label = "ds5";
95			gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
96			linux,default-trigger = "bluetooth-power";
97		};
98
99		led-vbus-det { /* U5 USB5744 VBUS detection via MIO25 */
100			label = "vbus_det";
101			gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
102			default-state = "on";
103		};
104	};
105
106	wmmcsdio_fixed: fixedregulator-mmcsdio {
107		compatible = "regulator-fixed";
108		regulator-name = "wmmcsdio_fixed";
109		regulator-min-microvolt = <3300000>;
110		regulator-max-microvolt = <3300000>;
111		regulator-always-on;
112		regulator-boot-on;
113	};
114
115	sdio_pwrseq: sdio-pwrseq {
116		compatible = "mmc-pwrseq-simple";
117		reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */
118		post-power-on-delay-ms = <10>;
119	};
120
121	ina226 {
122		compatible = "iio-hwmon";
123		io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;
124	};
125
126	si5335_0: si5335-0 { /* clk0_usb - u23 */
127		compatible = "fixed-clock";
128		#clock-cells = <0>;
129		clock-frequency = <26000000>;
130	};
131
132	si5335_1: si5335-1 { /* clk1_dp - u23 */
133		compatible = "fixed-clock";
134		#clock-cells = <0>;
135		clock-frequency = <27000000>;
136	};
137
138	dpcon {
139		compatible = "dp-connector";
140		label = "P11";
141		type = "full-size";
142
143		port {
144			dpcon_in: endpoint {
145				remote-endpoint = <&dpsub_dp_out>;
146			};
147		};
148	};
149};
150
151&dcc {
152	status = "okay";
153};
154
155&gpio {
156	status = "okay";
157	gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL",
158			  "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS",
159			  "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1",
160			  "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1",
161			  "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT",
162			  "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE",
163			  "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL",
164			  "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C",
165			  "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E",
166			  "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3",
167			  "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2",
168			  "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3",
169			  "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK",
170			  "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1",
171			  "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6",
172			  "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */
173			  "", "",
174			  "", "", "", "", "", "", "", "", "", "",
175			  "", "", "", "", "", "", "", "", "", "",
176			  "", "", "", "", "", "", "", "", "", "",
177			  "", "", "", "", "", "", "", "", "", "",
178			  "", "", "", "", "", "", "", "", "", "",
179			  "", "", "", "", "", "", "", "", "", "",
180			  "", "", "", "", "", "", "", "", "", "",
181			  "", "", "", "", "", "", "", "", "", "",
182			  "", "", "", "", "", "", "", "", "", "",
183			  "", "", "", "";
184};
185
186&gpu {
187	status = "okay";
188};
189
190&i2c1 {
191	status = "okay";
192	pinctrl-names = "default", "gpio";
193	pinctrl-0 = <&pinctrl_i2c1_default>;
194	pinctrl-1 = <&pinctrl_i2c1_gpio>;
195	scl-gpios = <&gpio 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
196	sda-gpios = <&gpio 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
197	clock-frequency = <100000>;
198	i2c-mux@75 { /* u11 */
199		compatible = "nxp,pca9548";
200		#address-cells = <1>;
201		#size-cells = <0>;
202		reg = <0x75>;
203		i2csw_0: i2c@0 {
204			#address-cells = <1>;
205			#size-cells = <0>;
206			reg = <0>;
207			label = "LS-I2C0";
208		};
209		i2csw_1: i2c@1 {
210			#address-cells = <1>;
211			#size-cells = <0>;
212			reg = <1>;
213			label = "LS-I2C1";
214		};
215		i2csw_2: i2c@2 {
216			#address-cells = <1>;
217			#size-cells = <0>;
218			reg = <2>;
219			label = "HS-I2C2";
220		};
221		i2csw_3: i2c@3 {
222			#address-cells = <1>;
223			#size-cells = <0>;
224			reg = <3>;
225			label = "HS-I2C3";
226		};
227		i2csw_4: i2c@4 {
228			#address-cells = <1>;
229			#size-cells = <0>;
230			reg = <0x4>;
231
232			pmic: pmic@5e { /* Custom TI PMIC u33 */
233				compatible = "ti,tps65086";
234				reg = <0x5e>;
235				interrupt-parent = <&gpio>;
236				interrupts = <77 IRQ_TYPE_LEVEL_LOW>;
237				#gpio-cells = <2>;
238				gpio-controller;
239			};
240		};
241		i2csw_5: i2c@5 {
242			#address-cells = <1>;
243			#size-cells = <0>;
244			reg = <5>;
245			/* PS_PMBUS */
246			u35: ina226@40 { /* u35 */
247				compatible = "ti,ina226";
248				#io-channel-cells = <1>;
249				reg = <0x40>;
250				shunt-resistor = <10000>;
251				/* MIO31 is alert which should be routed to PMUFW */
252			};
253		};
254		i2csw_6: i2c@6 {
255			#address-cells = <1>;
256			#size-cells = <0>;
257			reg = <6>;
258			/*
259			 * Not Connected
260			 */
261		};
262		i2csw_7: i2c@7 {
263			#address-cells = <1>;
264			#size-cells = <0>;
265			reg = <7>;
266			/*
267			 * usb5744 (DNP) - U5
268			 * 100kHz - this is default freq for us
269			 */
270		};
271	};
272};
273
274&pinctrl0 {
275	status = "okay";
276	pinctrl_i2c1_default: i2c1-default {
277		mux {
278			groups = "i2c1_1_grp";
279			function = "i2c1";
280		};
281
282		conf {
283			groups = "i2c1_1_grp";
284			bias-pull-up;
285			slew-rate = <SLEW_RATE_SLOW>;
286			power-source = <IO_STANDARD_LVCMOS18>;
287		};
288	};
289
290	pinctrl_i2c1_gpio: i2c1-gpio-grp {
291		mux {
292			groups = "gpio0_4_grp", "gpio0_5_grp";
293			function = "gpio0";
294		};
295
296		conf {
297			groups = "gpio0_4_grp", "gpio0_5_grp";
298			slew-rate = <SLEW_RATE_SLOW>;
299			power-source = <IO_STANDARD_LVCMOS18>;
300		};
301	};
302
303	pinctrl_sdhci0_default: sdhci0-default {
304		mux {
305			groups = "sdio0_3_grp";
306			function = "sdio0";
307		};
308
309		conf {
310			groups = "sdio0_3_grp";
311			slew-rate = <SLEW_RATE_SLOW>;
312			power-source = <IO_STANDARD_LVCMOS18>;
313			bias-disable;
314		};
315
316		mux-cd {
317			groups = "sdio0_cd_0_grp";
318			function = "sdio0_cd";
319		};
320
321		conf-cd {
322			groups = "sdio0_cd_0_grp";
323			bias-high-impedance;
324			bias-pull-up;
325			slew-rate = <SLEW_RATE_SLOW>;
326			power-source = <IO_STANDARD_LVCMOS18>;
327		};
328	};
329
330	pinctrl_sdhci1_default: sdhci1-default {
331		mux {
332			groups = "sdio1_2_grp";
333			function = "sdio1";
334		};
335
336		conf {
337			groups = "sdio1_2_grp";
338			slew-rate = <SLEW_RATE_SLOW>;
339			power-source = <IO_STANDARD_LVCMOS18>;
340			bias-disable;
341		};
342	};
343
344	pinctrl_spi0_default: spi0-default {
345		mux {
346			groups = "spi0_3_grp";
347			function = "spi0";
348		};
349
350		conf {
351			groups = "spi0_3_grp";
352			bias-disable;
353			slew-rate = <SLEW_RATE_SLOW>;
354			power-source = <IO_STANDARD_LVCMOS18>;
355		};
356
357		mux-cs {
358			groups = "spi0_ss_9_grp";
359			function = "spi0_ss";
360		};
361
362		conf-cs {
363			groups = "spi0_ss_9_grp";
364			bias-disable;
365		};
366
367	};
368
369	pinctrl_spi1_default: spi1-default {
370		mux {
371			groups = "spi1_0_grp";
372			function = "spi1";
373		};
374
375		conf {
376			groups = "spi1_0_grp";
377			bias-disable;
378			slew-rate = <SLEW_RATE_SLOW>;
379			power-source = <IO_STANDARD_LVCMOS18>;
380		};
381
382		mux-cs {
383			groups = "spi1_ss_0_grp";
384			function = "spi1_ss";
385		};
386
387		conf-cs {
388			groups = "spi1_ss_0_grp";
389			bias-disable;
390		};
391
392	};
393
394	pinctrl_uart0_default: uart0-default {
395		mux {
396			groups = "uart0_0_grp";
397			function = "uart0";
398		};
399
400		conf {
401			groups = "uart0_0_grp";
402			slew-rate = <SLEW_RATE_SLOW>;
403			power-source = <IO_STANDARD_LVCMOS18>;
404		};
405
406		conf-rx {
407			pins = "MIO3";
408			bias-high-impedance;
409		};
410
411		conf-tx {
412			pins = "MIO2";
413			bias-disable;
414		};
415	};
416
417	pinctrl_uart1_default: uart1-default {
418		mux {
419			groups = "uart1_0_grp";
420			function = "uart1";
421		};
422
423		conf {
424			groups = "uart1_0_grp";
425			slew-rate = <SLEW_RATE_SLOW>;
426			power-source = <IO_STANDARD_LVCMOS18>;
427		};
428
429		conf-rx {
430			pins = "MIO1";
431			bias-high-impedance;
432		};
433
434		conf-tx {
435			pins = "MIO0";
436			bias-disable;
437		};
438	};
439
440	pinctrl_usb0_default: usb0-default {
441		mux {
442			groups = "usb0_0_grp";
443			function = "usb0";
444		};
445
446		conf {
447			groups = "usb0_0_grp";
448			power-source = <IO_STANDARD_LVCMOS18>;
449		};
450
451		conf-rx {
452			pins = "MIO52", "MIO53", "MIO55";
453			bias-high-impedance;
454			drive-strength = <12>;
455			slew-rate = <SLEW_RATE_FAST>;
456		};
457
458		conf-tx {
459			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
460			       "MIO60", "MIO61", "MIO62", "MIO63";
461			bias-disable;
462			drive-strength = <4>;
463			slew-rate = <SLEW_RATE_SLOW>;
464		};
465	};
466
467	pinctrl_usb1_default: usb1-default {
468		mux {
469			groups = "usb1_0_grp";
470			function = "usb1";
471		};
472
473		conf {
474			groups = "usb1_0_grp";
475			power-source = <IO_STANDARD_LVCMOS18>;
476		};
477
478		conf-rx {
479			pins = "MIO64", "MIO65", "MIO67";
480			bias-high-impedance;
481			drive-strength = <12>;
482			slew-rate = <SLEW_RATE_FAST>;
483		};
484
485		conf-tx {
486			pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
487			       "MIO72", "MIO73", "MIO74", "MIO75";
488			bias-disable;
489			drive-strength = <4>;
490			slew-rate = <SLEW_RATE_SLOW>;
491		};
492	};
493};
494
495&psgtr {
496	status = "okay";
497	/* usb3, dp */
498	clocks = <&si5335_0>, <&si5335_1>;
499	clock-names = "ref0", "ref1";
500};
501
502&rtc {
503	status = "okay";
504};
505
506/* SD0 only supports 3.3V, no level shifter */
507&sdhci0 {
508	status = "okay";
509	no-1-8-v;
510	disable-wp;
511	pinctrl-names = "default";
512	pinctrl-0 = <&pinctrl_sdhci0_default>;
513	xlnx,mio-bank = <0>;
514};
515
516&sdhci1 {
517	status = "okay";
518	bus-width = <0x4>;
519	pinctrl-names = "default";
520	pinctrl-0 = <&pinctrl_sdhci1_default>;
521	xlnx,mio-bank = <0>;
522	non-removable;
523	disable-wp;
524	no-sd;
525	no-sdio;
526	cap-mmc-hw-reset;
527	cap-power-off-card;
528	mmc-pwrseq = <&sdio_pwrseq>;
529	vqmmc-supply = <&wmmcsdio_fixed>;
530	#address-cells = <1>;
531	#size-cells = <0>;
532	wlcore: wifi@2 {
533		compatible = "ti,wl1831";
534		reg = <2>;
535		interrupt-parent = <&gpio>;
536		interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */
537	};
538};
539
540&spi0 { /* Low Speed connector */
541	status = "okay";
542	label = "LS-SPI0";
543	num-cs = <1>;
544	pinctrl-names = "default";
545	pinctrl-0 = <&pinctrl_spi0_default>;
546};
547
548&spi1 { /* High Speed connector */
549	status = "okay";
550	label = "HS-SPI1";
551	num-cs = <1>;
552	pinctrl-names = "default";
553	pinctrl-0 = <&pinctrl_spi1_default>;
554};
555
556&uart0 {
557	status = "okay";
558	pinctrl-names = "default";
559	pinctrl-0 = <&pinctrl_uart0_default>;
560	bluetooth {
561		compatible = "ti,wl1831-st";
562		enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
563	};
564};
565
566&uart1 {
567	status = "okay";
568	pinctrl-names = "default";
569	pinctrl-0 = <&pinctrl_uart1_default>;
570};
571
572/* ULPI SMSC USB3320 */
573&usb0 {
574	status = "okay";
575	pinctrl-names = "default";
576	pinctrl-0 = <&pinctrl_usb0_default>;
577	phy-names = "usb3-phy";
578	phys = <&psgtr 2 PHY_TYPE_USB3 0 0>;
579	/delete-property/ reset-gpios;
580};
581
582&dwc3_0 {
583	status = "okay";
584	dr_mode = "peripheral";
585	maximum-speed = "super-speed";
586};
587
588/* ULPI SMSC USB3320 */
589&usb1 {
590	status = "okay";
591	pinctrl-names = "default";
592	pinctrl-0 = <&pinctrl_usb1_default>;
593	phy-names = "usb3-phy";
594	phys = <&psgtr 3 PHY_TYPE_USB3 1 0>;
595	reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;
596};
597
598&dwc3_1 {
599	status = "okay";
600	dr_mode = "host";
601	maximum-speed = "super-speed";
602};
603
604&watchdog0 {
605	status = "okay";
606};
607
608&ams_ps {
609	status = "okay";
610};
611
612&zynqmp_dpdma {
613	status = "okay";
614};
615
616&zynqmp_dpsub {
617	status = "okay";
618	phy-names = "dp-phy0", "dp-phy1";
619	phys = <&psgtr 1 PHY_TYPE_DP 0 1>,
620	       <&psgtr 0 PHY_TYPE_DP 1 1>;
621};
622
623&out_dp {
624	dpsub_dp_out: endpoint {
625		remote-endpoint = <&dpcon_in>;
626	};
627};
628